Low supply voltage high-performance CMOS current mirror with low

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Abstract—This paper presents a scheme for the efficient imple- mentation of a low supply voltage continuous-time high-perfor- mance CMOS current mirror with ...
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 51, NO. 3, MARCH 2004

Low Supply Voltage High-Performance CMOS Current Mirror With Low Input and Output Voltage Requirements J. Ramírez-Angulo, Fellow, IEEE, R. G. Carvajal, Member, IEEE, and A. Torralba, Senior Member, IEEE

Abstract—This paper presents a scheme for the efficient implementation of a low supply voltage continuous-time high-performance CMOS current mirror with low input and output voltage requirements. This circuit combines a shunt input feedback and a regulated cascode output stage to achieve low input resistance and very high output resistance. It can be used as a high-precision current mirror in analog and mixed signal circuits with a power supply close to a transistor’s threshold voltage. The proposed current mirror has been simulated and a bandwidth of 40 MHz has been obtained. An experimental chip prototype has been sent for fabrication and has been experimentally verified, obtaining 0.15-V input–output voltage requirements, 100- input resistance, and more than 200-M (G ideally) output resistance with a 1.2-V supply in a standard CMOS technology.





Index Terms—CMOS analog integrated circuits, current mirrors, low-voltage analog electronics.

I. INTRODUCTION

H

IGH-PERFORMANCE current mirrors with low input and output voltages are required as building blocks of mixed-mode VLSI systems that operate from a single supply of 1.5 V or below. High accuracy requires very high output resistance and low input resistance. Low-voltage operation requires low input and output voltages as well as low supply requirements for the control circuitry used to improve the mirror’s input and output resistance. The notation used in this paper will now be introduced. Only -MOS transistor current mirrors will be considered here without loss of generality, as the same considerations apply to -MOS transistors current mirrors by simply changing the polarity of currents and voltages. All the schemes discussed here use the structure depicted in Fig. 1, with two matched transistors M1 (input transistor) and M2 (output transistor) and additional circuitry. Notation in Fig. 1 is as follows. is the current mirror’s input voltage. • is the current mirror’s output voltage. •

Manuscript received June 15, 1999; revised August 15, 2000. This paper was recommended by Associate Editor M. Helfenstein. This work was supported by the National Science Foundation under Grant MIP-97110099, by the NASA Center for Autonomous Control Engineering, by the Spanish CICYT, and by the European Union (FEDER) under Grant 1FD97-0317. J. Ramírez-Angulo is with the Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM 88003-0001 USA (e-mail: [email protected]). R. G. Carvajal and A. Torralba are with the Departamento de Ingeniería Electrónica, Escuela Superior de Ingenieros, Universidad de Sevilla, Seville 41092, Spain (e-mail: [email protected]). Digital Object Identifier 10.1109/TCSII.2003.822429

Fig. 1.

General scheme for high-performance current mirror structure.

is the M2 drain voltage. is the supply voltage of the control circuitry used to improve mirror performance. Also, throughout the paper, the following definitions apply. • Upper index means quiescent conditions. means the minimum (max• Upper index imum) value that permits proper operation of the current mirror. is the threshold voltage of an unbiased transistor. • is the transistor’s threshold voltage increased by body • . Note that, as M1 and M2 have no body effect if transistors M1 and M2 are effect, properly matched. is the minimum drain–source saturation voltage, • • •



is the drain–source overdrive voltage. . is the maximum gain of a single-stage am• and are the small-signal transconducplifier, where tance gain and the output resistance of the MOS transistor, respectively. . • Low input impedance means For illustrative purposes typical values for a 2- m CMOS V, . For lowtechnology are assumed: voltage operation, the dimensions and bias currents of M1 and V and V. M2 are selected to achieve These values maintain M1 and M2 in saturation and allow a V V, maximum gate–source voltage swing assuming the drain–source voltage is kept constant. As many applications require the cascading of mirrors, a figure of merit for low-voltage operation is the voltage requirement in the signal path, which can be expressed by . Traditional techniques to improve a mirror’s performance have used architectures which , for instance, the consignificantly increased the value of , ventional cascode mirror is characterized by

1057-7130/04$20.00 © 2004 IEEE

RAMÍREZ-ANGULO et al.: LOW SUPPLY VOLTAGE HIGH-PERFORMANCE CMOS CURRENT MIRROR

(a)

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(b)

(c)

(d)

(e) Fig. 2. Previously reported high-performance current mirrors: (a) [3], (b) [4], (c) [5], (d) [6], and (e) [7].

. Several low-voltage CMOS and BiCMOS mirror implementations were reported in [1], [2]. These implementations make use of single ended and differential dc-level shifters to reduce input and output voltage requirements. All schemes for improving the input and output resistance of a mirror are based on specific implementations of shunt-input and series-output negative feedback amplifiers [3]–[7]. Assuming that the amplifiers used for this purpose have input and and respectively, then an output open-loop gains input resistance and an output resistance are obtained. The regulated cascode mirror to drive the [3] [Fig. 2(a)] uses an amplifier with gain cascode transistor. This leads to a high value of ( is the voltage gain of the cascode transistor M4) and consequently to a very high output resistance. The circuit in [4] [Fig. 2(b)] is similar to a regulated cascode current mirror whose input voltage is reduced by means of feedback. In this

circuit and in the circuit in [5] [Fig. 2(c)] the drain voltages , of the mirror transistors are compared to force thereby improving the accuracy of the current copy. The active-input regulated cascode scheme reported in [6] uses differential amplifiers on the input and output sides of the mirror [Fig. 2(d)]. Both amplifiers have one of their inputs connected . This scheme is characterized in to a reference voltage practice only by very high output resistance but it does not have low input resistance (see comments in Section III). The schemes in references [5] and [6] have also potential for low-voltage operation in the case that differential amplifiers with p transistors are used. Finally, in [7] [Fig. 2(e)] a current mirror is presented that achieves low input impedance with low input voltage requirements. This corresponds to a simple implementation of a shunt input scheme using a single-ended amplifier with only one transistor (M3) and one dc bias current source . Given that the bias current is mirrored onto the output

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 51, NO. 3, MARCH 2004

(a) (a)

(b) Fig. 3. (a) Proposed low-voltage high-performance current mirror. (b) Implementation of the differential amplifier A .

of the mirror, a current source on the input side at can be for some applications. (optionally) used to remove from This current source could alternatively be subtracted on the node at the mirror’s output. II. PROPOSED LOW-VOLTAGE HIGH-PERFORMANCE MIRROR SCHEME In the following, a simple and efficient implementation of the regulated cascode output section is discussed. This leads to a very high output resistance and accurate current copy. The implementation is shown on the right side of Fig. 3(a). In order to and , the differmake equal the values of voltages ential amplifier Ada in feedback configuration has been used. and of the two This improves accuracy given that the mirror transistors M1 and M2 are now equal. A low-voltage implementation of the differential amplifier is shown in Fig. 4 and consists of a differential pair (M5, M6) followed by a dc-level shifter (M7). The level shifter is only required in technologies where the N transistor threshold voltage is higher than the p transistor’s threshold voltage. The supply requirements of the am) are given by plifier (assuming

(3)

(b) Fig. 4.

Open-loop response analysis: (a) input side and (b) output side.

where is the threshold voltage of transistor M5 and a voltage is assumed for the current source . drop of As this determines the minimum supply re. For the numerical values quirements of the control circuit, given in Section I, the minimum supply voltage for the amplifier is 1.15 V, assuming V. Returning to Fig. 3(a), if M2 and M4 operate in saturated , the output resistance is given mode, , where denotes the gain of the by differential amplifier and denotes the gain of the cascode transistor M4. Assuming that both gains are of the same order of magnitude (50–100), then the output resistance range, although it is can theoretically take values in the due to drain-substrate limited in practice to only hundreds leakage currents at the drain of M4. For , the transistor M4 leaves the saturated mode and the open-loop gain of the output series feedback network is reduced to . In this case, a relatively high output resistance is still achieved. Even for , ( M1 and M2 operating in triode mode, similar to the cases reported in [5]–[7]) the mirror remains functional with . The final case is not of practical interest since in this mode of operation the drain currents are dependent both on gate–source as well as on drain–source voltages and

RAMÍREZ-ANGULO et al.: LOW SUPPLY VOLTAGE HIGH-PERFORMANCE CMOS CURRENT MIRROR

thereby the offset voltages of the differential amplifier can lead to relatively large gain errors. The proposed current mirror has advantages over any previously reported implementation, which is subject of the following discussion. The low-voltage scheme in [4] [Fig. 2(b)] also uses an amplifier to compare the drain voltages of the input and output mirror transistors as proposed here, but with some severe limitations. 1) It does not have low input impedance. 2) In order to maintain the mirror transistors in saturated mode, the input current swing must be severely constrained. 3) When operated in triode mode, no high output impedance can be achieved and poor gain accuracy results are proand duced since drain currents are dependent on both on . 4) To operate M1 and M2 in saturated mode in order to CMOS produce the high output resistance, a multiprocess with different threshold voltages for transistors is required. M4 and M2 5) This implementation only works with current-mode op-amps. The circuit in [5] [Fig. 2(c)] also uses an amplifier to compare the drain voltages of the mirror’s input and output transistors. This circuit is suitable for working as a low-voltage tail current source, but the maximum output resistance is limited by the internal impedance of the input current source. On the other hand, the very high output resistance of the mirror proposed here does not depend on the input source. The active-input regulated cascode current mirror in [6] [Fig. 2(d)] achieves very high output resistance and could be operated in low voltage, as the current mirror proposed here. However the input side loop has two high-impedance nodes and for this reason it always requires careful compensation to prevent oscillations or transient response with long settling times. This scheme does not directly compare the input and output nodes of the mirror but uses two op-amps. Hence, when compared with our implementation, it has higher power consumption, larger area requirements and and is also less accuracy. The difference between limited by the cumulative effect of the input offset and gain errors of two operational amplifiers. This degradation effect increases with increasing frequency or when the mirror transistors are operated in the triode mode. Finally, as the input stage is the one proposed in [7] [Fig. 2(e)], it has similar input performances, but the output stage of the proposed implementation is superior. Disadvantages are as follows. • In comparison to the conventional (and simpler) cascode and high-swing cascode mirrors the low-voltage operation and improved input and output resistance of the proposed mirror are accompanied by bandwidth/transient performance and equivalent input noise degradation, additional circuit complexity and power dissipation. Special care must be given to the design of the frequency compensating elements in the input and output loops in order to achieve a transient response without large overshot or long settling times (see Section III). Similar problems charac-

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terize all structures of Fig. 2 and in general many analog systems operating from low supply voltages. • Careful design of the biasing network is required in cases where the bias current of M3 requires to be removed from the current signal path (M1, M2, M4). This is done by including a dc current source Ib from the input node to ground. This source cannot be cascoded due to low input voltage requirements. III. STABILITY CONSIDERATIONS The proposed scheme [Fig. 3(a)] has weakly coupled negative feedback loops in both the input and output sides of the mirror. Stability analysis of Sections III and IV follows. Input Section: The shunt input scheme might require compensation as the open-loop gain of the internal feedback loop formed by M1 and M3, can be very high. Straightforward analysis based on the scheme of Fig. 4(a) shows that the input section loop has a Gain-bandwidth product and a nondominant pole given approximately by • • where , , are the parasitic capacitances at nodes “a” and “b”, is the capacitance between nodes “a” and “b” and is the small-signal transconductance gain of transistor Mi. A capacitance connected between the input node and the gate of the transistor M1 creates a dominant pole to higher frequencies and also shifts the nondominant pole [8]. This scheme might require the use of a resistance with value in series with the in order to shift the zero located in this case at to very high frequencies [8]. Another alternative for stability with large phase margin and without the utilization of a compensation capacitor , is to satisfy the , which leads to and condition . This is easily achieved by inclusion of the bottom source Ib mentioned in Section II. Output Section: Analysis of the output section [Fig. 4(b)] and nonleads to a gain-bandwidth product dominant high-frequency poles given approximately by: , and , respectively (two high-frequency zeros are neglected in this analysis). , , and are the parasitic capacitances at nodes “d”, “e,” and “f,” respectively. This section does not and require compensation if the conditions are satisfied. This condition is easily satisfied. SPICE Simulations: The frequency response of the current mirror was simulated with HSPICE using BSIM3.3 transistor models and the parameters of Table I. The models used for the simulations were those of a 2- m CMOS N-well MOSIS process, with nominal and transistor threshold voltages of 0.8 V and 0.75 V respectively. Equal bias currents and were used for transistors in the current path (M1, M2, and M4) and for transistors in the input and output control circuits. A single supply V and a load resistance k were selected. Fig. 5(a) and (b) shows simulated frequency and

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 51, NO. 3, MARCH 2004

TABLE I CURRENT MIRROR PARAMETERS

Fig. 6.

Low-voltage mirror experimental dc characteristic.

ventional (much simpler) two transistor mirror has an equivalent input noise of 4.6 pA Hz and a bandwidth of 120 MHz. From simulations the 1% settling time is approximately 0.23 s. IV. EXPERIMENTAL RESULTS

(a)

The circuit of Fig. 3 was fabricated and tested in the CMOS n-well MOSIS process with the parameters of 2Table I. Nominal p- and n-transistor threshold voltages in this technology are 0.8 and 0.75 V, respectively. The fabricated circuit included the bottom current source Ib of Fig. 3(a). The circuit parameters shown in Table I were selected in order to obtain quiescent drain–source saturation voltages and overdrive voltages of 0.1 V or less, allowing the operation of the control circuit with a supply of 1.2 V. The experimental dc output from 0 to characteristics were measured by sweeping 1.2 V and by stepping the input current from 4.2 A to 8 A using a curve tracer [Fig. 6]. The measured values for and were approximately constant and close to 145 mV. High output impedance 200 M was observed for voltages V and currents up to 10 A. Experimentally, the mirror remained functional even by using a supply voltage as low as 1 V. Large parasitic capacitances at the mirror’s output node precluded measurement of high-frequency characteristics. V. CONCLUSION

(b) Fig. 5. Low-voltage mirror simulated responses: (a) frequency response and (b) transient response.

transient responses, respectively. The bandwidth of the mirror is close to 40 MHz (a compensation capacitor of 1 pF was used). The simulated equivalent input white noise current was 6.9 pA Hz. Under similar conditions (same sizes and bias currents) bandwidth and noise characteristics for all other mirrors shown in Fig. 2 have comparable values while the con-

An efficient implementation of a low-voltage high-performance current mirror was introduced and experimentally verified. This scheme allows cascading mirrors with voltage requirements in the signal path down to just two times the minimum drain–source voltage of a saturated transistor, and improves the input and output resistances. The supply requirements of the mirror’s control circuitry are close to a transistor’s threshold voltage. No other current mirror topology has been reported with better input–output impedance characteristics, higher accuracy and comparable frequency response. The circuit can be used as a building block in low-voltage mixed-mode VLSI systems.

RAMÍREZ-ANGULO et al.: LOW SUPPLY VOLTAGE HIGH-PERFORMANCE CMOS CURRENT MIRROR

ACKNOWLEDGMENT The help of G. O. Ducoudray and A. Diaz-Sanchez in testing the circuits is gratefully acknowledged.

REFERENCES [1] J. Ramírez-Angulo, “Low voltage current mirrors for built-in current sensors,” in Proc. IEEE Int. Symp. Circuits and Systems, vol. 5, London, U.K., May–June 30–2, 1994, pp. 529–532. , “Current mirrors with low input and output voltage requirements,” [2] in Proc. 37th Midwest Symp. Circuits and Systems, Lafayette, LA, Aug. 3–5, 1994, pp. 107–110.

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[3] E. Säckinger and W. Guggenbühl, “A high swing, high impedance MOS cascode circuit,” IEEE J. Solid-State Circuits, vol. 25, pp. 289–298, Feb. 1990. [4] T. Itakura and Z. Czarnul, “High output-resistance CMOS current mirrors for low-voltage applications,” IEICE Trans. Fundam., vol. E80-A, no. 11, pp. 230–232, Jan. 1997. [5] F. You, S. H. K. Embabi, J. F. Duque-Carrillo, and E. Sánchez-Sinencio, “An improved current source for low voltage applications,” IEEE J. Solid-State Circuits, vol. 32, pp. 1173–1180, Aug. 1997. [6] T. Serrano and B. Linares-Barranco, “The active-input regulated cascode current-mirror,” IEEE Trans. Circuits Syst. I, vol. 41, pp. 464–467, June 1994. [7] V. Peluso, P. V. Coreland, M. Steyaert, and W. Sansen, “900 mV differential class AB OTA for switched op-amp applications,” Electron. Lett., vol. 33, no. 17, pp. 1455–1456, 1997. [8] P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, Third ed. New York: Wiley, 1993, ch. 9.4.