Low-Temperature Bonded GaN-on-Diamond HEMTs

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT)
REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < of the device) without impacting device channel temperature and reliability. State-of-the-art RF power of 11W/mm at 10GHz has been achieved with the new GaN-on-Diamond HEMT. A 3.6X improvement in power capability has also been demonstrated over the equivalent GaN-on-SiC HEMT.

with 3X more gate periphery within the same active area of the standard GaN-on-SiC HEMT. Shown in Figure 2 are layouts of

TABLE I COMPARISON OF DIAMOND-GROWTH AND DEVICE-TRANSFER GAN-ONDIAMOND APPROACHES

II. DEVICE DESIGN CONSIDERATIONS AND THERMAL ANALYSIS OF GAN-ON-DIAMOND DEVICES

Fig. 1. Device-transfer GaN-on-Diamond device approach. In this approach, GaN epi layer thickness is reduced, the AlN nucleation layer is eliminated and the SiC substrate is replaced with very high thermal conductivity diamond through a low-temperature bonding technique. With this design, the hot spot of the GaN device is within 1m of the diamond substrate, substantially reducing device thermal resistance.

Figure 1 shows the device-transfer GaN-on-Diamond device approach employed in this work. The mechanical mismatch in the device structure is reduced by performing the diamond bonding at a relatively low temperature, thus lowering stress due to coefficient of thermal expansion (CTE) mismatch between the diamond and GaN layers for low wafer bow and improved device reliability. The design of the new GaN-onDiamond HEMT also incorporates the following two key features that enable an improvement in power capability over the conventional GaN-on-SiC HEMT: a) elimination of thermal barriers by removal of the high-defect-density epi nucleation layer and 50-75% of GaN buffer thickness, and b) integration of diamond heat spreader by replacing the original epi substrate with the very high thermal conductivity CVD diamond. The proximity of the diamond substrate to the device heat source ensures efficient lateral heat spreading and vertical heat transfer. Table I compares the device-transfer GaN-onDiamond approach to the conventional diamond-growth one [15]. The new approach is superior to that of the conventional GaN-on-Diamond in the following areas: a) the use of higher performance industry standard GaN-on-SiC as starting epi, b) the use of higher thermal conductivity diamond, c) virtually no impact from CTE mismatch between GaN and diamond as a result of the low-temperature GaN/diamond bonding, and d) the high-yield “Device-First” GaN-on-SiC wafer fabrication. A. Design of RF and Thermal Test Devices By removing the AlN nucleation and GaN layers below the channel, the majority of the epi thermal barrier is eliminated. Attachment to existing high thermal conductivity diamond substrates provides an efficient heat spreader close to the device channel. This allows for a small-gate-pitch device structure that can provide higher RF power at reduced channel temperatures. To experimentally verify the improvement in power capability of the GaN-on-Diamond HEMT, small-gate-pitch device designs have been used to fabricate GaN-on-Diamond devices

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Diamond-Growth GaN-on-Diamond [1-5]

Device-Transfer GaN-onDiamond (This Work)

Starting epi

GaN-on-Si

GaN-on-SiC: higher performance GaN RF technology

Diamond substrate

Grown at a high temperature (>800ºC); severe GaN/diamond CTE mismatch - resulting in significant wafer bow

3X increase in device power capability.

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < B. GaN-on-Diamond Device RF Parasitics The microwave CVD diamond substrates used in the GaNon-Diamond approach have a low dielectric constant (5.7 vs 9.7 for SiC), reducing substrate loading effects. In terms of device layout, the small-gate-pitch design with the same active area dimensions introduces only a minor increase in phase difference from device center to device edge, which leads to a negligible degradation in RF combining efficiency. Device pulsed I-V collapse, kinks in device I-V and threshold voltage shift are commonly observed due to traps in a GaN HEMT. With the new GaN/diamond interface, it is important to understand the potential trapping related issues from the GaN/diamond interface in the GaN-on-Diamond HEMT. To investigate the trapping effect at the GaN/diamond interface, a modeling was performed. The simulation was based on the modification of the trapping effect models described in [6]. The traps at the diamond-GaN interface pin or nearly pin the Fermi level, leading to an electric field proportional to the difference between the pinned Fermi level position and the Fermi level position in the two-dimensional electron gas (2DEG) within the device channel. The value of the electric field caused by the surface traps can be estimated as FT ~ NTEg/NTo(ds+df), leading to the change in the electron density in the two-dimensional gas on the order of nsT = NTEg/qNTo(ds+df) and the corresponding threshold voltage shift VT = NTEg/NToCi(ds+df). Here NT and NTo are the surface trap density and the characteristic surface trap density (which determines the shift from the neutral level in the density of states distribution and is the model parameter),  is the dielectric permittivity of the GaN buffer, E g is the energy gap of the GaN buffer, ds is the buffer thickness, i.e. the distance between the device channel and the buffer-substrate interface, parameter df accounts for the electric fringing fields into ambient, and Ci =  /di is the gate-to-channel capacitance per unit area. Figure 3 shows the threshold voltage shift VT versus ds dependences for different values of NT (for NTo = 5x1012/cm2). The value of VT determines the current collapse and trapping transient effect induced by the traps at the buffer-substrate interface and should be kept at a small fraction of the gate voltage swing. It can be seen from Figure 3 that at a GaN/diamond interface trap density of ~1012/cm2, the impact of the trapping effect is insignificant in device threshold voltage shifting at channel/diamond separation of >0.5μm. In other words, the GaN/diamond bonding interface has negligible impact to device operation in terms of parasitic capacitance or parallel leakage at a target GaN epi thickness of >0.5μm. Guided by the simulations, the channel/diamond separation (i.e., GaN epi thickness) in the device fabrication was kept in the range ~0.5-1.0μm. C. Thermal Analysis of GaN-on-Diamond HEMTs Finite-element modeling has been performed using ANSYS 14.5 to compare the thermal performance of our novel GaN-onDiamond process to that of industry-standard GaN-on-SiC technology. The thermal model stack-up includes a GaN device chip that is solder-attached using AuSn to a carrier and module housing assembly. The GaN thickness on diamond is 1m thinner than that on SiC, which reflects the thickness reduction

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during the SiC substrate removal and GaN etching and polishing steps within the device transfer process. A substrate thickness of 100µm is assumed for both SiC and diamond in the simulation. The GaN-on-SiC device has a 4x100µm gate geometry, while that of the GaN-on-Diamond device is 12x100µm with compressed gate pitch to fit within the same

Fig. 3. Simulated threshold voltage shift of a GaN-on-Diamond device as a function of trapping density at the diamond/GaN interface. At a trap density of ~1012/cm2, the impact of trapping effect is insignificant (0.5μm.

physical area. This translates to a 3X increase in gate packing density for GaN-on-Diamond versus GaN-on-SiC. Power dissipation is assumed to be 8W per mm of gate periphery in both cases. For boundary conditions, an isothermal surface (25°C or 85°C) is applied to the underside of the module housing. To capture thermal effects from the sub-micron device junction to the larger-sized module package, a multi-tier modeling technique is employed with varying mesh density appropriate for thermal gradients within each modeled layer. Results of higher tiers serve as boundary conditions for the next lower tier, and iterations are performed to ensure consistency. An important aspect of GaN device thermal modeling relates to the thermal boundary at the GaN-substrate interface. For GaNon-SiC, we assumed an interface resistance that is representative of epitaxial nucleation layers on SiC substrates [7]. For GaN-on-Diamond, the interface is represented by a room-temperature thermal boundary resistance (TBR) value between 15 and 60m2K/GW, scaled by the temperaturedependence of bonding material thermal conductivity. Table II summarizes the key parameters used in the ANSYS finiteelement thermal model. Figure 4 shows the simulated temperature profiles for the GaN-on-SiC chip with 3.2W heat load and GaN-on-Diamond chip with 9.6W dissipation. Module baseplate temperature was held constant at 85°C. Assuming a room temperature TBR value of 30m2K/GW, the device on diamond was able to achieve a 16°C lower channel temperature even with the 3X high gate packing density and corresponding higher heat flux. This thermal improvement is a direct result of lower thermal resistance and better heat spreading in diamond. The improved spreading in diamond also minimizes the peak flux in the solder attach layer immediately below the substrate and thus limits its temperature rise. A similar advantage is obtained in GaN-onDiamond at the lower module baseplate temperature of 25°C, although the difference is smaller at 5°C.

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < Additional analysis was performed to investigate the impact of GaN/diamond TBR value on device channel temperature and to determine the TBR values required to match the temperatures of the GaN-on-SiC baseline at 25°C and 85°C baseplate temperatures, while assuming the same 3X higher power in GaN-on-Diamond. This was performed by analyzing GaN-onDiamond temperatures with varying TBR, plotting the results and extracting the TBR value at which the GaN-on-Diamond channel temperature with 9.6W dissipation equals that of the GaN-on-SiC baseline at 3.2W. At the lower base temperature of 25°C, the GaN/diamond TBR value that matches the channel temperature of GaN-on-SiC baseline is 36m2K/GW. At the higher base temperature of 85°C, the TBR value that matches GaN-on-SiC temperature is 44m2K/GW. The sensitivity of device channel temperature to TBR value was also studied. At the lower base temperature of 25°C, the sensitivity of channel temperature ranges from 0.8 to 1.1K per m2K/GW of GaN/diamond TBR. At the higher base temperature of 85°C, this sensitivity value is slightly higher at 1.0 to 1.3K per m2K/GW within the investigated TBR range of 15 to 60m2K/GW, meaning as TBR rises by 10m2K/GW, the corresponding GaN-on-Diamond channel temperature rise will be 8 to 13 degrees. This relatively low sensitivity of channel temperature to GaN/diamond TBR value suggests a practical tolerance exists for bonding interface quality without significant compromises in device performance and reliability. To understand the contribution from each component of the thermal stack-up, temperature rises in individual layers are plotted for both GaN-on-SiC and GaN-on-Diamond cases in Figure 5. The left plot shows the thermal rises with a baseplate temperature of 25°C, while the right plot shows the same for a baseplate temperature of 85°C. When the baseplate temperature is increased from 25°C to 85°C, the dependence of device channel temperature to TBR is reduced from 1.05°C to 0.85°C per unit TBR, indicating that TBR at the GaN/diamond interface plays a less significant role when device is operated at a higher baseplate temperature. For TBR below 30m2K/GW, the lower temperature rise in diamond more than compensates for the combined increases in carrier/housing, solder attach and nucleation/TBR. This effect is more significant at higher baseplate temperature, as seen in Figure 5. It is also clear from the bar charts that comparing to the GaN-on-SiC HEMT, the superior thermal properties of diamond in the GaN-onDiamond device offer a significant advantage in the substrate temperature rise even with 3X higher heat dissipation. In summary, finite-element thermal modeling has been performed for GaN device chips with 5:1 reduced gate pitch in typical RF module housing configuration. Assuming 3X higher gate packing density and thus 3X higher power dissipation on diamond, the GaN-on-Diamond devices are able to achieve comparable or lower channel temperature compared to industry-standard GaN-on-SiC devices when the TBR is ~35m2K/GW. This TBR requirement is further relaxed at higher baseplate temperatures. The modeling results indicate that superior power handling capability can be realized with this low-temperature device transfer GaN-on-Diamond process. This technology will in turn enable higher power RF sources in smaller footprints, and major reductions in system size, weight and power (SWaP) due to associated relaxation of prime power and cooling requirements.

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TABLE II SUMMARY OF ANSYS THERMAL ANALYSIS PARAMETERS GaN-on-SiC Device layout GaN thickness GaN thermal conductivity Substrate interface Substrate thermal conductivity Substrate thickness Normalized heat dissipation Total dissipation Die-attach Carrier/module Base temperature

GaN-on-Diamond

4 x 100µm 12 x 100µm ~2µm ~1µm K = 170W/mK* Nucleation layer TBR = 15-60m2K/GW* Kz = 473W/mK* Kz = 2,000W/mK* Kxy = 340W/mK* Kxy = 1,800W/mK* 100µm 8W/mm 3.2W 9.6W 25µm AuSn solder CuW/Al (total thickness > 4mm) 25°C, 85°C

* Values at room temperature

GaN-on-SiC 3.2W dissipation 260°C max temperature

GaN-on-Diamond 9.6W dissipation 244°C max temperature

295°C 275 255 235 215 195 175 155 135 115 95

Fig. 4. Temperature contours of modeled GaN-on-SiC and GaN-on-Diamond devices at 3.2W and 9.6W dissipation respectively. Module baseplate temperature is 85°C. At 3X higher power dissipation, the GaN-on-Diamond device achieves a maximum channel temperature of 244°C which is 16°C lower than that of the baseline GaN-on-SiC device. Quarter-symmetry is applied in these models to reduce computational time.

Fig. 5. Bar charts representing the individual layer temperature rise in the thermal stack-up for both GaN-on-SiC and GaN-on-Diamond. Results are shown for 25°C baseplate temperature (left) and 85°C baseplate temperature (right). GaN/diamond TBR values are listed for 15 to 60m2K/GW. Total power dissipation levels are 3.2W on SiC and 9.6W on diamond. The superior thermal properties of diamond offer a significant advantage in the substrate temperature rise even with 3X higher heat dissipation.

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REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < current transient results, the GaN-on-diamond HEMT is demonstrated to possess 3.6 times higher power capability than the industry-standard GaN-on-SiC device. The measured results – consistent with the device electrical and thermal analysis - clearly illustrate GaN-on-diamond HEMTs fabricated by low-temperature device-transfer technology exhibit superior electrical and thermal performance than the standard GaN-onSiC HEMTs. ACKNOWLEDGMENT This work was supported by DARPA NJTT program under the guidance of Dr. Avi Bar-Cohen, Dr. Joseph Maurer, Dr. Avinash Kane, Dr. Kaiser Matin and Dr. Jonathan Felbinger. The authors would like to thank Dr. Ivan Eliashevich of IQE/RF for GaN materials and Professor Ken Goodson and his group at Stanford University for thermal boundary resistance measurements. The earlier development of this technology by Dr. Felix Ejeckam and Dr. Daniel Francis of Group4 Labs and Dr. Marco Mendes of IPG Microsystems is much appreciated. The authors also would like to thank William Gouty and Karynn Sutherlin at AFRL for their assistance in providing device electrical and thermal measurements.

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G. H. Jessen, J. K. Gillespie, G. D. Via, A. Crespo, D. Langley, J. Wasserbauer, F. Faili, D. Francis, D. Babic, F. Ejeckam, S. Guo and I. Eliashevich, “AlGaN/GaN HEMT on diamond technology demonstration,” in Proc. IEEE Compound Semicond. Integr. Circuit Symp., San Antonio, TX, 2006, pp. 271–274. [2] J. G. Felbinger, M. V. S. Chandra, Y. Sun, L. F. Eastman, J. Wasserbauer, F. Faili, Dubravko Babic, D. Francis and F. Ejeckam, “Comparison of GaN HEMTs on diamond and SiC Substrates,” IEEE Electron Device Lett., vol. 28, no. 11, pp. 948–950, Nov. 2007. [3] F. Ejeckam, D. Francis, F. Faili, D. Babic, J. Felbinger, D. J. Twitchen and B. Bolliger, “GaN-on-Diamond: a brief history,” in Proc. 2014 IEEE Lester Eastman Conf., Cornell University, Ithaca, NY, Aug. 2014, pp. 15. [4] M. Tyhach, D. Altman, S. Bernstein, R. Korenstein, D. Francis, F. Faili, F. Ejeckam, J. Cho, K. Goodson, S. Kim and S. Graham, “Next generation gallium nitride HEMTs enabled by diamond substrates,” in Proc. 2014 IEEE Lester Eastman Conf., Cornell University, Ithaca, NY, Aug. 2014, pp. 6-9. [5] D.C. Dumka and T.M. Chou, “GaN-on-Diamond HEMTs: Road to maximum utilization of RF power capabilities of GaN,” presented at 2014 IEEE Lester Eastman Conf., Cornell University, Ithaca, NY, Aug. 2014. [6] A. Koudymov and M. Shur, “Non-ideal current transport in heterostructure field effect transistors,” International J. of High Speed Electronics and Systems, vol. 18, no. 4, pp. 935–947, 2008. [7] G. J. Riedel, J.W. Pomeroy, K.P. Hilton, J.O. Maclean, D.J. Wallis, M.J. Uren, T. Martin, U. Forsberg, A. Lundskog, A. Kakanakova-Georgieva, G. Pozina, E. Janzen, R. Lossy, R. Pazirandeh, F. Brunner, J. Wurfl, M. Kuball, "Reducing thermal resistance of AlGaN/GaN electronic devices using novel nucleation layers," IEEE Electron Device Lett., vol. 30, no. 2, pp. 103-106, Feb. 2009. [8] J. J. Komiak, K. Chu, and P. C. Chao, “Decade bandwidth 2 to 20 GHz GaN HEMT power amplifier MMICs in DFP and no FP technology,” in 2011 IEEE MTT-S International Microwave Symposium Digest, June 2011, pp. 1-4. [9] P. C. Chao, K. Chu and C. Creamer, “A new high power GaN-onDiamond HEMT with low-temperature bonded substrate technology,” in Proc. Int. Conf. on Compound Semicond. Manuf. Tech., New Orleans, LA, May 2013, pp.179-182. [10] J. Cho, P.C. Chao, M. Asheghi and K.E. Goodson, "Phonon conduction normal to polysilicon films on diamond," presented at ASME 4th

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Micro/Nanoscale Heat & Mass Transfer (MNHMT) International Conf., Hong Kong, China, Dec. 2013.

(M’82–SM’87–F’08) received his Ph.D. degree in EE from Cornell University. He is the Technical Director of the Microelectronics Center at BAE Systems, having responsibility of managing groups of engineers and scientists involving in advanced HEMT MMIC processing and reliability testing for applications at frequencies from 1 to 300 GHz. Technologies currently under development include MHEMT, GaN HEMT and GaAs high speed optoelectronics. Prior to BAE Systems, he was the CTO of WIN Semiconductors for 6” GaAs commercial foundry service in Taiwan, and the manager of the Advanced HEMT Process Development Group at GE / Martin Marietta / Lockheed Martin Electronics Laboratory, Syracuse, NY. He pioneered the use of low resistance T-gates in a HEMT, 6” GaAs PHEMT / 6” GaN MMIC processes for low cost commercial, and high performance GaN-on-GaN power HEMTs for military applications. He has more than 30 years of microwave experience. He has published more than 180 technical papers in the field of microwave devices and circuits. He was the Principal Investigator of DARPA WBGS-RF GaN and NJTT programs. He also served as the General Chair of the 2014 IEEE Lester Eastman Conference. He is a BAE Engineering Fellow. P.C. Chao

Second B. Author was born in Greenwich Village, New York City, in 1977. He received the B.S. and M.S. degrees in aerospace engineering from the University of Virginia, Charlottesville, in 2001 and the Ph.D. degree in mechanical engineering from Drexel University, Philadelphia, PA, in 2008. From 2001 to 2004, he was a Research Assistant with the Princeton Plasma Physics Laboratory. Since 2009, he has been an Assistant Professor with the Mechanical Engineering Department, Texas A&M University, College Station. He is the author of three books, more than 150 articles, and more than 70 inventions. His research interests include high-pressure and high-density nonthermal plasma discharge processes and applications, microscale plasma discharges, discharges in liquids, spectroscopic diagnostics, plasma propulsion, and innovation plasma applications. He is an Associate Editor of the journal Earth, Moon, Planets, and holds two patents. Mr. Author was a recipient of the International Association of Geomagnetism and Aeronomy Young Scientist Award for Excellence in 2008, the IEEE Electromagnetic Compatibility Society Best Symposium Paper Award in 2011, and the American Geophysical Union Outstanding Student Paper Award in Fall 2005.
