Low-Voltage and Low-Power CMOS Voltage-to-Current Converter

IEICE TRANS. ELECTRON., VOL.E87–C, NO.6 JUNE 2004

1029

LETTER

Special Section on Analog Circuit and Device Technologies

Low-Voltage and Low-Power CMOS Voltage-to-Current Converter Weihsing LIU† , Member and Shen-Iuan LIU†a) , Nonmember

SUMMARY A CMOS voltage-to-current converter in weak inversion is presented in this Letter. It can operate for low supply voltage and its power consumption is also low. As the input voltage varies from −0.15 V to 0.15 V, the measured maximum linearity error for the proposed voltageto-current converter, is about 3.35%. Its power consumption is only 26 µW under the supply voltage of 2 V. The proposed voltage-to-current converter has been fabricated in a 0.5 µm N-well CMOS 2P2M process. The proposed circuit is expected to be useful in analog signal processing applications. key words: low-voltage, low-power, voltage-to-current converter

1.

Introduction

In the past decades, the portable electronic systems have lead to the demand of the circuits which can operate with low supply voltages and low-power consumption [1]–[12]. Consequently, low-voltage and low-power consumption circuit techniques have become more and more important for modern electronic systems. In order to realize the low power circuits, one of the possible methods is to use MOSFETs in the weak inversion region. Many analog signal-processing circuits had been developed in literatures, such as the voltage-to-current (VTC) converter [13]–[15], current-mode multiplier/dividers, square-rooting circuits and other signal processing circuits [5], [9]–[12]. Among them, the VTC converters [13]–[15] had been widely used in analog signal processing, such as analog adder/subtractor [16], continuous-time filters, automatic gain control circuits, and four-quadrant multipliers. Based on the exponential characteristics of MOSFETs in weak inversion, some of them can achieve the requirements for low voltage and low power. Unfortunately, the VTC converters in weak inversion are rare. Therefore, the development of the VTC converter using MOSFETs in weak inversion is of certain interest. In this Letter, a low-voltage and low-power CMOS VTC converter is proposed to operate for a single supply voltage of 2 V while the power consumption is only 26 µW. The proposed circuits has been fabricated in a 0.5 µm N-well CMOS 2P2M process. The experimental results are given to demonstrate the proposed circuits.

Manuscript received October 21, 2003. Manuscript revised January 15, 2004. † The authors are with Graduate Institute of Electronics Engineering & Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan 10617, R.O.C. a) E-mail: [email protected]

2.

Circuit Implementation

2.1 Design Principle According to the Taylor’s series expansion, a general exponential function can be expressed as exp(x) ≈ 1 + x +

xn x2 x3 + + ···+ +··· 2! 3! n!

(1)

Supposed that x 1, the higher order terms of the Taylor’s series expansion can be neglected and Eq. (1) can be rewritten as exp(x) ≈ 1 + x +

x2 2

if

x1

(2)

According to Eq. (2), one can have exp(x) − exp(−x) ≈ 2x

(3)

The error between “exp(x) − exp(−x)” and “2x” is plotted in Fig. 1. The error can be less than 1% while |x| < 0.15. From Eq. (3), supposed that “x” is the input voltage and “exp(x) − exp(−x)” is the output current, a VTC converter can be realized. 2.2 Proposed VTC Converter Consider the circuit shown in Fig. 2 [16], [17] where Ib is a bias current. Assume that both M1 and M2 are perfectly matched and biased in the weak inversion region. The VI characteristics of the MOSFET in weak inversion can be given as [11] (VDD − V1 ) + (n − 1)(VDD − VB ) (4) Ib = ID0 · exp nUT

Fig. 1

The error between “exp(x) − exp(−x)” and “2x.”


1030

and

Fig. 2

3.

and

Proposed VTC converter.

(VDD − V2 ) + (n − 1)(VDD − VB ) I2 = ID0 · exp nUT

(5)

where n is the slope factor, UT = kT/q is the thermodynamic voltage, ID0 is the leakage current and VB is the body voltage of M1 and M2. From Eqs. (4) and (5), one can have (V1 − V2 ) I2 = Ib · exp (6) nUT According to Eq. (6), a voltage-mode exponential function circuit can be realized. For a MOSFET to operate in the weak inversion region, the drain current must comply with the following requirement [6]: ID < 2n

KpW 2 UT L

(Vb − Vin ) − Vc I4 = Ib · exp nUT Vb − Vc −Vin = Ib · exp · exp nUT nUT

(9)

Based on Eq. (3), the current Iout can be written as Vin Iout = I2 − I6 = I2 − I4 ≈ 2Ib · K · (10) nUT −V b c . From Eq. (10), a VTC converter can where K = exp VnU T be given and its gain can be adjusted by the bias voltages Vb and Vc . Since M1-M4 are biased in the weak inversion region, the power consumption can be very low. There are only two cascaded transistors, therefore the proposed VTC converter can operate for low supply voltage.

Basic exponential function circuit.

Fig. 3

(7)

The proposed VTC converter is shown in Fig. 3. Assume that M1-M4 are perfectly matched and are all biased in the weak inversion region. A current mirror, composed of M5 and M6, is used to copy the current I4 . If Vb and Vc are bias voltages and according to Eq. (6), the currents I2 and I4 can be expressed as (Vb + Vin ) − Vc I2 = Ib · exp nUT Vb − Vc Vin = Ib · exp · exp (8) nUT nUT

Experimental Results

The proposed low-voltage and low-power CMOS VTC converter has been fabricated in a 0.5 µm N-well CMOS 2P2M process. The die photograph of the proposed circuit is shown in Fig. 4. In the proposed circuit, all the PMOS transistors are embedded in their individual wells. The aspect ratios of the PMOS M1-M4 in the proposed VTC transistors and those of the NMOS tranconverter are WL = 11 µm 10 µmµm W sistors are L = 1 µm . The threshold voltage for the NMOS transistor is 0.78 V and that for the PMOS transistor is −1.1 V in our process and the supply voltage in the experiment is 2 V. The measured DC transfer curve of the proposed VTC converter is shown in Fig. 5. The experiments were performed with the bias voltage Vb =0.75 V, 0.8 V and 0.85 V, respectively. For the proposed circuit to work properly, M1 and M3 should be biased in weak inversion, therefore, according to Eq. (7), the bias current Ib was set to 0.1 µA. While the input voltage Vin varies from −0.15–0.15 V, the measured output oﬀset current is less than 0.9 nA under all situations. As the Ib was increased to 0.75 µA, the measured input range was reduced to −0.09–0.09 V. For an even higher bias current, the corresponding input range will be further reduced. Figure 6 shows the errors between the measured results and the theoretical values calculated by Eq. (10) which is defined by: error% =

measured value − theoretical value theoretical value × 100%

(11)

The maximum measured error was 3.35% which occurred at Vb =0.85 V and Vin = −0.15 V; however, most of the measured errors are less than 3%. According to Fig. 6, as the input voltage is increased, the measured errors is also increased. One of the reasons is due to the neglect of the higher order terms in Eq. (1). Another one is the larger input voltage will drive the MOS transistor into saturation,

LETTER

1031

Fig. 4

The die photo of the proposed VTC converter.

Fig. 7 Fig. 5

Measured THD vs. magnitude of Vin .

The measured DC transfer curve of the proposed VTC converter.

Fig. 8 Fig. 6 Errors between the measured results of the proposed VTC converter and the theoretical values.

therefore the leakage current from the drain to the substrate can no longer be neglected [17]. The THD of the output current as a function of the amplitude of the input voltage are shown in Fig. 7, which were measured with the bias current Ib = 0.1 µA, Vb = 0.8 V and 0.85 V, respectively. As the frequency of the input voltage is 10 kHz, the measured maximum THD is about 2.48%. The measured maximum power consumption for the proposed VTC converter is 26 µW which occurred at Vb = 0.85 V and Vin = 0.15 V. The frequency response of the proposed VTC converter is

Frequency response of the proposed VTC converter.

shown in Fig. 8, which was performed with the bias voltage Vb = 0.8 V, and the magnitude of the small signal was 0.01 V. The measured corresponding −3 dB bandwidth can be 704 kHz. 4.

Conclusions

In this Letter, a new design principle has been disclosed. Based on the design principle, a low-voltage and low-power CMOS voltage-to-current converter has been developed. Experimental results have been given to confirm the validity of the theoretical analysis. The proposed low-voltage and low-power VTC converter is expected to be useful in other


1032

analog signal processing applications. Acknowledgement This work is partially supported by National Science Council, Taiwan, Republic of China under Grant NSC 91-2626E-236 -002. The author Weihsing Liu is also with the faculty of the Department of Electronic Engineering, Tung Nan Institute of Technology. References [1] A. Toker and S. Ozoguz, “Analogue switch for very low-voltage applications,” Electron. Lett., vol.39, no.9, pp.175–176, Jan. 2003. [2] M.N. El-Gamal, K.H. Lee, and T.K. Tsang, “Very low-voltage (0.8 V) CMOS receiver front-end for 5 GHz RF applications,” IEE Proceedings- Circuits, Devices and Systems, vol.149, no.5/6, pp.355–362, Oct./Dec. 2002. [3] E. Tiiliharju and K. Halonen, “Current-folded mixer for upconversion applications,” Electron. Lett., vol.38, no.25, pp.1664–1666, Dec. 2002. [4] A. Motamed, C. Hwang, and M. Ismail, “A low-voltage low-power wide-range CMOS variable gain amplifier,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol.45, no.7, pp.800–811, July 1998. [5] M. Van Der Gevel and J.C. Kuenen, “Simple low-voltage weak inversion MOS 1/x circuit,” Electron. Lett., vol.30, no.20, pp.1639– 1640, Sept. 1994. [6] J. Pimentel, F. Salazar, M. Paheco, and Y. Gavriel, “Very-low-power analog cells in CMOS,” Proc. 43rd IEEE Midwest Symposium on Circuits and Systems, vol.1, pp.328–331, Aug. 2000. [7] C. Hung, K. Halonen, V. Porra, and M. Ismail, “Low-voltage, micropower weak-inversion CMOS GM-C filter,” Proc. third IEEE In-

[8]

[9]

[10]

[11]

[12]

[13]

[14] [15]

[16] [17]

ternational Conference on Electronics, Circuits, and Systems, vol.2, pp.13–16, Oct. 1996. F. Serra-Graells, “VLSI CMOS low-voltage log companding filters,” Proc. ISCAS 2000 Geneva, The 2000 IEEE International Symposium on Circuits and Systems, vol.1, pp.172–175, May 2000. √ M. Van Der Gevel and J.C. Kuenen, “ x circuit based on a novel back-gate-using multiplier,” Electron. Lett., vol.30, no.3, pp.183– 184, Feb. 1994. J. Mulder, A.C. Van Der Woerd, W.A. Serdun, and A.H.M. Van Boermund, “Application of the back gate in MOS weak inversion translinear circuits,” IEEE Trans. Circuits Syst. I, Foundam. Theory Appl., vol.42, no.11, pp.958–962, Nov. 1995. E.A. Vittoz, Micropower Techniques, in Design of MOS VLSI Circuits for Telecommunications, ed. J. France and Y. Tsivids, Prentice Hall, 1994. C.C. Chang and S.I. Liu, “Weak inversion four-quadrant multiplier and two-quadrant divider,” Electron. Lett., vol.34, no.22, pp.2079– 2080, Oct. 1998. C. Hung, M. Ismail, K. Halonen, and V. Porra, “A low-voltage railto-rail CMOS V-I converter,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol.46, no.6, pp.816–820, June 1999. B. Fotouhi, “All-MOS voltage-to-current converter,” IEEE J. SolidState Circuits, vol.36, no.1, pp.147–151, Jan. 2001. K. Bult and H. Wallinga, “A class of analog CMOS circuits based on the square law characteristics of an MOS transistor in saturation,” IEEE J. Solid-State Circuits, vol.SC-22, no.3, pp.357–365, June 1987. R. Fried and C. Enz, “Simple and accurate voltage adder/subtractor,” Electron. Lett., vol.33, no.1, pp.944–945, May 1997. J. Mulder, A.C. van der Woerd, W.A. Serdijn, and A.H.M. van Roermund, “Application of the back gate in MOS weak inversion translinear circuits,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol.42, no.11, pp.958–962, Nov. 1995.