than, or equal to, one. The current gain approach depends on using a current division network (CDN). [1] in the feedback of a fully differential buffer. (FDB) [2].
Low Voltage High Current Gain CMOS Digitally Controlled Fully Differential CCII Soliman A. Mahmoud Electrical Engineering Dept. Cairo University, Fayoum Branch, Egypt applications, digital control is more attractive [1], [1213]. In this paper, a digitally controlled fully differential second generation current conveyor (DCFDCCII) is presented, the DCFDCCII is based on using fully differential buffer FDB [2] with its output current sensed and copied to the current ports with a current gain where this current gain is digitally controlled. The current gain approach depends on using current division network (CDN) [1] in the feedback of the FDB to get current gain greater than, or equal to, one. The paper is organized as follows: In section II, the basic operation of the CDN and the idea of the current gain approach will be given. Then, the complete CMOS realization of the DCFDCCII will be given in section III. Finally, application of the DCFDCCII in realizing digitally programmable VGA will be given in section IV. The VGA employs only one DCFDCCII and all equal resistances and the gain tuning is achieved without any change of the external resistances.
Abstract— This paper presents a digitally controlled CMOS fully differential second generation current conveyor (DCFDCCII) with a current gain between terminals X and Z where this current gain is greater than, or equal to, one. The current gain approach depends on using a current division network (CDN) [1] in the feedback of a fully differential buffer (FDB) [2]. The presented DCFDCCII operates under low supply voltage of ±1.5V. Application of the DCFDCCII in realizing variable gain amplifier is also presented with the advantage of digitally tuned gain without any change of the circuit components. I. INTRODUCTION The second generation current conveyor (CCII) proposed by Sedra and Smith [3] is one of the most important and versatile current-mode building block currently available. Basically, a CCII is a three-terminal device derived by interconnecting a voltage and current follower. An ideal CCII exhibits infinite resistance at terminals Y and Z, and zero resistance at terminal X. The voltage at terminal X follows that at terminal Y, and the current at terminal Z is a replica of the current at terminal X. positive and negative CCIIs are defined according to the follow direction of the Z terminal current. Of course, a CCII- can be derived from a CCII+ by simply using current mirrors to invert the output current direction, and vice versa [4]. Since the introduction of the CCII, it has been used in wide range of applications and several circuit realizations have been proposed for its implementation (e.g., [5-10]). The CCII is a single ended device, however, fully differential circuit configuration recently have been widely used in high frequency analog signal applications [2]. As compared to their single-ended counterparts, they have higher rejection capabilities to clock-feed-through, charge rejection errors and power supply noises, larger output dynamic range, higher design flexibility, and reduced harmonic distortion [11]. Programmable characteristic of an analog cell is a key feature that is used in so many useful applications. Analog or digital tuning can be employed to control the parameters of the analog cell. However, in low voltage applications, there is a limitation on the allowable range of the analog tuning voltage. Hence, in these
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II. CURRENT GAIN APPROACH USING CURRENT DIVISION NETWORK (CDN) The symbol of the CDN presented in [1] is shown in Fig. 1. The n-bits CDN consists of n current division cells (CDCs) where each CDC has digital control bit ai. According to the current division principle, the input current (Ii) of the CDN is divided between the two output currents IO1 and IO2 as given in equation (1).
I O1 = αIi,
I O 2 = (1 − α )Ii
(1)
Where α is the current gain of the CDN and given by:
α=
I O1 1 i =n−1 i = 1 + ∑ 2 ai Ii 2 n i =0
(2)
Fig. 1: Symbol of the CDN.
Hence, the current gain (α) of the CDN is digitally controlled where α is less than, or equal to, one. The basic idea of using the CDN with current gain greater than, or equal to, one is shown in Fig. 2. It
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depends on injecting the input current in the first outputnode of the CDN and receiving it from the input node (i.e., exchanging the input/output nodes). Using equation (2), the new current equations of the CDN in Fig. 2 will be written as follows:
I O1 =
Ii
α
=
2 n Ii 1 +
2 ai ∑ i =0
i = n −1
0.5µm CMOS parameters. n=6 for the CDN and the power supply is balanced (±1.5V). The current at node Z1 is shown in Fig. 4 when node X is driven by current IX while VY=0 and Z terminals are loaded by RZ1=RZ2=1KΩ for current gain setting of 1, 2, 4, 8, and 16 (α =1, 1/2, 1/4, 1/8, and 1/16 respectively). The input impedance at node X for the same gain setting is shown in Fig. 5. The X-terminal voltage is tested in Fig. 6 by sweeping VY from -0.75 to 0.75V at α =1 and X terminal is loaded by RX=10KΩ.
(3)
i
Fig. 2: Basic Idea of the Current Gain Approach.
I O2 =
(1 − α ) Ii
(4)
α
Hence, the current gain at IO1 will be 1/α which is greater than, or equal to, one. To realize this idea, an input stage is required to represent low input impedance at the current injection node since the output nodes of the CDN itself are high impedance nodes [1]. Also, an output stage is required to sink (or source) the required current as equation (3) indicates. Finally, it is worth note that an attractive output current is available at node IO2 where the current gain ((1-α)/α) can be used for either attenuation (at α ≥0.5) or amplification (at α ≤0.5). The complete CMOS realization of the idea is shown in Fig. 3 based on the voltage buffer given in [14]. The required output stage is formed by transistors M9-M12 representing class AB push-pull output stage where the standby current is adjusted using transistors M21-M23. Transistors M13 and M14 sense the current of the output stage and transfer it to the output node Z1. Transistors M1-M5 represent the required input stage. The matched transistor M1 and M2 operate in the saturation region and carry equal current due to the tail biasing transistors M3-M5. Hence, the voltage at node X is forced to follow that of node Y and the input impedance at node X is expected to be very small. Therefore, the complete circuit represents a singleended digitally controlled current conveyor (DCCCII) with two Z-terminals and the matrix equation representing its operation is as follows:
0 0 1 I X 0 0 0 VZ 1 0 0 0 VZ 2 V Y 0 0 0
160uA
= 16
= 8
100uA
IIZ1Z1 [dB] [µA]
= 4 = 2 0A
Current Gain = 1
-100uA
-160uA -20uA
I(RZ1)
-10uA
0A
10uA
20uA
IX
Fig. 4: Z1-Current of the DCCCII at Different Gain Setting.
RinX [Ω]
40
20 Current Gain = 16 = 8 = 4 0
= 1
-20 -10uA
-5uA -D(V(X))
0A
5uA
10uA
IX
Fig. 5: Simulated Input Resistance at Node X of the DCCCII.
750mV
500mV
(5) VX [V]
0 VX 1 I Z1 α I = (1 − α ) Z2 I α Y 0
Fig. 3: CMOS Realization of the Single-Ended Digitally Controlled CCII with Current Gain Greater than One.
Hence, the current gain at node Z1 is greater than, or equal to, one. Simulations were carried out to check the performances of circuit in Fig. 3 using PSPICE and
0V
-500mV
-750mV -750mV V(X)
-400mV
0V
400mV
VY
Fig. 6: DC Response at Node X of the DCCCII.
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750mV
(a) Fig.7: Circuit of the DCFDCCII.
(b) (a) CMOS Realization.
Fig. 9 shows the AC response of the Z1-terminals voltage of the DCFDCCII at α =1. The Y-X transfer characteristic is shown in Fig. 10 where the differential X-terminals voltage is shown versus the differential Y input.
III. REALIZATION OF THE DCFDCCII USING CURRENT GAIN APPROACH The complete CMOS circuit of the DCFDCCII is shown in Fig. 7(a) based on the current gain approach discussed above and using fully differential buffer FDB [2]. The FDB is consisting of two matched differential pairs (M1-M2) and (M3, M4), matched biasing currents sources transistors (M7, M8), matched active load transistors (M5-M6), and two class AB output stages (M9-M12, and M15-M18, and the biasing of the output stage M21-M23). The differential input is applied to the two high impedance terminals of the NMOS transistors M2 and M3. The tail current transistors M7 and M8 carry equal bias current IB and IM2=IM3 by the current mirror action of transistors M5 and M6. Hence, the two matched differential pairs carry equal differential and common mode current values. Therefore: (6) (VX + ) − (VX − ) = (VY + ) − (VY − ) Transistors M13-M14 and M19-M20 are used to copy the current of the class AB output stages of the FDB and transfer it to the Z1 port. Considering the current relations of the CDN and the current gain approach discussed previously, it can be shown that the DCFDCCII has two fully-differential Z-terminals and the matrix equation representing its operation is as follows:
0 V Xd 1 I Z 1d α I = (1 − α ) Z 2d I α Yd 0
0 0 1 I Xd 0 0 0 VZ 1d 0 0 0 VZ 2 d V Yd 0 0 0
(b) Symbol.
(VZ1+)-(VZ1-) [V]
400mV
0V
-400mV -25mV
-20mV -10mV ((V(Z1+)-V(Z1-)))
0V
10mV
20mV
25mV
VYd
Fig. 8: DC Response of the Differential Z1-Voltage of the DCFDCCII.
(VZ1+)-(VZ1-) [dB]
0
-20
-40 1.0KHz 4.0KHz 11KHz 30KHz DB(V(Z1+)-V(Z1-))
90KHz
300KHz 1.0MHz
4.0MHz 11MHz 30MHz
90MHz
300MHz
Frequency
Fig. 9: AC Response of the Differential Z1-Voltage of the DCFDCCII.
(7)
1.0V
(VX+)-(VX-) [V]
Where, VXd = (VX+)-(VX-), VYd = (VY+)-(VY-), IZ1d = (IZ1+)-(IZ1-), IZ2d = (IZ2+)-(IZ2-), IXd = (IX+)-(IX-), and (IY+) = (IY-) = 0. The CMOS circuit in Fig 7(a) has been simulated using PSPICE. The Y-Z1 transfer characteristics are shown in Fig. 8 and Fig. 9. In Fig. 8, the differential Z1terminals voltage is shown versus the differential Y input for gain setting of 1, 2, 4, 8, and 16 (α = 1, 1/2, 1/4, 1/8, and 1/16 respectively) when all X and Z terminals are loaded by equal resistance R=10KΩ.
0V
-1.0V -1.0V V(X+)-V(X-)
-0.5V
0V
0.5V
1.0V
VYd
Fig. 10: DC Response of the Differential X-Voltage of the DCFDCCII.
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IV. DIGITALLY PROGRAMMABLE VGA
REFERENCES
The circuit of the VGA is shown in Fig. 11. The VGA employs only one DCFDCCII and all-equal resistors. Using direct analysis and equation (7), the two output voltages of the VGA, VZ1d and VZ2d, are given by the following equation:
[1] M. A. Hashiesh, S. A. Mahmoud, A. M. Soliman, “Digitally controlled CMOS balanced output transconductor based on novel current-division network and its applications,” The 47th IEEE International Midwest Symposium on Circuits and Systems, MWCAS2004, Hiroshima, Japan, vol. III, pp. 323-326, July 25-28, 2004. [2] S. A. Mahmoud, “Low voltage fully differential CMOS current feedback operational amplifier,” The 47th IEEE International Midwest Symposium on Circuits and Systems, MWCAS2004, Hiroshima, Japan, vol. I, pp. 49-52, July 25-28, 2004. [3] A. Sedra and K. Smith, “A second-generation current conveyor and its applications, ” IEEE Trans. Circuit Theory, vol. CT-17, pp. 132-134, Feb. 1970. [4] R. Mita, G. Palumbo, and S. Pennisi, “1.5-V CMOS CCII+ with high current-drive capability,” IEEE Trans. Circuit Syst. II, vol. 50, pp. 187-190, April 2003. [5] H. O. Elwan and A. M. Soliman, “Low-voltage lowpower CMOS current conveyor, ” IEEE Trans. Circuit Syst. I, vol. 44, pp. 828-835, Sept. 1997. [6] I. A. Awad and A. M. Soliman, “New CMOS realization of the CCII-,” IEEE Trans. Circuit Syst. II, vol. 46, pp. 460-463, April 1999. [7] A. M. Ismail, and A. M. Soliman, “Low-power CMOS current conveyor,” Electron. Lett., vol. 36, pp. 7-8, Jan. 2000. [8] A. El-Adawy, A. M. Solimam, and H. O. Elwan, “A novel fully differential current conveyor and applications for analog VLSI,” IEEE Trans. Circuit Syst. II, vol. 47, pp. 306-313, April 2000. [9] A. M. Ismail, and A. M.Soliman, “CMOS-CCII realization based on the differential amplifier: A review,” Frequenz, vol. 54, pp 182-187, July-Aug. 2000. [10] H.-W. Cha, and K. Watanabe, “Wideband CMOS current conveyor, ” Electron. Lett., vol. 32, pp. 1245-1246, Jully 1996. [11] D. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997, ch. 6. [12] S. A. Mahmoud, and I. A. Awad, “Digitally controlled balanced output transconductor and applications,” 15th International Conference On Microelectronics, ICM03, Cairo, Egypt, pp.211214, Dec. 9-11, 2003. [13] A. A. El-Adawy, A. M. Soliman, and H. O. Elwan, “Low voltage digitally controlled CMOS current conveyor,” Int. J. Electron. Commun., vol. 56, pp. 137-144, 2002. [14] H. Elwan, and M. Ismail, “CMOS low noise class AB buffer”, Electronics Letters, vol. 35, pp.18341836, Oct. 1999.
VZ 1d =
VZ 2 d =
1
α
(8)
VYd
1−α
α
(9)
VYd
Fig. 11: DCFDCCII-Based VGA Circuit.
Therefore, the gain at terminals Z1 is greater than, or equal to, one while the gain at terminals Z2 may be greater than one (α≤0.5) or less than one (α≥0.5). The gain-tuning is achieved without any change of the external passive elements. Fig. 12 shows the simulation of the VGA with dBlinear gain setting from 0 to 24 dB in 6 dB step.
Voltage Gain [dB]
30
20
10
0 -25mV
-20mV -10mV DB(D(V(Z1+)-V(Z1-)))
0V
10mV
20mV
25mV
VYd
Fig. 12: dB-Linear Gain of the VGA in 6dBs Gain Step.
V. CONCLUSION In this paper, a digitally controlled fully differential current conveyor (DCFDCCII) has been presented. A current division network (CDN) has been used to provide a current gain between terminals X and Z of the DCFDCCII. The CDN has been used in a feedback configuration with a fully differential buffer to provide a digitally controlled current gain between terminals X and Z greater than, or equal to, one. Application of the DCFDCCII in realizing variable gain amplifier (VGA) has been given. The presented blocks have been confirmed using PSPICE simulation.
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