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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 6, JUNE 2001
Low-Voltage Low-Power Accurate Extractor CMOS George Fikos and Stilianos Siskos
Abstract—Circuits extracting a MOSFET’s threshold voltage belong to the general category of bias circuits. Since these circuits do not process signal inputs, their power consumption should be low, while preserving high accuracy and robustness of the output against supply voltage variations and transistor mismatch. In this brief, a low-voltage low-power extractor is proposed. By utilizing novel self-biased analog CMOS extracting block, the extractor feedback on a simple low-voltage presents less than 0.3% error for wide supply voltage range, and achieves low-power consumption and self-compensation for second-order effects and mismatch. These features are supported by simulation results. Index Terms—Analog VLSI, CMOS, low-power circuits, low-voltage cirextractors. cuits,
I. INTRODUCTION The threshold voltage VT of a MOSFET is a useful quantity for transistor characterization, temperature measurement, and compensation. Producing this quantity can be necessary, for canceling itself out in several V –I and I –V conversion circuits [1] and for producing correct bias conditions [2]. It can also be exploited in the emerging field of low voltage and/or low power circuits through level shifting [3]. VT extractors’ power consumption is a major factor that cannot be neglected in modern analog circuit design. Portability of circuits requires battery operation and therefore, low-voltage criteria and supply voltage independence should both be satisfied. Prior implementations either did not deal with these aforementioned aspects of design [4]–[8], or consider the supply dependence of the output neglectable by using technology with small channel length modulation factor ( 0:001 V01 ) [9], several decades less than the one used in this implementation ( 0:05 V01 ). The proposed low-voltage low-power self-biased VT extractor combines a simple low voltage VT extracting block and novel feedback, to achieve independence of the output from the supply voltage, low current consumption (therefore, low power consumption), accuracy of the extracted threshold voltage toward supply voltage variations and compensation of body effect and transistor mismatch. The above-mentioned advantages are confirmed through comparative simulations against representative prior implementations [5], [6], for several analog technologies. II. CIRCUIT DESCRIPTION AND ANALYSIS The proposed extractor (Fig. 1), consists of three blocks: 1) a simple VT extracting block; 2) an offset generator; and 3) the current feedback loop. A. Analysis of the VT Extracting Block Assuming that all transistors of this block operate in saturation (4VT N 0 V 2VTN 0 ), with the ratios of (W/L) shown in Fig. 1 (K1 = K2 = K3 = K4 =4 = k ), body effect not being considered
Manuscript received July 2000; revised June 2001. The work of G. Fikos was supported by a scholarship from the State Scholarships Foundation of Greece. This paper was recommended by Associate Editor G. Cauwenberghs. The authors are with the Electronics Laboratory, Department of Physics, Aristotle University of Thessaloniki, Thessaloniki 54006, Greece. (e-mail:
[email protected]). Publisher Item Identifier S 1057-7130(01)07505-X.
Fig. 1.
Proposed V extractor.
(VBSi = 0), and assuming that the drain current of each mosfet follows the simple quadratic law
IDi
= Ki (VGSi 0 VTN 0 )2
(1)
then
= ID2 (1) )VS = V =2 (1)^(2) ID3 = ID4 ) VO = VTN 0 : ID1
(2) (3)
Since V 2VTN 0 , the VT extracting block has the ability of operating under low supply voltage. 1) Channel Length Modulation and Mobility Reduction: The drain current of each transistor, considering channel length modulation () and mobility reduction ( ), is modulated from (1) to the more realistic expression
= Ki (1 + VGSi )01 (VGSi 0 VTN 0 )2 (1 + VDSi ): (4) Substituting (4) on ID1 = ID2 and ID3 = ID4 , results in the same IDi
solution (2) for VS and
K [1 + (V 0 VO )]01 (V 0 VO 0 VTN 0 )2 [1 + (V = 4K (1 + VO )01 (V =2 0 VTN 0 )2 (1 + VO ):
0 VO )] (5)
Solution of (5) results in VO being a function of VTN 0 ; V; and . But VO can become independent on and and still being given by (3) by forcing (through proper feedback)
V
= 2VO :
(6)
2) Body Effect: In the case of n-well technology, M1 and M3 have VBS 6= 0 and, therefore, their threshold voltages will follow (7):
VTN
= VTN 0 +
p
28b + jVBS j 0 28b
:
(7)
In this case, the equation producing VO can be reached as follows:
ID1
ID3
^(7)V = ID2 (1)) S p p = V 0 28b + VS 0 28b
2
= ID4 (1)^(7) )^(8)VO p p = VTN 0 + 28b + VS 0 28b + VO
1057–7130/01$10.00 © 2001 IEEE
(8)
:
(9)
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 6, JUNE 2001
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TABLE I SIMULATION RESULTS
Solution of (9) generally differs from the desired output (3). But (3) can still be valid through body effect compensation, by forcing VS VO in (9), or equivalently (substituting VS VO in (8) and solving for V )
=
= p p (10) V = 2V + 28 + V 0 28 : 3) Geometric Mismatch: Mismatch between M1 ; M ; M ; M through transconductance parameters K ; K + 1K ; K ; 4(K + 1K ), respectively, is considered. Substituting (1) on I = = I , using the approximations: (1 + x) I ;I 1 + x=2; (1 + x)0 1 0 x, and keeping first-order terms, produces V =V + (V 0 V =2)[1K =K 0 1K =2K ]: (11) O
O
b
b
2
1
1
1
2
2
D2
D3
O
3
4
2
D1 1=2
D4
1
T N0
T N0
2
2
1
1
Equation (11) shows a first-order approximation on the detrimental effect of transconductance mismatch, but if—under proper feedback—(6) becomes valid, then mismatch is compensated (up to first order) and the desired output (3) is still achieved. 4) Validity of the Quadratic Drain Current Expression: Due to subthreshold current, (1) is valid for values of VGSi > VT N 0 kT =q [10]. Generally the gate overdrive voltage VGSi 0 VT N 0 should be at least several UT kT =q greater than VT N 0 for strong inversion equations being really dominant, since VT N 0 is an extrapolated value from 1=2 the curve ID f VGS , for values of VGS far beyond VT N 0 . So, for strong inversion operation
+3
VS
= = (
)
V
+V
T N0
OFF
, V 2V
T N0
+ 2V
OFF
(12)
where VOFF is several UT . Biasing of the transistor at the exact value of VGS where the max1=2 imum slope of the ID f VGS curve occurs, plays a critical role in the accuracy of prior implementations. A prior design [8], achieves the aforementioned bias condition with the use of two differential difference amplifiers (DDA), at the expense of area and power consumption. 5) Conclusions of VT Extracting Block’s Analysis: The undesired sensitivity of the output to second-order effects could be compensated through voltage V , implementing (6) for ; and transconductance mismatch compensation, or (10) for body effect compensation. Considering the above, along with (12) for strong inversion operation, realistic compensation for all second-order effects can be achieved if
= (
)
= 2V + 2V
V
O
OFF
(13)
where
2U
T
8
< VOFF < UT :
(14)
B. Analysis of the Offset Generator In the attempt to implement the feedback shown in (13), an offset should be added to VO . The offset generator takes VO as input and adds an offset of several UT on this value. Considering that VO is very near to VT N 0 , then VGS 5 0 VT N 0 < kT =q , so taking [10] into consideration, subthreshold drain current equations are more realistic to use in order to calculate this block’s output, VOGEN
3
= I ) aI e
aID5
D8
0
V
=U
=
I0 e(V
)=U
=b
= V + U ln(ab) (15) = K =K is the p-mirror current gain and b is the =K . Since M and M operate in the boundaries of )V
OGEN
O
T
where a M7 M6 ratio KM5 M8 5 8 subthreshold and strong inversion regions, (15) is not very accurate. Additively, possible mismatch in the offset generator can be incorporated in the inaccuracy of (15). The important point is that all the above, however, are not crucial for the extractor’s operation because accuracy in the value of VOGEN is not an issue, due to inequality (14). C. Analysis of the Feedback Block Transistors M9 and M4 (Fig. 1) are 5 and 4 times wider than M2, respectively, and due to the current mirror formed by M10 and M11, VOGEN is fed back to VS as follows:
ID9
= I + I )V = V =2V + 2U ln(ab): D2
D4
O
(1)
S
^ )
(2) (15)
OGEN
V (16)
T
So, the proposed extractor implements (16), corresponding to (13), resulting in a very accurate, robust extraction of the threshold voltage. To justify the low-voltage low-power characterization of the overall circuit, the supply voltage limitations and the total current consumption are calculated
VDD
V +V
IDD
DSp; sat
= 2V + 2V + 5K =K V = I + I + I + I = 11K V
(13)
T N0
D2
OFF
D4
D8
2
D9
11
(17)
OFF
2
2 OFF
:
(18)
Equation (18) also shows that for a fixed supply voltage VDD , the total current consumption, and therefore power consumption, can be linearly controlled through scaling of the devices.
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 6, JUNE 2001
III. SIMULATION RESULTS The first set of simulations compares the accuracy of the output regarding the nominal threshold given by SPICE MOSFET models, sweeping the supply voltage VDD , for three different technologies and for three different VT extractors, the proposed one, [5] and [6]. The results are shown in Table I. It is seen that in previous implementations, VDD affects the output so heavily through channel length modulation and mobility reduction, that accuracy comparisons with the nominal VTN 0 value become meaningless. In the proposed implementation, these effects are compensated, resulting in greatly reduced dependency of the output on VDD and high accuracy, differing—in the worst case of AMS 1.2 —less than 0.3% from the SPICE nominal value. The presented independence on VDD makes the circuit’s output more trustworthy. As far as operation under low voltage supply is concerned, the minimum VDD for correct operation is significantly reduced, confirming (17), VDD min 2VTNO + 100 mV. Reduced sensitivity of the total current consumption on VDD is also presented, supporting (18). In all cases, less power consumption than the compared circuits is achieved. Another simulation, tests the accuracy of the proposed extractor including body effect, using the MIETEC 2.4- technology. Sweeping VDD from 2 to 5 V results in the maximum deviation of VO from the nominal VTN 0 being less than 1.5%. The compensation achieved in this case does not have excellent results because the implemented equation (16) is similar but not identical with the one needed for ideal body effect compensation, (10). The effect of mismatch on the output is simulated through Monte Carlo analysis. Mismatch is considered on all devices, including current mirrors in contrast to [7]. Using a uniform distribution for transcoductance values, with deviation of 65% on the nominal values of transcoductances (Ki ) (Fig. 1), the deviation of the output from the nominal VTN 0 is less than 0.6%, and is mainly caused by the excess voltage VOFF 70 mV, in (11). These results support (11), so the proposed structure is proved robust against transistor mismatch. Finally, the linear dependence of the output on temperature, reported on [11], is confirmed by sweeping temperature from 0 to 100 C with a fixed VDD value, producing a linear dependence of the output on temperature with (dVO =dT ) = 1:183 mV/ C and maximum deviation from linearity less than 0.14%, presenting significant thermometric capabilities.
[4] N. Manaresi, E. Franchi, A. Gnudi, and G. Baccarani, “MOSFET threshold extraction circuit,” Electron. Lett., vol. 31, no. 17, pp. 1434–1435, Aug. 1995. [5] M. G. Johnson, “An input-free V extractor circuit using a two-transistor differential amplifier,” IEEE J. Solid-State Circuits, vol. 28, pp. 704–705, June 1993. [6] I. M. Filanovsky, “An input-free V extractor circuit using a series connection of three transistors,” Int. J. Electron., vol. 82, no. 5, pp. 527–532, 1997. [7] C. G. Yu and R. L. Geiger, “An accurate and matching-free threshold voltage extraction scheme for MOS transistors,” in Proc. IEEE Int. Symp. Circuits and Systems, vol. 4, May 1994, pp. 115–118. [8] U. Cilingiroglu and S. K. Hoon, “An accurate self-bias threshold voltage extractor using differential difference feedback amplifier,” in Proc. IEEE Int. Symp. Circuits and Systems, vol. 5, May 2000, pp. 209–212. [9] Z. Wang, “Automatic V extractors based on an n n MOS transistor array and their application,” IEEE J. Solid-State Circuits, vol. 27, pp. 1277–1285, Sept. 1992. [10] S. Collins, D. R. Brown, and G. F. Marshall, “An analog vector matching architecture,” Anal. Integr. Circuits Signal Process., vol. 8, pp. 247–257, 1995. [11] Y. P. Tsividis, Operation and Modeling of the MOS Transistor, 1st ed. New York: McGraw Hill, 1987.
2
Analysis of DCTLMS Algorithm With a Selective Coefficient Updating S. Attallah and S. W. Liaw
Abstract—Recently, a fast version of LMS algorithm where only a small subset of the coefficients is updated at each iteration has been published in the literature. In this brief, we analyze the effects of this technique on the discrete cosine transform domain LMS (DCTLMS) algorithm, and highlight its advantages and drawbacks. It will be shown, in particular, that a reduction in the computational complexity can be achieved without causing any degradation to the steady state error of the algorithm. The analytical results are then confirmed by simulations where real speech and first-order Markov signals are used. Index Terms—Computational complexity, DCT transform-domain LMS, partial update.
I. INTRODUCTION IV. CONCLUSION The proposed self-biased extractor utilizes novel feedback on a simple low-voltage VT extracting block, achieving: 1) ability of operation under low supply voltage; 2) low current consumption, independent of the supply voltage due to self-biasing; therefore, 3) low power consumption; and 4) extreme accuracy and robustness of the output due to immunity to VDD variations through second-order effects and mismatch self-compensation. The above features were confirmed through SPICE simulations.
REFERENCES [1] S.-I. Liu and C.-C. Chang, “A CMOS square-law vector summation circuit,” IEEE Trans. Circuits Syst. II, vol. 43, pp. 520–524, July 1996. [2] G. Fikos and S. Siskos, “Analogue CMOS vector normalization circuit,” Electron. Lett., vol. 35, no. 25, pp. 2197–2198, Dec. 1999. [3] J. Ramirez-Angulo, “Current mirrors with low input voltage requirements for built in current sensors,” in Proc. IEEE Int. Symp. Circuits and Systems, May 1994, pp. 529–532.
Adaptive filters based on one version or another of LMS algorithm are probably the most widely used in practice. This is due essentially to the properties of LMS which are: simplicity in use and implementation, numerical stability, and a relatively low computational complexity as compared to other algorithms [1]. However, when the input signal samples are highly correlated, the LMS convergence degrades. It can be shown that the convergence speed is badly affected by the eigenvalues spread of the input signal correlation matrix which is generally
Manuscript received March 2000; revised May 2001. This paper was recommended by Associate Editor C. Cowan. S. Attalah was with the Centre for Wireless Communications, National University of Singapore, TeleTech Park, Singapore 117674. He is now with the School of Electrical and Computer Engineering, Curtin University of Technology, Perth 6845, Australia (e-mail:
[email protected]). S. W. Liaw is with the Centre for Wireless Communications, National University of Singapore, TeleTech Park, Singapore 117674. Publisher Item Identifier S 1057-7130(01)07503-6.
1057–7130/01$10.00 © 2001 IEEE
