The 1b comparator is based on a differential difference amplifier comprising two parallel PMOS differential pairs followed by an inverting gain stage. It is followed ...
ISSCC 2004 / SESSION 12 / BIOMICROSYSTEMS / 12.3
12.3
A 0.18µm CMOS 10-6lux Bioluminescence Detection System-on-Chip
H. Eltoukhy1, K. Salama1, A. El Gamal1, M. Ronaghi2, R. Davis2 Stanford University, Stanford, CA Stanford Genome Technology Center, Stanford, CA
1
Each column DSP comprises eight 20b loadable shift registers, a 20b adder/subtractor, and a 64x20 SRAM and performs read/write/add/subtract/accumulate/shift operations on the ADC data. The column DSP shift registers are strung together into eight 320b shift registers that are used to latch the ADC output, provide testability and for serial data readout.
2
Bioluminescence whereby light is emitted as a result of a chemical reaction offers several advantages over other assay methods, such as fluorescence, including low background and the utilization of reagents with extended shelf life [1]. Also, since no filters or excitation sources are needed, lab-on-chip integration is considerably easier. Of special interest are luciferase-based assay methods with a 560nm emission peak that are used to detect pathogens and proteins, perform gene expression and regulation studies, and sequence DNA. Today’s commercial luminescence detection systems use expensive, cooled CCD-based camera setups and require many microliter volumes of costly reagents due to the high loss in their optical paths. There is growing need for miniaturized low cost luminescence detection systems for environmental and biomedical diagnostics. To address this need systems in which the luminescent chemistry is directly coupled to the detector surface, and therefore must be operated at room temperature [2] are being investigated. This work is targeted to a set of applications, including nucleic acid, protein and pathogen detection, which require 1-1000 assay sites each of size 150x150µm2 and have reaction times of 1-30s with a minimum emission rate of 4x105 photons/cm2.s (10-6lux). As off-theshelf CCD and CMOS imagers cannot satisfy these requirements, a detection chip having a pixel array with the same pitch as the assay site array is designed and fabricated. A block diagram of the chip, which is fabricated in a 0.18µm CMOS process [3], is given in Fig. 12.3.1. It comprises three main sections, an 8x16 pixel array, a per-pixel 13b 2-step ADC, and a column-level DSP SIMD array. To achieve low read noise, a pseudo-differential pixel and ADC architecture is used. The pixel comprises a P+/N/Psub photodiode, an NMOS reset gate and two PMOS source followers one connected to the photodiode and the other connected to a global reference signal VREF. A PMOS follower circuit is used to lower photodiode operating voltage range to reduce dark current and to achieve high linearity. Each pixel's pseudo-differential output is connected to a separate ADC channel consisting of a VGA, a 1b differential comparator and a 4b DAC as shown in Fig. 12.3.2. A per-pixel ADC design is chosen to (i) achieve over seven 13b MS/s using simple low frequency circuits, (ii) reduce noise bandwidth, (iii) provide architecture scalability, and (iv) eliminate switching noise. The VGA employs a fully differential amplifier with a non-silicided P+ poly resistor feedback network. A PMOS folded cascode topology with a low impedance output stage and amplifier-based common-mode feedback is used. The amplifier’s DC gain and bandwidth are designed for near resistor limited linearity and low noise. A resistive feedback instead of a switched capacitor design is used to eliminate the adverse effects of clocking and switching and save area.
Two-step A/D conversion is performed simultaneously for all pixels. A coarse 4b conversion is performed first. The DAC output is then subtracted from the pixel output, amplified by a factor of 30 and quantized to 9b. Single-slope A/D conversion is performed in each step using a differential ramp signal and a digital ramp sequence that are generated on-chip and globally distributed to the comparators and column-level shift registers, respectively. When a comparator output flips, the corresponding digital code is latched into the shift register. The resulting 13b digital values are subsequently stored in the DSP SRAM. To reduce read noise, the second ADC step is repeated multiple times and the outputs are accumulated by the DSP to produce up to a 20b result. The chip operation is illustrated in Fig. 12.3.3. Several dark frames with the same integration time are first captured and averaged to accurately estimate the background signal. Light emission is triggered by the addition of a chemical reagent and the signal frame is then captured. A variation of correlated multiple sampling [4] is used in capturing each frame. Pixel values are read out four times: during reset, just after reset, at the end of integration and during the following reset. Each readout is performed multiple times as explained earlier. If Bi and Si, i=1,..,4, are the respective averaged pixel background and signal values, the estimated signal is given by S= (S3-S2)- (S4-S1)-((B3-B2)-(B4-B1)). Note that (S3-S2) corresponds to digital CDS operation. The subtraction of (S4-S1) reduces the 1/f noise of the readout chain, which is important given the long circuit observation time. Figure 12.3.4 summarizes the main chip characteristics and performance and Fig. 12.3.5 provides a micrograph of the test chip. Figure 12.3.6 plots measured fine-step ADC transfer curve. Figure 12.3.7 plots SNR versus the number of the incident photons/pixel for 30s integration for (i) single 13b A/D conversion, (ii) averaged 128 13b A/D conversions, and (iii) optimal shot noise limited performance. Note that the SoC performance exceeds the 10-6lux detection requirement and is close to optimal and that averaging provides around 5.3dB improvement over single 13b A/D conversion. Acknowledgments: The authors thank P. Griffin, A. Agah and A. Hassibi for their valuable insights, and S. Kavusi, A. Ercan, H. Tian and D. Yang to the design and verification of the sensor. The work was partially supported by NIH Grant: 5 PO1 HG000205 and DARPA Grant: N66001-02-1-8940. References: [1] N. Van Dyke et al., “Luminescence Biotechnology: Instruments and Applications,” CEC Press, New York, 2002. [2] K. Salama, H. Eltoukhy, A. Hassibi, A. El Gamal, “Modeling and Simulation of Integrated Luminescence Detection Platforms,” Proceedings of SPIE, vol. 4966, pp. 106-116, 2003. [3] H.C. Chien et al., “Active Pixel Image Sensor Scale Down in 0.18um CMOS Technology,” IEDM Technical Digest, pp. 813-6, December 2002. [4] A. Fowler et al., “Noise Reduction Strategy for Hybrid IR Focal Plane Arrays,” Proceedings of SPIE, vol. 1541, pp. 127-133, 1991.
The 1b comparator is based on a differential difference amplifier comprising two parallel PMOS differential pairs followed by an inverting gain stage. It is followed by a 3.3V to 1.8V level shifting buffer. The 4b DAC uses a differential current steering architecture. Since the DAC is reset after each ADC and not stepped, area is saved by using binary weighted instead of thermometer coding architecture.
• 2004 IEEE International Solid-State Circuits Conference
0-7803-8267-6/04 ©2004 IEEE
ISSCC 2004 / February 17, 2004 / Salon 1-6 / 2:30 PM
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• 2004 IEEE International Solid-State Circuits Conference
0-7803-8267-6/04 ©2004 IEEE
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Figure 12.3.6: Measured fine-step ADC Transfer Curve.
Figure 12.3.7: Simulated SNR versus illumination in lux for 30s integration time.
• 2004 IEEE International Solid-State Circuits Conference
0-7803-8267-6/04 ©2004 IEEE
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• 2004 IEEE International Solid-State Circuits Conference
0-7803-8267-6/04 ©2004 IEEE
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• 2004 IEEE International Solid-State Circuits Conference
0-7803-8267-6/04 ©2004 IEEE
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• 2004 IEEE International Solid-State Circuits Conference
0-7803-8267-6/04 ©2004 IEEE
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Figure 12.3.4: Chip characteristics and measured performance.
• 2004 IEEE International Solid-State Circuits Conference
0-7803-8267-6/04 ©2004 IEEE
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Figure 12.3.5: Chip micrograph.
• 2004 IEEE International Solid-State Circuits Conference
0-7803-8267-6/04 ©2004 IEEE
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Figure 12.3.6: Measured fine-step ADC Transfer Curve.
• 2004 IEEE International Solid-State Circuits Conference
0-7803-8267-6/04 ©2004 IEEE
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Figure 12.3.7: Simulated SNR versus illumination in lux for 30s integration time.
• 2004 IEEE International Solid-State Circuits Conference
0-7803-8267-6/04 ©2004 IEEE
