Modeling and Control of a Modular Multilevel Converter-Based HVDC ...

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 12, DECEMBER 2012

Modeling and Control of a Modular Multilevel Converter-Based HVDC System Under Unbalanced Grid Conditions Minyuan Guan, Student Member, IEEE, and Zheng Xu, Member, IEEE

Abstract—The modular multilevel converter (MMC) is an emerging and attractive topology for the high-voltage directcurrent (HVDC) transmission system. This paper presents a generalized mathematical model for MMC in HVDC applications under balanced and unbalanced grid conditions. The dynamics of the positive-, negative-, and zero-sequence components are derived from the model. Then, a dual current control scheme with positiveand negative-sequence current controllers is applied to MMC. The power controller to eliminate negative-sequence current components and the other one to eliminate double-line-frequency voltage ripple are compared. Moreover, a zero-sequence current controller is proposed in addition to the positive- and negative-sequence current controllers. Time-domain simulations on a 61-level MMCHVDC test system are performed in the PSCAD/EMTDC software environment. The results demonstrate that the MMC-HVDC system with or without converter transformer is able to operate under unbalanced conditions by the use of the proposed control scheme. Index Terms—High-voltage direct-current (HVDC) transmission, modular multilevel converter (MMC), unbalanced operation, voltage-sourced converter (VSC)-HVDC.

I. INTRODUCTION HE high-voltage direct-current (HVDC) system based on voltage-sourced converters (VSC-HVDC) is a new generation of HVDC technology. The use of fully controlled power semiconductors provides VSC-HVDC with self-commutated capability. This feature enables independent control of real and reactive power at ac terminals, and power supplies to weak or passive ac networks [1], [2]. The modular multilevel converter (MMC) was first introduced in 2001 [3]. This converter is an emerging cascaded multilevel converter with common dc bus, and considered suitable for VSC-HVDC transmission [4]–[10]. MMC is well scalable to high-voltage levels of power transmission based on cascade connection of multiple submodules (SMs) per arm [4], which also means a high number of output voltage levels (e.g., “Trans Bay Cable” Project is at 400 kV dc voltage, and about 200 SMs per arm [6]). The high number of voltage levels provides high-

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Manuscript received December 5, 2011; revised February 10, 2012; accepted March 24, 2012. Date of current version July 13, 2012. Recommended for publication by Associate Editor R. Burgos. The authors are with the College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2012.2192752

quality output voltage with low common-mode voltage, also known as zero-sequence voltage in a three-phase ac system [11]. Thus, only small or even no filters are required. Another advantage of the high-level number is that low switching frequency modulation scheme can be adopted to reduce semiconductor switching losses [5], [11]–[13]. Vector current control derived in the dq synchronous reference frame (SRF) has been widely used in three-phase ac/dc converters. To deal with unbalanced grid conditions, a dual current control scheme including positive- and negative-sequence vector current controllers was introduced in [14], and applied to two-level and three-level grid-connected VSCs in [15]–[18]. This control scheme can also be applied to the control of MMCbased HVDC system [9]. Thus, investigations on the performance of a vector-controlled MMC-HVDC system are required. A new MMC model is proposed in [19], in which the impact of six arm reactors on power exchange is taken into account. The new model is derived from medium- or low-voltage inverters, in which the dc side is composed of two identical dc voltage sources in series connection with the dc-side neutral point grounded. As a matter of fact, there is no realistic dcside neutral point existing in MMC-based HVDC system, and grounding devices are installed at the ac side of the converter to provide a reference to ground [20]. In a conventional two-level converter, only positive- and negative-sequence current components are controllable. The zero-sequence components can be partially controlled in the three-level NPC converter by an appropriate choice of the redundant switching state vectors [21], [22]. In a VSC-HVDC transmission system, the zero-sequence components are usually excluded from the converter by a Y/Δ-connected three-phase transformer, with the Δ-connection on the converter side. However, zero-sequence components are unavoidable in the event of asymmetrical faults on the converter side of the transformer or in a transformerless scheme. Because of the distributed location of capacitive energy storages in MMC, an independent control over zero-sequence components becomes possible [4]. In this paper, a mathematical model for MMC in HVDC applications under balanced and generalized unbalanced grid conditions is derived. Not only the positive- and negative-sequence components, but also the zero-sequence components are taken into considerations. Based on this model, control strategies of MMC-HVDC under generalized unbalanced grid conditions are given. The rest of this paper is organized as follows. Section II introduces the system structure and operation principles of the MMC in HVDC applications. The generalized mathematical

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GUAN AND XU: MODELING AND CONTROL OF A MODULAR MULTILEVEL CONVERTER-BASED HVDC SYSTEM

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III. GENERALIZED MATHEMATICAL MODEL A. Generalized Mathematical Model As shown in Fig. 1, ik 1 and ik 2 are the upper and lower arm currents in phase-k (k = a, b, c), and their sum constitutes the phase-k current ik ik 1 + ik 2 = ik .

(1)

Their difference, which circulates through the phase-k unit [19], is expressed as (ik 1 − ik 2 ) . 2 Then, ik 1 and ik 2 are expressed as ⎧ ik ⎪ + ik dif ⎨ ik 1 = 2 ⎪ ik ⎩ − ik dif . ik 2 = 2 Applying Kirchhoff’s voltage law (KVL) to the upper lower converter arms of the phase-k in Fig. 1 yields [19] Ud dik 1 − uk 1 = 2L + 2Rik 1 uk − uo + 2 dt ik dif =

Fig. 1.

Circuit configuration of a modular multilevel converter.

model of MMC is derived in Section III. Section IV presents the designed controllers for the MMC-HVDC system under generalized unbalanced conditions. To investigate the proposed controllers, time-domain simulation studies in the PSCAD/EMTDC software environment are presented in Section V. Section VI concludes this paper. II. SYSTEM STRUCTURE AND OPERATION PRINCIPLES Fig. 1 depicts the circuit configuration of an MMC in HVDC applications. The dc-side neutral point “o” is a fictitious point [9], and unavailable in a realistic MMC-HVDC system. The converter topology consists of six converter arms where each arm contains a series connection of n nominally identical SMs and a converter inductance 2L [4]. The total equivalent resistor of each converter arm is represented by 2R. Each SM contains an insulated gate bipolar transistor (IGBT) half-bridge as switching element and a dc storage capacitor. The upper and lower arms in one phase comprise a phase unit [6]. There are two complementary switching states relevant to the normal operation of SM [8]: the ON-state, when the upper IGBT is switched ON and the lower IGBT is switched OFF, and the OFF-state, when the upper IGBT is switched OFF and the lower IGBT is switched ON. In the ON-state, the storage capacitor voltage is applied to the output terminal of the SM, and the charging or discharging of the capacitor depends on the current flow direction [13]. In contrast, zero voltage is applied to the output terminal of the SM in the OFF-state, irrespective of the current flow direction. Usually, the SMs switched at ON-state are half of all the SMs in one phase unit [8]. By dividing them between the upper and lower arms, a desired output voltage at the ac output terminal is obtained. The SMs at ON-state in one arm can be varied from 0, 1, to n, so n+1 discrete voltage levels are available.

Ud dik 2 + uk 2 = 2L + 2Rik 2 uk − uo − 2 dt

(2)

(3)

and

(4)

(5)

where uo is the potential to ground of the dc-side neutral point. The sum of (4) and (5) divided by 2 is (uk 2 − uk 1 ) dik + uo = L + Rik . uk − (6) 2 dt Subtracting (5) from (4), we obtain dik dif + 4Rik dif . (7) dt Equations (6) and (7) are derived by Kirchhoff’s current and voltage laws, and are satisfied under both balanced and unbalanced grid conditions. Let uk 1 + uk 2 − Ud = 4L

(uk 2 − uk 1 ) . (8) 2 Equation (6) for three phases (a, b, c) can be written as ⎧ dia ⎪ ⎪ ⎪ ua − (va + uo ) = L dt + Ria ⎪ ⎪ ⎪ ⎨ dib (9) + Rib ub − (vb + uo ) = L ⎪ dt ⎪ ⎪ ⎪ ⎪ ⎪ ⎩ u − (v + u ) = L dic + Ri . c c o c dt The dynamics of the MMC ac-side variables are described by (9), which are illustrated in Fig. 2. vk =

B. Symmetrical Components Under unbalanced grid conditions (e.g., asymmetrical fault), the unbalanced three-phase voltages and currents at fundamental

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Fig. 3.

Fig. 2.

Simplified equivalent circuit on the ac side.

frequency can be decomposed into positive-, negative-, and zerosequence components [23]. The zero-sequence component is extracted from three-phase quantities by (fa + fb + fc ) (10) 3 where f represents voltage or current. The method used in [24] to separate the positive- and negative-sequence components is adopted here. Then, the system described by (9) can be decomposed into three decoupled subsystems as f0 =

di+ (t) + + L abc + Ri+ abc (t) = uabc (t) − vabc (t) dt

(11a)

di− − − abc (t) + Ri− abc (t) = uabc (t) − vabc (t) dt

(11b)

L

di0 (t) + Ri0 (t) = u0 (t) − (v 0 (t) + uo (t)) (11c) dt where (11a), (11b), and (11c) represent the “positive-sequence subsystem,” the “negative-sequence subsystem,” [15] and the “zero-sequence subsystem,” respectively. The positive- and negative-sequence subsystems in MMC, in terms of their synchronous dq-frame components, are expressed as L

di+ R 1 + 1 d = − i+ u − vd+ + ωi+ q + dt L d L d L di+ R + 1 1 q = −ωi+ i + u+ − vq+ d − dt L q L q L di− R 1 − 1 − d = − i− u − vd − ωi− q + dt L d L d L

(12a)

Schematic diagram of an MMC-based HVDC system.

method. With a proper modulation method, the common-mode voltage and the zero-sequence components in (11c) are very small due to the high number of voltage levels. Thus, the potential to ground of the dc-side neutral point is also small, and the positive and negative pole voltages to ground are almost symmetrical under the balanced grid condition. C. Instantaneous Real and Reactive Power The active and reactive power inputs at the point of common coupling (PCC) in Fig. 1 are given in [14] and [25] as P = P1 + Ps2 sin(2ωt) + Pc2 cos(2ωt) + 3u0 i0

(14a)

Q = Q1 + Qs2 sin(2ωt) + Qc2 cos(2ωt)

(14b)

where P1 , Q1 , Ps 2 , Pc 2 , Qs 2 , and Qc 2 are given by ⎡ + ⎤ ⎤ ⎡ ud u+ u− u− q q d P1 ⎢ + ⎥⎡ + ⎤ ⎢ Q ⎥ −u+ u− −u− ⎢ uq q d ⎥ id d ⎢ 1 ⎥ ⎢ ⎥ ⎥ ⎢ ⎥ ⎢ i+ ⎥ ⎢ Ps2 ⎥ 3 ⎢ u− −u− −u+ u+ ⎢ ⎥⎢ q ⎥ q q d d ⎥= ⎢ ⎢ ⎢ ⎥. ⎢ Pc2 ⎥ 2 ⎢ u− + ⎥ + − ⎥ ⎣ i− ⎦ u u u ⎥ ⎢ q d q d d ⎢ ⎥ ⎥ ⎢ ⎢ ⎥ + + − − − Q ⎣ s2 ⎦ uq ⎦ iq −uq ud ⎣ −ud − − + Qc2 u −u u −u+ q

d

q

d

(15) If the d-axis is fixed to the positive-sequence grid-voltage component, the q-axis component of positive-sequence grid voltage u+ q is zero in steady state. If the negative- and zero-sequence current components are zero, (14) can be simplified as + P = 1.5u+ d id

(16a)

+ Q = −1.5u+ d iq .

(16b)

(12b) IV. CONTROL (13a)

di− R − 1 − 1 − q = ωi− i + u q − vq (13b) d − dt L q L L which is the same as that in conventional converters (e.g., twolevel converter and three-level NPC converter) given in [15] and [16]. It can be inferred from (11) that uo (t) is a zero-sequence component at the ac side, and has no influence on the positive- and negative-sequence subsystems. Under the balanced condition, the common-mode voltage of MMC is not only determined by the number of voltage levels, but also affected by the modulation

Fig. 3 shows the schematic diagram of an MMC-HVDC system. When asymmetrical faults occur at the ac system, there will be negative- and zero-sequence components in grid voltages. In conventional converters with concentrated energy storage capacitors at the dc side (e.g., two-level converter), only positiveand negative-sequence current components are fully controllable. Thus, the converter transformer is connected in the Y/Δ configuration to exclude the zero-sequence components from the converter. However, zero-sequence components will appear in the event of asymmetrical faults on the converter side of the converter transformer. On the other hand, zero-sequence components are unavoidable in transformerless scheme under asymmetrical fault conditions.


In MMC, the distributed location of energy storage capacitors permits independent control of each phase. Thus, a zerosequence current control becomes possible in addition to the positive- and negative-sequence current control. A. Control of Positive- and Negative-Sequence Currents If there are no zero-sequence components, only positive- and negative-sequence components are taken into consideration. According to (12) and (13), the positive- and negative-sequence current control of conventional converters (e.g., two-level converter and three-level NPC converter), which is explained in detail in [15] and [16], can be directly applied to MMC; therefore, a brief description is given here. The control scheme is divided into two separate loops: an inner fast current loop and an outer slow loop [16]. 1) Inner Loop Current Control: The inner current control is developed to regulate the positive- and negative-sequence cur+∗ − −∗ rents i+ dq and idq at their command references idq and idq by + − adjusting the control inputs vdq and vdq , respectively. The dis+ − turbance inputs udq and udq could be canceled by feed-forward compensation. The control inputs are given by [15] and [16] +∗ + +∗ + + vd+ = u+ + ωLi − k (i − i ) + k − i )dt (i p1 d i1 q d d d d (17a) + +∗ + +∗ + vq+ = u+ − ωLi − k (i − i ) + k − i )dt (i p2 q i2 q q q q d (17b) − − − −∗ − −∗ − vd = ud − ωLiq − kp3 (id − id ) + ki3 (id − id )dt (18a) − − − −∗ − −∗ − vq = uq + ωLid − kp4 (iq − iq ) + ki4 (iq − iq )dt . (18b) 2) Outer Loop Control for Conventional Converters: The outer loop control is designed to provide the command refer−∗ ences i+∗ dq and idq for the inner loop current control. Two different power controllers have been proposed for conventional converters under unbalanced conditions [15]. The power controller 1 is developed to eliminate negativesequence current components by setting their command references as zero [9], [15] i−∗ dq = 0.

(19)

The line currents could be kept balanced with the power controller 1, so the command references i+∗ dq can be derived from (16) as i+∗ d = i+∗ q ∗

∗

P∗ 1.5u+ d

−Q∗ = 1.5u+ d

(20a)

(20b)

where P and Q are the command references of three-phase real and reactive power inputs at PCC, respectively.

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If the converter is assigned to control dc-side voltage, (20a) should be replaced by ∗ = k (U − U ) + k (21) (Ud∗ − Ud )dt i+∗ p5 d i5 d d where Ud∗ is the command reference of dc-side voltage. Notch filter can be used to filter the double-line-frequency ripple in dc-side voltage. The power controller 2 is developed to eliminate the doubleline-frequency ripple in dc-side voltage by canceling the doubleline-frequency ripple in the three-phase real power input to the converter [14]–[16]. This can be done by making [P1 , Q1 , Ps2 , Pc2 ]T = [P ∗ , Q∗ , 0, 0]T .

(22)

Substituting (22) into (15), we obtain [14], [24] ⎡ + ⎤ ⎡ +∗ ⎤ ⎡ + ⎤ uq id ud ⎢ ⎥ + ⎥ ⎢ i+∗ ⎥ −u+ 2P ∗ ⎢ ⎢ q ⎥ ⎢ uq ⎥ 2Q∗ ⎢ d ⎥ ⎢ ⎥ ⎢ −∗ ⎥ = ⎢ ⎥+ − ⎥ 3D2 ⎢ ⎣ id ⎦ 3D1 ⎣ −u− d ⎦ ⎣ uq ⎦ i−∗ −u− −u− q q d where

(23)

⎧ 2 + 2 − 2 − 2 ⎨ D1 = u+ + uq − ud − uq d 2 + 2 − 2 − 2 ⎩ D2 = u+ + uq + ud + uq . d

(24)

3) Outer Loop Power Controller for MMC: In conventional converters (e.g., two-level converter and three-level NPC converter), the dc-side voltage is supported by centralized energy storage capacitors arranged at the dc side. The positiveand negative-sequence components of the power ripple in each phase, which are circulating between three phases, have no effect on the three-phase real power and the dc-side voltage. In MMC, the energy storage capacitors are separately distributed in three phases and the dc-side voltage is supported by three phase units. Thus, power ripple in a single phase will result in a dc-side voltage ripple. The positive- and negative-sequence components of phase-k voltage and current are expressed, respectively, as = [ U + cos(ωt + θk+ ) u+− k

U − cos(ωt + θk− ) ]T

(25a)

i+− = [ I + cos(ωt + ϕ+ k k )

T I − cos(ωt + ϕ− k )]

(25b)

where the amplitudes of positive- and negative-sequence voltages are expressed, respectively, as [9] 2 2 U+ = u+ + u+ (26a) q d 2 2 u− + u− . (26b) U− = q d The instantaneous power input to phase-k (k = a, b, c) is represented by + − − pk (t) = (u+ k (t) + uk (t))(ik (t) + ik (t)) − 0 = Pk 1 + p + k 2 + pk 2 + pk 2

p+ k2,

(27) p− k2,

p0k 2

where Pk 1 is the dc component of pk . and are the double-line-frequency power ripples in positive-, negative-,

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and zero-sequence, respectively. Substituting (25) into (27), we obtain − − − − p+ k 2 = 0.5U I cos(2ωt + θk + ϕk )

(28a)

+ + + + p− k 2 = 0.5U I cos(2ωt + θk + ϕk )

(28b)

(28c)

0 where p+ k 2 and pk 2 are zero under balanced condition. The threephase real power input is the sum of the instantaneous power inputs to three phases

p(t) = 3Pk 1 + 3p0k 2 .

(29)

Since power ripple in three-phase real power is eliminated with the power controller 2, the zero-sequence component in the single-phase power ripple is also eliminated. The dc-side voltage ripple at double line-frequency in conventional converters can be eliminated with the power controller 2. In MMC, not only the zero-sequence component but also the positive- and negative-sequence components of the power ripple in single-phase will cause dc-side voltage ripple. Thus, the dc-side voltage ripple in MMC cannot be eliminated with the power controller 2. A comparison of single-phase power ripples with the power controllers 1 and 2 is given here. In steady state, the positive- and negative-sequence currents track their command references with zero errors under the action of the integral term of PI controllers. Thus, the amplitudes of positive- and negative-sequence currents are expressed as [9] 2 2 i+∗ + i+∗ (30a) I+ = q d 2 2 i−∗ + i−∗ . (30b) I− = q d − For the power controller 1, the amplitudes of p+ k 2 , pk 2 , and are derived by substituting (19) and (20) into (28) and (30)

p0k 2

Pk+21 = 0 Pk−21 Pk021

( (P ∗ )2 + (Q∗ )2 ) = 3 ( (P ∗ )2 + (Q∗ )2 )U − . = (3U + )

Impact of zero-sequence components on MMC-HVDC systems.

and (30):

p0k 2 = 0.5U + I − cos(2ωt + θk+ + ϕ− k) + 0.5U − I + cos(2ωt + θk− + ϕ+ k )

Fig. 4.

(31a)

(31b)

(31c)

With the power controller 1, Pk−21 under unbalanced conditions is the same as that under balanced condition, most of which can be absorbed by the converter reactors and SM capacitors without causing significant dc-side voltage ripple. Since there are plenty of SM capacitors in MMC, the dc-side voltage ripple caused by p0k 21 is small. − For the power controller 2, the amplitudes of p+ k 2 , pk 2 , 0 and pk 2 are obtained by substituting (23) and (24) into (28)

Pk+22

(U − )2 = 3

(U + )2 Pk−22 = 3

(P ∗ )2 (Q∗ )2 + − 2 2 + 2 − (U ) ) ((U ) + (U − )2 )2 (32a)

((U + )2

(P ∗ )2 (Q∗ )2 + . − 2 2 + 2 − (U ) ) ((U ) + (U − )2 )2 (32b) is zero

((U + )2

The amplitude of p0k 2

Pk022 = 0.

(32c)

Usually, the command reference of real power is much larger than that of reactive power. Thus, the Pk−22 is usually larger than − Pk−21 . The sum of p+ k 2 and pk 2 may be considerably larger in one of the three phases with the power controller 2, which will lead to high ripples in SM capacitor voltages as well as in the dc-side voltage. Moreover, Pk+22 and Pk−22 become extremely large under certain conditions (e.g., U+ ≈ U − ). Therefore, the objective of the power controller 2 to eliminate double-line-frequency ripple in dc-side voltage is not accomplished in MMC. B. Control of Zero-Sequence Current The controllers described previously take no consideration of the zero-sequence components. The dynamics of zero-sequence components can be rewritten as L

di0 (t) + Ri0 (t) = u0 (t) − uo (t) − v 0 (t) dt

(33)

where u0 (t) is the zero-sequence component in grid voltage. Under asymmetrical faults on the converter side of the transformer or in a transformerless scheme, there will be considerable zerosequence component in grid voltage, which will lead to high zero-sequence current component in input ac currents. According to Kirchhoff’s current law, zero-sequence current will be transmitted to the dc side as shown in Fig. 4. The potential to ground of dc-side neutral point will float according to (33). Therefore, the converter may be shut down due to overcurrent and/or overvoltage. To avoid the aforesaid problems, a zero-sequence current controller is proposed. The command reference of the zerosequence current component is set as zero i0∗ = 0.

(34)


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TABLE I PARAMETERS OF THE STUDIED SYSTEM

Fig. 5.

Block diagram of the zero-sequence current controller.

Fig. 6.

Block diagram of the overall unbalanced control scheme.

A PI feed-back controller with a zero-sequence grid-voltage feed-forward compensator is used for the control of zerosequence current component. The zero-sequence current control is given by (35) and illustrated in Fig. 5 v 0 (t) = u0 (t) − kp6 (i0∗ − i0 ) + ki6 (i0∗ − i0 )dt . (35) The integral term of the PI controller guarantees zero steadystate error, so zero-sequence current is eliminated. The potentials to ground of two dc-side neutral points “o1 ” and “o2 ” are clamped to zero. Moreover, the unwelcome zero-sequence instantaneous real power [25], represented by “3u0 i0 ” in (14a), is eliminated. So the command references of positive- and negative-sequence current components determined by (19), (20), and (23) are still valid. Thus, the zero-sequence current controller coordinates well with the positive- and negativesequence current controllers. The fault ride-through capability of the MMC-HVDC system is enhanced by the zero-sequence controller, which can be implemented by software routine in the microcomputer control system with no additional cost in hardware. Under normal operation conditions, the zero-sequence controller is disabled since it may introduce small disturbance caused by the small common-mode voltage. Fig. 6 shows an overview of the unbalanced control scheme. The overview illustrates the relationships between the controllers mentioned in this section. V. CASE STUDY A. Study System In this section, dynamic performance of an MMC-HVDC system with the controllers described in Section IV in response to single line-to-ground (SLG) fault is investigated by time-domain

simulation studies in the PSCAD/EMTDC environment. Table I lists the parameters of the studied 61-level MMC-HVDC system as shown in Figs. 1 and 3. The parameters of PI controllers and dc cables are provided in Appendices A and B, respectively. The nearest level modulation in [11]–[13] and the straightforward voltage balancing strategies in [9] are adopted in the studied system. The start-up process is not studied here; the capacitor voltages of SMs were initially charged at nominal value (e.g., 3 kV). The MMC-1 station controls dc-side voltage and reactive power input to the converter, and their command references are set as 180 kV and 0 MVar, respectively. The MMC-2 station regulates the real and reactive power inputs to the converter, and their command references are set as −180 MW and 0 MVar, respectively. B. Performance of Two Power Controllers A temporary SLG fault at the line side of MMC-2 transformer is imposed at t = 0.4 s and cleared after 0.25 s. If the SLG fault occurs at the line side of the MMC-1 transformer, the control objects of the MMC-1 station (e.g., the dc-side voltage) and the MMC-2 station (e.g., the real power) can be exchanged. Dynamic performances of the studied system with the power controller 1 and power controller 2 are investigated and compared. 1) Performance of the Power Controller 1: The power controller 1 is adopted in this case. The corresponding simulation waveforms at MMC-2 are illustrated in Fig. 7. Fig. 7(a) and (b) shows the three-phase input voltages at the Y-side and Δside of the converter transformer, respectively. Fig. 7(c) shows the three-phase input currents at the Δ-side of the converter transformer. Fig. 7(d) and (e) shows the positive- and negativesequence current components, respectively. With the power controller 1, negative-sequence current components are eliminated

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Fig. 7. Simulation waveforms of the studied system with the power controller 1 under an SLG fault (MMC-2 side): (a) three-phase input voltages at the Y-side of the converter transformer, (b) three-phase input voltages at the Δ-side of the converter transformer, (c) three-phase input currents at the Δ-side of the converter transformer, (d) positive-sequence current components, (e) negativesequence current components, (f) three-phase real and reactive power, (g) dc-side voltage, and (h) capacitor voltages of SMs in the phase-a upper arm.

and the three-phase currents are kept balanced during the SLG fault. Fig. 7(f) shows that there are double-line-frequency ripples in real and reactive power inputs to MMC-2 during the fault. Fig. 7(g) shows that the amplitude of dc-side voltage ripple during the fault is small. The capacitor voltages of SMs in the phase-a upper arm are illustrated in Fig. 7(h). The capacitor voltage ripples are increased under unbalanced conditions. Desired dynamic response of a back-to-back MMC-HVDC system with the power controller 1 under unbalanced grid conditions is also validated by the simulation studies in [9]. 2) Performance of the Power Controller 2: The power controller 2 is adopted in this case. The corresponding simulation waveforms at MMC-2 are illustrated in Fig. 8. Fig. 8(a) and (b) shows the three-phase input voltages at the Y-side and Δ-side of the transformer, respectively. Fig. 8(c) shows the three-phase

Fig. 8. Simulation waveforms of the studied system with the power controller 2 under an SLG fault (MMC-2 side): (a) three-phase input voltages at the Y-side of the converter transformer, (b) three-phase input voltages at the Δ-side of the converter transformer, (c) three-phase input currents at the Δ-side of the converter transformer, (d) positive-sequence current components, (e) negativesequence current components, (f) three-phase real and reactive power, (g) dc-side voltage, and (h) capacitor voltages of SMs in the phase-a upper arm.

input currents at the Δ-side of the transformer. Fig. 8(d) and (e) shows the positive- and negative-sequence current components, respectively. Fig. 8(f) shows the three-phase real and reactive power inputs to MMC-2. During the fault, the three-phase real power ripple is eliminated with the power controller 2, but the amplitude of dc-side voltage ripple shown in Fig. 8(g) is much larger than that in Fig. 7(g). The instantaneous power input to phase-k is expressed as pk (t) = Uk cos(ωt + θk )Ik cos(ωt + ϕk ) = 0.5Uk Ik cos(θk − ϕk ) + 0.5Uk Ik (2ωt + θk + ϕk ) (36) where Uk and Ik are the amplitudes of voltage and current in phase-k, respectively. θk and ϕk are the relative phase angles of voltage and current in phase-k. The single-phase power ripple is at double line-frequency, whose amplitude is the half of the


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Fig. 10. Simulation waveforms of the studied system under an SLG fault (MMC-2 side): (a) positive-sequence d-axis current components, (b) positivesequence q-axis current components, (c) negative-sequence current components, and (d) zero-sequence current component.

Fig. 9. Simulation waveforms of the studied system under an SLG fault (MMC-2 side): (a) three-phase input voltages at PCC of MMC-2, (b) threephase input currents at PCC of MMC-2, (c) three-phase real and reactive power, (d) dc-side voltage, (e) dc-side currents, and (f) capacitor voltages of SMs in the phase-a upper arm.

multiplication of the amplitudes of voltage and current in that phase. During the fault, the current amplitudes of two phases in Fig. 8(c) are much larger than that in Fig. 7(c), which means severe overcurrent. Thus, the amplitude of single-phase power ripple in these phases with the power controller 2 would be much larger than that with the power controller 1, which causes high ripples in SM capacitor voltages as shown in Fig. 8(h), and, consequently, high ripple in the dc-side voltage. The objective of the power controller 2 to eliminate doubleline-frequency dc-side voltage ripple under unbalanced conditions is not accomplished in MMC. Furthermore, severe overcurrent faults may be caused by the power controller 2. Thus, the power controller 2 is inappropriate for the control of MMC under unbalanced grid conditions. C. Performance of the Zero-Sequence Controller To investigate the performance of the zero-sequence controller, the converter transformers in Fig. 3 are removed. The studied system is in transformerless scheme. A temporary SLG (e.g., in phase-c) fault at the PCC of MMC-2 occurs at t = 0.4 s and is cleared after 0.25 s. The power controller 1 is adopted. The zero-sequence controller is put into service at t = 0.5 s. Fig. 9(a) and (b) shows the three-phase voltage and current inputs at the line side of MMC-2, respectively. Fig. 9(c) shows the three-phase real and reactive power inputs to MMC-2. DC-

side voltage and currents are illustrated in Fig. 9(d) and (e), respectively. Fig. 9(f) shows the capacitor voltages of SMs in the phase-a upper arm. The corresponding positive-, negative-, and zero-sequence current components are illustrated in Fig. 10. When the SLG fault is imposed and the zero-sequence controller is not activated (e.g., from t = 0.4 s to t = 0.5 s), the amplitude of zero-sequence current component is large, and the ac currents become highly unbalanced. Moreover, zero-sequence current component in ac currents is transmitted to the dc side as shown in Fig. 9(e). Without the zero-sequence controller, the MMC will be forced to be shut down due to large amplitude of zero-sequence current component introduced by asymmetrical faults. When the zero-sequence controller is activated, the zerosequence current component in Fig. 10(d) is reduced to almost zero and the ac currents in Fig. 9(b) are kept balanced. Moreover, the dc-side currents are smoothed. With the zero-sequence controller, the MMC is able to be in continuous operation under asymmetrical faults. Therefore, the fault ride-through capability of the MMC-HVDC system is enhanced by the zero-sequence controller. The converter transformer is one of the major cost components in HVDC transmission systems. By increasing the number of SMs per arm, the MMC is well scalable to highvoltage/power level, and high-quality voltage waveform can be achieved. Therefore, eliminating the converter transformer in one or both converter stations becomes possible, which provides additional flexibilities in station circuit configurations and significant reductions in cost and footprint of the converter station. However, the asymmetrical-fault ride-through capability of the MMC-HVDC system is constrained without the additional zero-sequence controller. Thus, the zero-sequence controller is indispensable for MMC-HVDC in transformerless scheme.

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VI. CONCLUSION This paper presents a generalized mathematical model for MMC in realistic HVDC applications. In the model, the impact of six arm reactors on power exchange and the potential to ground of the dc-side neutral-point are taken into account. Under unbalanced grid conditions (e.g., asymmetrical faults), the model is decomposed into the positive-, negative-, and zerosequence subsystems. The positive- and negative-sequence inner loop current controllers are applied to MMC, and two outer loop power controllers are available. In MMC, the objective of the power controller 1 to eliminate negative-sequence current components is satisfied, but the objective of the power controller 2 to eliminate double-line-frequency ripple in dc-side voltage is not satisfied. Further, a zero-sequence current controller coordinating well with the positive- and negative-sequence current controllers is proposed. With the zero-sequence controller, the asymmetrical-fault ride-through capability of the MMC-HVDC systems, especially the ones in transformerless scheme, is enhanced. The use of transformerless scheme provides additional flexibility in system configurations and significant reductions in cost and footprint of the converter station. The simulation studies based on a 61-level MMC-HVDC transmission system are performed in the PSCAD/EMTDC software environment. The proposed control scheme is validated by the simulation results.

Fig. 11. Block diagram of the control loop of positive-sequence d-axis current component. TABLE II PARAMETERS OF PI CONTROLLERS

TABLE III CABLE PARAMETERS

APPENDIX A. Tuning of PI Controllers Substituting (17a) into (12a), we obtain di+ + +∗ + +∗ + d + Rid = kp1 (id − id ) + ki1 (id − id )dt . L dt (37) The block diagram of the control loop of positive-sequence d-axis current component is illustrated in Fig. 11, and the openloop transfer function is

The parameters of the PI controllers are listed in Table II. More complicated tuning method for PI regulators is left for future study.

kp + ki /s (38) Ls + R where kp and ki are proportional and integral gains, respectively. If the two gains are selected as [26]

The frequency-dependent (phase) model is applied as the simulation model for the cables in the PSCAD/EMTDC software. The cable parameters are listed in Table III, which is based on a cable design that is assembled from [27].

(s) =

kp =

L R and ki = τi τi

(39)

then the open-loop and closed-loop transfer functions are represented by (40) and (41), respectively (s) = G(s) =

1 τi s

(40)

i+ 1 d . +∗ = 1 + τi s id

(41)

Thus, the closed-loop system is reduced to a simple first-order system with a time constant of τ i , which is usually chosen in the range of 1–5 ms [26]. Equation (39) can also be applied to the other current control loops because of the same transfer function.

B. Parameters of DC Cables

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Minyuan Guan (S’11) was born in Zhejiang, China, in 1985. He received the B.S. degree in electrical engineering from Zhejiang University, Hangzhou, China, in 2008, where he is currently working toward the Ph.D. degree in electrical engineering. His current research interests include HVDC transmission systems, the application of power electronics in power systems, and grid integration of distributed energy resources.

Zheng Xu (M’00) was born in Zhejiang, China, in September 1962. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from Zhejiang University, Hangzhou, China, in 1983, 1986 and 1993, respectively. He has been with the College of Electrical Engineering, Zhejiang University, since 1986 and has been a Professor there since 1998. His research interests include HVDC transmission systems, flexible ac transmission systems, and wind energy generation and grid integration.