Modified Sakurai-Newton current model and its applications to CMOS ...

Modified Sakurai-Newton Current Model and its Applications to CMOS Digital Circuit Design Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra Coordinated Science Laboratory/ECE Department University of Illinois at Urbana-Champaign 1308 W. Main Street, Urbana, IL 61801 {mansour, mmansour, amehrotr}@uiuc.edu

Abstract

Accurate drain current modeling for deep submicron (DSM) CMOS circuits is essential in the design and analysis of high-performance digital integrated circuits. Typically, circuit designers employ quick manual calculations in order to estimate the circuit delay using the transistor drain current, which are then followed by more accurate but time consuming circuit simulations using simulators such as HSPICE. The Shichman and Hodges [4] classical quadratic current model for MOSFETs is widely used for manual calculations mainly due to its simplicity. However, in DSM CMOS process technologies, i.e., for 0.35 µm and below, this model gives errors in current estimation that can be as high as 64% when compared to circuit simulations using advanced device models such as the HSPICE level 49 model.1 The purpose of

this paper is to propose a device model that is similar in complexity to the Shichman and Hodges current model but provides a high degree of accuracy when compared to HSPICE level 49 simulations. The Shichman and Hodges model [4] is not accurate for short-channel transistors because it neglects carrier velocity saturation. Sakurai and Newton proposed a model that takes into account short-channel behavior, known as the α-power law model [1]. However, the α-power law model was not sufficiently accurate, and an improved nth-power law model [2] (henceforth referred to as the SN-model) with additional parameters was proposed later. The SN-model provides sufficiently accurate estimates of the drain current when used for wide transistors which do not suffer from narrow-width effects. For instance, in [2] the transistors considered have an effective channel length of 0.25 µm and a transistor width of at least 5 µm, while the minimum transistor width in this technology is 0.36 µm. Thus, the transistors considered are at least 14× the minimum sized transistor. However, digital circuit designers are mainly interested in designing circuits with transistors having widths ranging from minimum size up to 8× the minimum width.2 In this region, the SNmodel is not accurate in describing the relationship between the transistor drain current and its width. This is mainly due to narrow-width effects and the fact that the current no longer has a linear relationship to the transistor width as is the case in the SN-model which has a constant transconductance parameter derived from SPICE device models. In this paper, we present an extension to the SN-model that provides a high-degree of accuracy for drain current calculations, and yet has a simple form. Referred to as the modified SN-model, the proposed model takes into account the dependence of carrier mobility on the vertical field, carrier velocity saturation, and the dependence of the drain current on the transistor gate width (narrow-width effects). The MSN-model matches HSPICE level 49 simulations to within 1.2% average (3% maximum) error in 0.25 µm and 0.18 µm CMOS technologies over a wide range of transistor widths, fanouts, and input rise/fall times. In contrast, the SN-model

1 For 0.25 µm process technology with W = 0.36 µm and the remaining parameters are as described in Table 1.

2 The exception are repeaters which constitute a small percentage of all transistors present in digital VLSI circuits.

This paper presents a model for estimating the drain current in deep submicron CMOS devices. The model presented is an extension of Sakurai and Newton’s model (SNmodel) [1, 2], and hence is referred to as the modified SNmodel (MSN-model). The proposed model preserves the simplicity of the SN-model while providing accurate drain current estimates for varying device widths. The transistor drain current values predicted by the proposed model are compared with HSPICE level 49 simulations for 0.25 µm and 0.18 µm CMOS processes. Manually computed current values for inverter circuits via the proposed model match HSPICE simulations on average to within 1.2% (3% maximum) over a wide range of transistor widths, fanouts, and input rise/fall times. Further, this model is accurate in estimating the current in series-connected transistors having arbitrary widths, where the previous SN-model requires a delay degradation factor with transistors of equal sizes in order to work [3]. The proposed model has been successfully incorporated into a senior level circuit design course at the University of Illinois at Urbana-Champaign.

1

Introduction

Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI’03) 0-7695-1904-0/03 $17.00 © 2003 IEEE

results in 11.4% average (23.5% maximum) error. Thus, the proposed MSN-model improves on the SN-model to dramatically increase its accuracy while keeping its simplicity and hence can be employed by circuit designers for manually estimating CMOS drain currents. Furthermore, we show that using the MSN-model in the delay calculation of different inverter circuits provides accurate estimates to HSPICE simulations.

from the SN-model one needs to re-derive the model parameters for each possible transistor width, which is impractical. Circuit designers typically need accurate current estimates for various widths in order to size up a circuit to meet a specific delay or power constraint, as an example.3 Thus, there is a need for a model that preserves the simplicity of the SNmodel while improving its accuracy when it comes to varying the transistor width.

2

2.3

Drain Current Model

In this section, we first describe the SN-model (section 2.1), followed by a discussion of the limitations of the SNmodel in section 2.2. The proposed MSN-model is presented in sections 2.3 and 2.4 along with its parameter values for 0.25 µm and 0.18 µm CMOS technologies.

2.1

We propose the following modification to the SN-model. The current equations in the two operating regions become: α

(5) IDSAT = K (VGS − VT H ) (1 + λVDS ) , VDS VDS α IDLIN = K (VGS − VT H ) 2 − , (6) VDSAT VDSAT K = β1 + β2 W + β3 W 2 .

Sakurai-Newton (SN) Model

We present below the drain current expressions derived by Sakurai and Newton [1, 2]: W α B (VGS − VT H ) (1 + λVDS ), (1) Lef f W VDS VDS α = B (VGS − VT H ) 2 − , Lef f VDSAT VDSAT (2) 0.5α VGS − VT H VDSAT = VDSAT1 , (3) VDD − VT H

IDSAT = IDLIN

VDSAT1 = VDSAT |VGS =VDD ,

The Proposed Modified SN-Model

(4)

where 1 ≤ α ≤ 2 is the velocity saturation index, B is the transconductance parameter, Lef f is the effective channel length, VT H is the threshold voltage, VDD is the supply voltage, λ is the channel length modulation factor, and VGS and VDS are the gate-source and drain-source voltages, respectively. The voltage VDSAT determines the boundary between linear and saturation regions. In [1] the transconductance parameter B := µCox /2, whereas in [2] it is derived through a parameter extraction experiment done on a specific transistor with a given transistor width.

(7)

The transconductance parameter in (7) (henceforth called the K parameter) is a width-dependent coefficient. It’s values 1/α are derived from the slope of the curve in the Ief f vs. VGS plots using (5) with VDS = VDD , where Ief f is defined as Ief f =

ID . 1 + λVDS

(8)

The coefficients (β1 , β2 , and β3 ) in (7) are then determined by fitting a quadratic to the K vs. W plot. This simple modification to the SN-model enables us to accurately predict the drain current obtained from HSPICE level 49 simulations for varying transistor widths. The parameter values for α, λ, VT H , and γ are derived following the same procedure described in [2].

2.4

Modified SN-Model Parameter Values

For 0.25 µm CMOS technology, the K parameter equations in (A/Vα ) for the NMOS and PMOS devices are: Kn = 31.23 × 10−6 + 209.8Wn + 1.951 × 106 Wn2 , (9) Kp = 6.885 × 10−6 + 66.06Wp + 523.2 × 103 Wp2 , (10) and for 0.18 µm, the corresponding equations are:

2.2

Limitations of the SN-Model

According to (1) and (2), the drain current is directly proportional to the transistor gate width (B is constant). Figures 1a and 1b show that the SN-model is inaccurate when compared to the HSPICE level 49 simulations as the transistor width increases from minimum size. The SN-model parameters were derived as described in [2] for transistor widths of 0.36 µm and 0.22 µm for the 0.25 µm and 0.18 µm process technologies, respectively. These parameters are then used to calculate the drain currents for larger widths. This inaccuracy is mainly due to the narrow-width device effects, and hence, in order to get accurate current estimates

Kn = 2.088 × 10−5 + 422.5Wn + 2.170 × 106 Wn2 , (11) Kp = −4.72 × 10−8 + 118.0Wp + 3.266 × 106 Wp2 . (12) The remaining model parameters derived for the NMOS and PMOS devices are listed in Table 1. Figures 2a - 2d show the MSN-model I-V curves as compared to HSPICE level 49 simulations for 0.25 µm and for 0.18 µm CMOS processes. As shown in the plots, the proposed model matches HSPICE simulations for different transistor widths and input voltages with a high degree of accuracy. 3 This is typically the case for small cells [5]. For macrocells a different design methodology is needed [6].


0.25µm, 2.5V

−3

2.5

x 10

I−Vds plots: . . . SN model __ HSPICE I−Vgs plots: ._. SN model .... HSPICE

W=1.76µm

I−Vds plots: . . . SN model __ HSPICE

1

I−Vgs plots: ._. SN model .... HSPICE

W=2.88µm 0.8

Id: Drain Current [A]


2

0.18µm, 1.8V

−3

x 10

1.2

1.5

1

W=1.44µm

W=0.88µm 0.6

0.4

W=0.44µm W=0.72µm

0.5

0.2

W=0.36µm

0 0

0.5

1

1.5

2

0

2.5

W=0.22µm

0

0.4

0.2

Vds: Drain−Source Voltage [V], Vgs: Gate−Source Voltage [V]

0.6

0.8

1

1.2

1.4

1.6

1.8


(a)

(b)

Figure 1. SN-model I-V plots for different NMOS transistor widths. 0.25µm, 2.5V

−3

1.8

x 10

0.18µm, 1.8V

−3

1.2

x 10

W=2.88µm

1.6

W=1.76µm

I−Vds plots: . . . MSN model

1 __ HSPICE

I−Vgs plots: ._. MSN model .... HSPICE

1.2



1.4

I−Vds plots: . . . MSN model __ HSPICE

1 W=1.44µm

0.8

0.6


0.8

0.6

W=0.88µm

0.4 W=0.72µm W=0.44µm

0.4 W=0.36µm

0.2

W=0.22µm

0.2

0 0

0.5

1.5

1

2

0 0

2.5

0.2


0.4

0.6

(a) 3

2.5

1.2

1.4

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1.8

0.18µm, 1.8V

−4

1.6

x 10

Vgs=1.8V

Vgs=2.5V

I−Vds plots: . . . MSN model __ HSPICE

I−Vds plots:

1.4 . . . MSN model __ HSPICE


I−Vgs plots:

1.2 ._. MSN model

Vgs=2.1V

.... HSPICE

2

1.5

Vgs=1.7V

1

Vgs=1.4V



1

(b)

0.25µm, 2.5V

−4

x 10

0.8


Vgs=1.4V

1

0.8 Vgs=1.0V

0.6

0.4

0.5 0.2 Vgs=0.6V

0 0

0.5

1

1.5

2

2.5

Vds: Drain−Source Voltage [V]. Vgs: Gate−Source Voltage [V]

(c)

0 0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8


(d)

Figure 2. MSN-model I-V plots: Varying W in (a) 0.25 µm, and (b) 0.18 µm. Varying VGS in (c) 0.25 µm for W = 0.36 µm, and (d) 0.18 µm for W = 0.22 µm.


Table 1. Modified SN-model parameter values. α

VDSAT1 (V ) VT H0 (V ) λ (V −1 ) γ (V 1/2 ) 2φf (V ) VDSAT (V )

3

1.224 1.200 0.560 0.049 0.440 0.860 0.8(VGS − VT H )0.5α

1.380 −1.286 −0.51 0.150 0.490 0.880 0.8(VGS − VT H )0.5α

Applications

In this section we demonstrate the effectiveness of the proposed current model in the design and analysis of practical VLSI circuits.

3.1

Series-Connected Transistors

It is possible to compute the drain current of M transistors connected in series which have arbitrary widths. This can be done by deriving the width of an equivalent transistor using the traditional relation 1 1 1 1 + = . + ··· + W1 Wef f WM W2

(13)

This equivalent transistor width can then be used in (7) to compute the equivalent K parameter. In contrast, using the computed Wef f in the SN-model results in inaccurate current estimates. This observation has also been noticed by Sakurai and Newton in [3] where they proposed using a scaling factor referred to as the delay degradation factor. However, the delay degradation factor only works for transistors having the same width. Furthermore, experiments show that the scaling factor is still not sufficiently accurate, as shown in Figure 3. Figures 3a and 3b show the drain saturation current calculated using the MSN-model together with (13) as well as the MSN-model together with the delay degradation factor given in [3]. As shown in the plots, the MSN-model along with (13) gives accurate current estimates. It has been noticed that in order to improve the accuracy of the delay degradation factor, one needs to take into account the variations of VDSAT 1 as a function of the device width. Example: In order to improve the drive strength of seriesconnected transistors, it is common to increase the widths of the transistors placed at the bottom (NMOS) or top (PMOS) away from the output node. Consider the case of four NMOS transistors connected in series, having sizes from top to bottom of 1×, 2×, 4×, and 8× the minimum size. Using HSPICE, the drain currents obtained are 190 µA and 109 µA as compared to 181 µA and 97 µA obtained using the MSN model for 0.25 µm and 0.18 µm technologies, respectively.

3.2

0.18 µm CMOS Process

0.25 µm CMOS Process PMOS NMOS

Parameters

Single Inverter Delay

We now demonstrate that the proposed MSN-model can also be used for accurate delay estimations. We use the same

NMOS

PMOS

0.930 1.000 0.555 0.069 0.460 0.886 0.9(VGS − VT H )0.5α

1.475 −1.120 −0.450 0.139 0.606 0.880 0.9(VGS − VT H )0.5α

delay model as [7] (shown here for clearness) vT H + α 1 CT VDD TP = − TIN + , 1+α 2 2ID

(14)

except that the drain current ID used is derived using equation (5). In this equation vT H = VT H /VDD , CT is the total capacitance discharged, TIN is the input rise/fall time, and ID is the drain saturation current with VGS = VDD . We compare in Table 2, the simulated and calculated values of delay for the MSN-model and the SN-model [2] for inverters with varying device widths, input rise times, and load capacitances. The SN-model parameters were derived for minimum-sized transistors in both technologies. As seen in Table 2, the MSN-model has an average error of 1.16% with a maximum of 2.72% and a standard deviation of 0.83%. In contrast, the SN-model achieves an average error of 11.4% with a maximum of 23.5% and a standard deviation of 8.18%. Note that the SN-model gives accurate results only when the device widths are minimum sized. Therefore the error in the delay calculations was mainly due to errors in the ID calculations.

3.3

Multistage Delay

Predicting the delay of the ith gate that resides within a chain of N gates requires an estimate of the input rise/fall time (TIN i ) of the ith gate. In particular, we take TIN i = 2TP (i−1) as an estimate of the input rise/fall time where TP (i−1) is the propagation delay of the previous stage. Note that TP i is given by (14). Figure 4 shows a good agreement between HSPICE delay and (14) (also using the modified SN-model) for different values of N in 0.25 µm and 0.18 µm CMOS processes.

3.4

CMOS Gate Design

The delay of CMOS gates can be approximated by constructing an equivalent inverter. This is an inverter where the pull-down NMOS and the pull-up PMOS transistors are resized to reflect the effective strength of the actual pull-down or pull-up path in the gate. Example: Consider the design of a complex CMOS gate implementing the logic function Z = ABC + D as shown in Figure 5. Assume the circuit is driving a load capacitance of 100 fF and needs to satisfy TP HL , TP LH ≤ 60 ps. We shall employ 0.18 µm process parameters for all calculations


0.25µm, 2.5V

−3

1

x 10

0.18µm, 1.8V

−4

8

x 10

___ HSPICE

___ HSPICE

* Delay degradation factor

0.8 MSN model

6 Id: Drain Current [A]


+

0.6

0.4

*

Delay degradation factor

+

MSN model

4

2

0.2

0 1

2

3

5

4

0 1

6

3 4 Number of Series Transistors

2

Number of Series Transistors

(a)

5

6

(b)

Figure 3. Current values in series-connected NMOS transistors. 0.25µm CMOS

0.18µm CMOS

2.5

2 HSPICE Level 49 Model Calculation

1.8 Wp

Wp

Wp

Wn

Wn

Wn

2

A

B

C

1.6

D

1.4

Z 1.5

W eq,p

Delay [ns]

Delay [ns]

1.2

1

A

1

W eq,n

0.8

B

0.6

0.5

D

0.4

C 0.2

Wn=0.36µm Wp=1.44µm

0

0

2

4 6 No. of Stages

8

10

0

Wn=0.22µm Wp=0.88µm

0

2

4 6 No. of Stages

8

10

Figure 4. Multistage inverter delay.

Figure 5. Complex CMOS gate example.

and simulations. We ignore self-capacitances in this analysis, although it could be easily added to the load capacitance as explained in [8, 11]. First we need to satisfy TP HL ≤ 60 ps. Substituting for the parameters in (5), we get:

B, and C, we choose WA,n = WB,n = WC,n = 0.83 µm. If we choose the discharge path as A, B, and C in HSPICE simulations, then we get a delay of 60.8 ps. A similar derivation is carried out for the PMOS network. Satisfying TP LH ≤ 60 ps, we get WA,p = WB,p = WC,p = WD,p = 11.3 µm. HSPICE simulation results for the pull-up network with the worst-case scenario of two series transistors being ON and the rest OFF, showed a delay of 58.8 ps. Therefore, the delay constraint of 60 ps is met. If the SNmodel were to be employed, then we get for the NMOS network: WD,n = 2.2 µm which corresponds to an HSPICE delay of 72 ps and WA,n = WB,n = WC,n = 0.73 µm with HSPICE delay of 69 ps. Similarly for the PMOS network, WA,p = WB,p = WC,p = WD,p = 9.1 µm which gives an HSPICE delay of 78.6 ps. As can be seen, the transistor sizing using the SN-model failed to meet the delay specifications when simulated using HSPICE.

I = Keq,n (1.8 − 0.56)0.93 (1 + 0.069 × 1.8) = 1.378Keq,n . The delay TP HL is then calculated using (14) with TIN = 0, to get TP HL =

100 × 10−15 × 0.9 ≤ 60 × 10−12 s. 1.378Keq,n

Hence, Keq,n ≥ 1.09 × 10−3 A/Vα . The equivalent transistor width is then calculated by solving for the positive root of (11) which gives Weq,n ≥ 2.5 µm. We can now choose WD,n = 2.5 µm for which we get a delay of 58.5 ps from HSPICE. For the remaining series transistors with inputs A,


Table 2. TP HL results for different inverter circuit configurations. Technology 0.25

Wp [µm] 1.44

Wn [µm] 0.36

TIN [ps] 50 100

1.44

50 100

1.44

2.88

50 100

4.32

50 100

0.18

0.88

0.22

45 75

0.88

45 75

0.88

1.76

45 75

2.64

45 75

CL [fF] 50 100 50 100 50 100 50 100 50 100 50 100 50 100 50 100 45 75 45 75 45 75 45 75 45 75 45 75 45 75 45 75

HSPICE [ps] 289.8 520.4 297.7 528.5 104.1 179.8 111.4 187.1 60.37 99.61 67.63 106.8 45.06 71.52 52.31 78.69 313.3 498.4 317.7 502.9 92.34 142.9 97.33 147.9 53.14 79.66 58.34 88.50 37.79 55.22 42.78 60.18

† B = 7.165 × 10−5 for 0.25 µm and B = 8.830 × 10−5 for 0.18 µm.

3.5

Sizing a Chain of Gates

K0 Ki

Wi CD + Wi+1 CG , CD + CG

Error-MSN [%] 0.81 0.28 0.90 0.37 0.71 1.67 0.41 1.46 2.72 0.42 2.89 0.75 2.61 1.61 0.94 2.48 0.03 1.15 0.02 1.19 2.30 0.62 1.43 0.09 2.65 0.56 0.79 1.19 0.85 0.71 1.34 1.13 1.16 0.83

Error-SN [%] 1.23 0.71 1.31 0.79 20.5 21.9 18.9 20.9 19.1 22.1 16.6 20.2 18.9 20.7 21.7 23.5 1.18 0.00 1.12 0.05 5.36 7.12 5.85 7.38 7.57 9.88 8.52 14.1 9.07 12.2 11.0 15.7 11.4 8.18

node:

Consider the example of sizing a chain of inverters designed to drive a large capacitive load with minimal propagation delay. The main objective of the problem is to choose a certain size Wi for the NMOS transistors in each of the N stages (see Figure 6a) to minimize delay. It is assumed that the PMOS transistors are greater than the NMOS transistors by a constant factor. Also, assume that each gate has an input capacitance per unit size of CG and a drain parasitic capacitance per unit size of CD . Let the final load be represented as: CL = WN +1 CG . We showed in section 2 that the transistor drain current is no longer linearly related to its width, and derived the K parameter equations (9)-(12). If a minimum sized gate (W0 ) has a delay of TP 0 while driving a load capacitance CD +CG , then the delay at each stage can be expressed in terms of the delay of the minimum sized gate as TP i = T P 0

SN-model† [ps] 286.2 516.7 293.8 524.3 82.75 140.4 90.32 147.9 48.83 77.64 56.40 85.21 36.53 56.73 40.98 60.23 317.0 498.4 321.3 502.6 87.39 132.7 91.64 137.0 49.12 71.79 53.37 76.04 34.36 48.48 38.06 50.73 Average Error Standard Deviation

MSN-Model [ps] 287.5 519.0 295.0 526.5 103.4 176.8 110.9 184.4 62.01 100.0 69.59 107.6 46.24 72.67 52.80 80.64 313.4 492.7 317.6 496.9 94.47 143.8 98.72 148.0 54.55 80.11 58.80 87.45 38.11 55.61 43.35 60.86

(15)

where Ki = K(Wi ), i = 0, 1, · · · , N . This makes the total delay (TD ) from the input terminal to the load capacitance

TD =

N i=1

TP 0

K0 Ki

Wi CD + Wi+1 CG . CD + CG

(16)

The minimum delay is obtained when all the partial derivatives of TD with respect to Wj are zero: Kj ∂TD CG CD = + − 2 (Wj CD + Wj+1 CG ) = 0, ∂Wj Kj−1 Kj Kj j =1, 2, · · · , N. Solving this equation gives an analytical expression for the optimum size of each gate: Kj CG CD + = 2 (Wj CD + Wj+1 CG ) , j = 1, 2, · · · , N. Kj−1 Kj Kj (17) Example: For the circuit shown in Figure 6b, we are given: CD = 1 nF per unit size, CG = 0.7 nF per unit size, and the inverter load W3 = 2 µm. We are asked to find W1 and W2 that minimizes the delay from the input to the output. Assume the PMOS transistor sizes are twice the size of their corresponding NMOS. Using (17), the two equations


W2

W1

WN

Wi

0.44µm

2W 2

2W 3

VIN

CG1

CD1

CG2

CD2

CGi

CDi

CGN

CDN

CL

4.0µm VOUT

0.22µm

(a)

W2

W3

2.0µm

(b)

Figure 6. (a) Chain of inverter circuits and (b) an example for N = 2. we need to solve are CG CD K + = 12 (W1 CD + W2 CG ) K0 K1 K1

Assuming a ramp input, these differential equations can be solved to give an expression for the gate delay with interconnect resulting in T P = TP 0 +

and CG CD K + = 22 (W2 CD + W3 CG ) . K1 K2 K2 The only unknowns in these equations are W1 and W2 . Solving these polynomial equations gives one positive real root which is W1 = 0.428 µm and W2 = 0.913 µm. HSPICE simulations using these sizes gives a delay of 140.7 ps. If we sweep W1 and W2 in HSPICE and measure the delay we find a minimum delay of 135.3 ps corresponding to W1 = 0.66 µm and W2 = 0.88 µm. Thus our estimates are relatively sufficient for quick hand calculations. Now, if we use the traditional super buffer design technique, discussed in [8], we first need to calculate the optimal scaling factor (S). Using CL = S N +1 CG = WN +1 CG we get S = 2.154. Therefore, W1 = 0.474 µm and W2 = 1.02 µm. HSPICE simulations with these sizes produces a delay of 193.5 ps. As can be seen, our delay analysis produced an error of 4% compared to 43% from the conventional super buffer design technique.

3.6

Circuits with Interconnect

The parasitic resistance of a metal or polysilicon line can have a significant influence on the signal propagation delay over the line. First, the delay with zero line resistance (TP 0 ) is estimated using the delay expression in (14) and substituting for CT the sum of the interconnect capacitance (CIN T ), the device’s parasitic capacitances (CD ), the effective gate capacitance (CG ), and the output load capacitance (CL ). If the interconnect resistance (RIN T ) is not zero and if the metal or polysilicon line is used for local interconnect (i.e., the interconnect delay is not the dominating delay factor), a simple π model can be used [9, 10]. This model places half the interconnect capacitance at the driver output and half at the load. These capacitances are separated by the interconnect resistance. Differential equations are then written for the voltage at the driver output (VD (t)) and the voltage at the load (VOU T (t)).

TIN T 1 TIN T 2 = TP 0 + TLIN T , TIN T 1 + TIN T 2

(18)

where TIN T 1 = RIN T (CD + CIN T /2), TIN T 2 = RIN T (CL + CIN T /2).

(19) (20)

The added delay due to the line resistance, namely local interconnect delay (TLIN T ), is therefore the final term in (18). The model in (18) is called the TLINT model. For long interconnects, where the interconnection delay becomes a dominant delay factor, the added delay is approximately that of a step input driving a distributed RC wire. The delay analysis of such RC networks requires either HSPICE simulations or other delay calculation methods such as the Elmore delay formula [8]. The gate delay with interconnect then becomes TP = TP 0 + TGIN T ,

(21)

TGIN T = RIN T (0.38CIN T + 0.69CL ).

(22)

where

The model in (21) is called the TGINT model. The plots in Figure 7a compare the TLINT (18) and TGINT (21) delay models through a 10-µm polysilicon line to HSPICE simulations for a wide range of driver sizes. As shown from the plots, the TLINT model fits HSPICE simulation results for large buffer sizes while not performing well, as expected, for smaller buffer sizes, where the interconnect delay is comparable to the buffer delay. The opposite is true for the TGINT model. It can be inferred from the plots that a general model can be obtained by taking a weighted average between the local interconnect model (TLINT) and the global interconnect model (TGINT). Hence, we propose the general interconnect model called the TINT model as follows: TP 0 TLIN T TP =TP 0 + TLIN T + TGIN T TP 0 + TLIN T TP 0 + TLIN T TP 0 + TGIN T =TP 0 + . (23) 1 + TP 0 /TLIN T


0.25mm, 2.5v CMOS Delay

0.25µm, 2.5v CMOS Delay

1.6

1.4

Interconnect delay is comparable to device delay

RINT

VD

VIN

1.2

HSPICE with interconnect General interconnect model HSPICE neglecting interconnect Model neglecting interconnect

3

VOUT

2.5 2W1

CL + CINT /2

8W1

RINT

VIN

Delay [ns]

CD+ CINT /2

Delay [ns]

3.5

TLINT Model SPICE TINT+Mod. SN-Model TGINT Model TINT+SN-Model

1

2 W1 =0.36µm

4W1

1.5

Interconnect delay dominates

0.8 1

0.6 0.5

0.4 0.6

0.8

1

1.2

1.4 1.6 Buffer Size [mm]

1.8

2

2.2

0

2.4

0

50

(a)

100 150 Interconnect Length [µm]

200

250

(b)

Figure 7. Delay with wire resistance for (a) variable buffer size and (b) variable wire length. Shown in the plots in Figure 7a are the delay calculation results using (23) with the SN-model (1) and the MSNmodel (5) employed to calculate TP 0 . For small buffer sizes, the SN-model results were 14% smaller than those obtained by HSPICE. This error decreases as the interconnect delay dominates over that of the device. On the other hand, the TINT model using the MSN-model to calculate TP 0 gives a maximum error of 2.6%. Figure 7b compares the equivalent input slew rate (TIN 2 ) found using HSPICE to the results of (23) using the MSNmodel for a minimum sized inverter driving a 4× the minimum size inverter through various wire lengths. As shown from the plots, the general interconnect model was able to predict the HSPICE simulation results over the range of interconnect lengths.

4

Conclusion

This paper provides a current model that accurately expresses the DSM CMOS I-V characteristics. The model is supported through comparisons between calculated and simulated values of the drain current drawn from CMOS inverter circuits over a large range of gate widths, loads with and without interconnect, and input ramp durations. We have also shown that the delay estimates using the MSN-model are also accurate compared to HSPICE. Further, the model is accurate in estimating the current flowing in series-connected transistors. By using 0.25 µm and 0.18 µm processes as reference, we have shown that the models can be used across DSM technologies. The proposed models base their validity on a set of process parameters that can be extracted directly from the SPICE models and experimental measurements. This capability permits the IC designer to easily estimate the current flowing in a CMOS circuit without resorting to time consuming circuit simulations.

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