MONOLITHIC INTEGRATED SOLAR E NERG Y HARVESTING SYSTEM Edgardo Mendez-Delgado*, Guillermo Serranot and Eduardo I. Ortiz-Rivera+
University of Puerto Rico - Mayagiiez Department of Electrical and Computer Engineering, Mayagiiez, P.R. 0081-9042 Email: *
[email protected]; t
[email protected];
[email protected] ABSTRACT
Monolithic Integrated Solar Energy Harvesling System Maximum Power Point Tracking
This paper presents a monolithic integrated solar energy harvesting circuit. Solar energy is harvested by CMOS Photo diodes fabricated on the same die as the power management circuits. The complete system includes a maximum power point tracking scheme, the use of a charge pump to increase the harvested voltage and regulation for load and power supply changes. Low power operation of the circuits is achieved through the use of sub-threshold and floating-gate design techniques. Simulated results using a photodiode model as the power supply show the feasibility of the proposed system.
Array
INTRODUCTION
The emergence of remote wireless sensors has created the need for low power, portable, and efficient integrated systems. Energy scavenging from the Sun has become a solution to power these systems without the need of batteries. Most of the published work have not been able to develop a single integrated system as they typically use discrete components for step-up conversion [1],external CPU's [2] and off chip PV cells [1]. Recently it has been demonstrated that integrated photodiodes can supply sufficient energy to low power inte grated circuits. These photodiodes are based on CMOS passive pixels and use multiple interconnect metal layers for three purposes: connecting the terminals of the diodes, store energy, and to diffract light. It has been shown that a single diode under 20 kLUX of incident white light intensity can deliver approximately 225f.LW/mm2 [3] for a 0.35 CMOS process. This work seeks to develop a monolithic integrated solar en ergy harvesting system including the PV cells in the same die that can serve as platform for future wireless sensor nodes.The proposed approach merges a Maximum Power Point Tracking scheme along with analog low-power and floating-gate IC design techniques in the design of a solar powered system. Figure I shows the block diagram of the proposed microelec tronic integrated system. First, energy conversion is performed with an array of p-dif/n-well photodiodes. Second, optimal energy transfer is enabled through the implementation of the Linear Reoriented Coordinate Method [4], [5]. An auxiliary photodiode array will be used to power up all these circuitry. Next, the stored voltage is then increased with a charge pump circuit. Finally the output voltage is regulated for load and power supply changes.The use of at least two external capacitances are needed to store charge after the MPPT stage and the output of the charge pump.
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Fig. 1.
Block diagram of the proposed Monolithic Integrated Solar System
ENERGY HARVESTING
CMOS photodiodes have been studied in previous works where different topologies and some techniques using up to six metal layers to diffract the sunlight have been investigated to increase the photocells efficiency. Both the layout geometry of the cells and the connection of the p-n junctions have been found to affect the efficiency. The types of connections for a standard CMOS process are n-well/substrate, n-well/p-diff and n-well/p-diff/substrate. The first is similar to the passive pixel structure used in imagers, the second can be used as a floating diode but has losses because of the parasitic diode formed by the n-well and the substrate and the third one is used to connect the substrate to the p-diff making this cell the more efficient as the current generated by the parasitic diode is added to the harvester diode current. To be able to implement the photodiodes in a single die with the circuits in a standard CMOS n-well process an n-well/p-diff floating diode must be used. In this case the n-well has to be connected to the substrate because it is usually the lowest potential. This connection short-circuits the parasitic diode formed by the n-well/substrate junction which limits the efficiency of the cell by reducing the photo generated current. In [6] the efficiencies for the different p-n junction connections are shown and for a specific structure the short-circuit connection reduces the current by 4 times. This value can be taken as an approximation of the effect of this connection in the design and simulations of the PV cells. For this work, floating n-well/p-diff diodes were designed since it is the only option to make the complete integrated solar
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problems in most efficient conditions. The Linear Reoriented Coordinates Method [7] models the behavior of a PV cell where the relation of the current I is related to the voltage V across the diode by Fig. 2.
I( V)
Metal 3 Parasitic diodes
Fig. 3.
p. Ix
Top view and cross section of a single photodiode structure
Top view of two diodes connected in series, shielded with metal 3
=
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. 1
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where Ix and Vx are the short-circuit and the open circuit voltage respectively, s is number of cells in series, p are the number of cells in parallel and the characteristic constant b was calculated using an algorithm based on the Fixed Point Theorem. The LRCM has the advantage that it can work for any type of solar cell and can be applied to integrated photo cells since it doesn't depends on the size and doesn't require specific parameters from the material of the PV cell.
to reduce the parasitic currents
system. The layout of the diodes is presented in Fig. 2 and its based on [3]. The structure was chosen for its simplicity and efficiency, in our work the metal connections are not used as integrated capacitors. Arrays of these structures were connected in parallel to be able to obtain sufficient current from the cells. To have sufficient voltage to power the circuits of the harvester an auxiliary diode array consisting of four of these diode arrays in series are needed. The connection of the diodes in series represents a problem because the parasitic diodes would consume a considerable amount of current. To try and lower this influence the surroundings of the diodes where covered with metal 3 (Fig.3) so that the parasitic current could be reduced. MAXIMUM POWER POINT TRACKING
Integrated photocells have a low and limited power because of the variations of illumination affecting the maximum power that should be obtained at all times. A maximum power point tracking (MPPT) will be used in our design to solve these 0.6
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�
0.4
_
lap-Ix '
[
(=t-) (-1) 1- exp b
1 - b + b . exp
1
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(3)
The characteristic curves of the PV cell are shown in Fig.4. Values for the short-circuit current and open circuit voltage were taken from the literature based on the type and geometry of the diodes. These values are Vx .479V, Ix 5.9 JLA and b 0.0747. Using the values of the PV cell mentioned before Vap and lap are 0.386V and 5.51JLA respectively. In our MPPT scheme the open circuit of the photodiode is constantly sampled to obtain the optimal value of the voltage under changing illumination conditions. This can be done because Vap is simply the multiplication of the open-circuit voltage by a constant factor, in our case 0.8l. =
=
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CIRCUIT IMPLEMENTATION
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Using the LRCM, we can obtain a a very close approximate to the optimal values of voltage Vap and current lap of the photodiode to calculate the maximum power using linear equations given by (2) and (3).
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The main focus for the design of this solar system is power reduction in the harvester circuit to make the use of the available power of the PV cells more efficient. For this purpose all of the active circuitry on the harvester will be working on the sub-threshold region. Another technique used in the design are floating-gate transistors. Floating-gates permit the programming of a desired DC voltage in the gate of a transistor making possible to reduce its threshold volt age, allowing operation at lower voltage supplies. A detailed method for programming floating-gates are discussed in [8]. The simulations for the complete harvesting circuit were done using a model for a 0.5JLm process.
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VChold for different loads. It can be seen how the voltage is maintained at the optimal voltage.
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l _____________________
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Schematic of the proposed charge pump. Floating-gate diode
connected transistors are used to reduce losses.
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Fig. 13.
Vq=-O.6V
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Fig. 12.
3 Time (ms)
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6
Output of the charge pump with different programmed voltages.
will be 3Vap - 2VD. An additional diode voltage drop can be seen due to D2, indicating an increase of diode voltage drops with the number of stages and degrading the charge pump efficiency. Observe that half period of the clock is used to step up the voltage in each stage. Therefore, an additional charge pump with the clk signals inverted and connected to the same load was implemented. This implementation allows an increase in voltage for both charge pumps in each half period respectively, thus taking the advantage of the full period of the clock. In addition, more current can be provided than a single charge pump. The proposed diode configuration, shown in the dashed lines in Fig. 11, is implemented with a diode-connected floating gate transistor. This configuration allows the manipulation of the transistor threshold voltage by modifying the charges in node Vq. Consequently, the diode voltage drop (drain-to-source voltage) will be reduced improving the charge pump efficiency. Figure 12 shows the charge pump output voltage for dif ferent floating gate charges. An increase in the output voltage can be seen with the addition of negative charges in the diode connected transistor. A maximum voltage of 2.1SV is obtained
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3 Time (ms)
4
6
5
Output of the charge pump for multiple loads.
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Fig. 14.
Transient response for the complete system from the moment light
hits the photodiodes to the moment the charge pump charges the capacitor to 2.1
V.
injecting O.8V in the proposed diode. Figure 13 shows the charge pump output voltage for different current loads. RESULTS
Figure 14 presents the simulated behavior of the complete system where it can be seen how Vaux starts to charge a SOOnF capacitor to 1.9 V. When the auxiliary cell voltage is enough to start the current reference, the hysteresis comparator starts to work immediately making a transition to a digital 1 which means the energy harvester doesn't have any power. When the auxiliary photo diode reaches 1.7 V the comparator state changes to a digital 0 and connects the harvester circuit to the auxiliary photodiode voltage. When the circuits have power it is seen how the voltage at VChold tends to Vap and the charge pump increases the voltage at Cload to 2.1 V.
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A complete solar scavenging system on a chip has been pro posed to power remote wireless sensors. Hardware implemen tation of the Linear Reoriented Coordinates Method will allow for on-chip optimal energy transfer. Low-voltage and low power operation is enabled through the use of sub-threshold and floating-gate design techniques. It has been demonstrated through simulations the feasibility of the proposed design. This material is based upon work supported by the National Science Foundation under Grant No. 0927011. R E F E R E NC E S [1] D. Dondi, A. Bertacchini, L. Larcher, P. Pavan, D. Brunelli, and L. Benini, "A solar energy harvesting circuit for low power applica tions," in Sustainable Energy Technologies, 2008. ICSET 2008. IEEE International Conference on, 24-27 2008, pp. 945 �949. [2] C. Alippi and C. Galperti, "An adaptive maximum power point tracker for maximising solar cell efficiency in wireless sensor nodes," in Circuits and Systems, 2006. ISCAS 2006. P roceedings. 2006 IEEE International Symposium on, 0-0 2006, p. 4 pp. [3] N. Guilar, A. Chen, T. Kleeburg, and R. Amirtharajah, "Integrated solar energy harvesting and storage," in Low Power Electronics and Design, 2006. ISLPED '06. P roceedings of the 2006 International Symposium on, 4-6 2006, pp. 20 �24. [4]
E. Ortiz Rivera and F. Peng, "Linear reoriented coordinates method,"
in Electro/information Technology, 2006 IEEE International Conference on, 7-10 2006, pp. 459 -464.
[5]
E. Ortiz-Rivera and F. Peng, "Analytical model for a photovoltaic module using the electrical characteristics provided by the manufacturer data sheet," in Power Electronics Specialists Conference, 2005. PESC '05. IEEE 36th, 16-16 2005, pp. 2087 �209J.
[6] C. Alippi and C. Galperti, "Integrated micro-solar cell structures for harvesting supplied microsystems in 0.35-um; cmos technology," in Sensors, 2009 IEEE, 25-28 2009, pp. 542�545. [7]
E. rtiz Rivera and F. Peng, "A novel method to estimate the maximum power for a photovoltaic inverter system," in Power Electronics Special
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A. Bandyopadhyay, G. Serrano, and P. Hasler, "Adaptive algorithm using hot-electron injection for programming analog computational memory elements within 0.2 percent of accuracy over 3.5 decades," Solid-State Circuits, IEEE Journal of, vol. 41, no. 9, pp. 2107 �2ll4, sept. 2006.
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