MOS Transistor

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EE141. 3. EECS141. Class Material. ❑ Last lecture. ▫ CMOS manufacturing process. ▫ Design rules. ❑ Today's lecture. ▫ MOS transistor operation and modeling.
EE141

EE141-Spring 2007 Digital Integrated Circuits

Announcements ‰ Lab

starts next week!

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Lecture 4 MOS Transistor

‰ Homework

#1 is (was) due today ‰ Homework #2 posted, due next Th 5pm 1

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Class Material ‰ Last

lecture

ƒ CMOS manufacturing process ƒ Design rules ‰ Today’s

MOS Transistor

lecture

ƒ MOS transistor operation and modeling ‰ Reading

(3.3.1-3.3.2)

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What is a Transistor?

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Switch Model of MOS Transistor G

A MOS Transistor

|VGS|

A Switch!

S

G |VGS| S

|VGS| ≥ |VT| D

S

Ron

Ron

D S

D |VGS| < |VT|

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D

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S

D |VGS| > |VT| 6

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MOS Transistors: Types and Symbols

NMOS and PMOS

D

NMOS Transistor

PMOS Transistor

G

G

VGS > 0 D

G

G

S NMOS Depletion

S NMOS Enhancement

VGS < 0

S

D

D

S

D

D

G S PMOS Enhancement 7

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Threshold Voltage: Concept S –

VG S

VT = VT 0 + γ ⋅ ‰ Fermi

n+

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The Threshold Voltage

D

G

S NMOS with Bulk Contact

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‰ Threshold +

B

G

(

2φF + VSB − 2φF

)

potential

n+

n-channel

N φF = φT ⋅ ln A ni

Depleti on region

2ΦF is approximately −0.6V for p-type substrates γ is the body factor VT0 is approximately 0.45V for our process

p-substrate B 9

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The Body Effect

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Transistor in Linear Mode

0.9

VGS > VDS + VT

0.85 0.8

S

VGS

VDS G

0.75

ID

D

n+

0.65

T

V (V)

0.7



V(x)

n+

+

0.6

L

x

0.55 0.5

reverse body bias

p-substrate

VT0

0.45 0.4 -2.5

-2

-1.5

-1

V EE141 EECS141

BS

-0.5

B

0

(V) 11

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The Drain Current ‰

The Drain Current

Charge in the channel is controlled by the gate voltage: Q i ( x ) = −Cox ⋅ [VGS − V ( x ) − VT ]

‰

Cox =

‰

Combining velocity and charge: ID ⋅ dx = μ n ⋅ Cox ⋅ W ⋅ (VGS − V − VT ) ⋅ dV

ε ox ‰

tox

Integrating over the channel:

Drain current is proportional to charge and velocity:

ID = k n’ ⋅

I D = − υn ( x ) ⋅ Q i ( x ) ⋅ W

υn ( x ) = −μ n ⋅ ξ( x ) = μ n ⋅

Transconductance:

dV dx 13

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‰

VGS

For VGD < VT, the drain current saturates: k’ W ID = n ⋅ ⋅ (VGS − VT )2 2 L

VDS > VGS - VT

G

μ ⋅ε k n’ = μ n ⋅ Cox = n ox t ox

Saturation

Transistor in Saturation VT < VGS < VDS + VT

V2 ⎤ W ⎡ ⋅ ⎢(VGS − VT ) ⋅VDS − DS ⎥ L ⎢ 2 ⎥ ⎦ ⎣

D

S

‰ n+

-

VGS - VT

+

Including channel-length modulation:

n+

k’ W ID = n ⋅ ⋅ (VGS − VT )2 ⋅ (1 + λ ⋅ VDS ) 2 L CLM

Pinch-off 15

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Current-Voltage Relations: A Good Ol’ Transistor

Modes of Operation Cutoff: VGS < VT

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ID = 0

6

x 10

-4

VGS= 2.5 V

5

VGS > VDS + VT

Saturation: VT < VGS < VDS + VT

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ID = k n’ ⋅

W L

⎡ V2 ⎤ ⋅ ⎢(VGS − VT ) ⋅ VDS − DS ⎥ 2 ⎥ ⎢ ⎦ ⎣

Resistive

k’ W ID = n ⋅ ⋅ (VGS − VT )2 2 L

VGS= 2.0 V 3

VGS= 1.5 V

1

VGS= 1.0 V 0

0.5

1

1.5

VDS (V) EE141 EECS141

Quadratic Relationship

VDS = VGS - VT

2

0

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Saturation

4

ID (A)

Resistive (Linear):

2

2.5

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Current-Voltage Relations: The Deep Sub-Micron Transistor

A Model for Manual Analysis VDS > VGS – VT

D

2.5

-4

Early Saturation

VGS= 2.5 V

Resistive:

VDS < VGS – VT

ID

VGS= 2.0 V 1.5

V2 ⎤ W ⎡ ID = k n’ ⋅ ⋅ ⎢(VGS − VT ) ⋅ VDS − DS ⎥ L ⎢ 2 ⎥ ⎣ ⎦

S

with

VT = VT 0 + γ ⋅

(

2φF + VSB − 2φF 19

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)

0

Linear Relationship

VGS= 1.5 V

1

VGS= 1.0 V

0.5

0

0.5

1

1.5

2

2.5

VDS (V)

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Velocity Saturation

Velocity Saturation Velocity saturates due to carrier scattering effects

ID Long-channel device

υ n (m/s)

‰

x 10

2

ID (A)

G

Saturation:

k’ W ID = n ⋅ ⋅ (VGS − VT )2 ⋅ (1 + λ ⋅ VDS ) 2 L

υsat = 105

VGS = VDD Short-channel device

Constant velocity

Constant mobility (slope = µ)

V DSAT

ξc = 1.5

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Regions of Operation

-4

x 10

6

-4

x 10 2.5

x 10

-4

2.5

VGS= 2.5 V

5 5

Resistive

2 4

1

Saturation VGS= 2.0 V

3

VGS= 1.5 V

1

VGS= 1.0 V

2 0.5

1 0 0

0.5

1

1.5

2

VGS(V)

Long Channel (L=2.5μm) EE141 EECS141

2.5

0 0

0 0

quadratic 0.5

1

1.5

2

0.5

1

1.5

2

-4

Velocity Saturation

VGS= 1.0 V

0.5

2.5

0

VGS= 2.0 V VGS= 1.5 V

1

0

VDS (V)

2.5

VGS= 2.5 V

Resistive

1.5

VDS = VGS - VT

2

x 10

2

ID (A)

ID (A)

ID (A)

linear

1.5

quadratic

ID (A)

4 3

VDS

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ID versus VGS 6

VGS - V T

ξ (V/µm)

0.5

1

1.5

2

2.5

VDS (V)

VGS(V)

Short Channel (L=0.25μm) 23

Long Channel (L=2.5μm) EE141 EECS141

W/L=1.5

Short Channel (L=0.25μm) 24

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Regions of Operation

Including Velocity Saturation 6

Approximate velocity:

x 10

-4

2.5

VGS= 2.5 V

Resistive

Saturation

1.5

VDS = VGS - VT

2

VGS= 1.5 V

1

VGS= 1.0 V

0 0

VGS= 2.0 V

VGS= 2.0 V

3

0.5

1

1.5

VGS= 1.5 V

1

VGS= 1.0 V

0.5

2

2.5

0

0

VDS (V)

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Regions of Operation – Simplified ‰

2.5

x 10

1

1.5

2

2.5

W/L=1.5

Short Channel (L=0.25μm) 26

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A Unified Model for Manual Analysis

VDSAT ≈ L·ξc

Define VGT = VGS – VT

0.5

VDS (V)

Long Channel (L=2.5μm)

In deep submicron, there are four regions of operation: (1) cutoff, (2) resistive, (3) saturation and (4) velocity saturation

VGS= 2.5 V

2

ID (A)

ID (A)

And integrate current again:

-4

Early Saturation

5 4

x 10

-4

define VGT = VGS – VT

VDS = VDSAT 2

Velocity Saturation

Linear

for VGT ≤ 0: ID = 0

G

ID (A)

1.5

Linear Relationship

1

VDS = VGT 0

ID

VDSAT = VGT

0.5

0

B

Saturation

0.5

1

1.5

ID = k '⋅

W L

⎛ V2 ⎞ ⋅ ⎜VGT ⋅ Vmin − min ⎟ ⋅ (1 + λ ⋅ VDS ) ⎜ 2 ⎟⎠ ⎝

2.5

VDS (V)

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Simple Model versus SPICE x 10

for VGT ≥ 0:

with Vmin = min (VGT, VDS, VDSAT) 2

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2.5

D

S

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Transistor Model for Manual Analysis

-4

VDS=VDSAT 2

Velocity Saturated

ID (A)

1.5

Linear 1

VDSAT=VGT 0.5

VDS=VGT 0

0

0.5

Textbook: page 103

Saturated 1

1.5

2

2.5

VDS (V)

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A PMOS Transistor

Next Lecture

-4

0

x 10

‰ Using

VGS = -1.0V

the MOS model:

ƒ Inverter VTC and delay

-0.2 VGS = -1.5V

ID (A)

-0.4

-0.6

-0.8

-1 -2.5

VGS = -2.0V

Assume all variables negative!

VGS = -2.5V

-2

-1.5

-1

-0.5

0

VDS (V)

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