Multi-Port High Voltage Gain Modular Power Converter for ... - MDPI

sustainability Article

Multi-Port High Voltage Gain Modular Power Converter for Offshore Wind Farms Sen Song 1 , Yihua Hu 1 Xianming Ye 4 1 2 3 4

*

ID

, Kai Ni 1, *

ID

, Joseph Yan 1 , Guipeng Chen 2 , Huiqing Wen 3 and

Department of Electrical Engineering and Electronics, The University of Liverpool, Liverpool L69 3BX, UK; [email protected] (S.S.); [email protected] (Y.H.); [email protected] (J.Y.) College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China; [email protected] Department of Electrical Engineering and Electronics, Xi’an Jiaotong-Liverpool University, Suzhou 215123, China; [email protected] Department of Electrical, Electronic and Computer Engineering, University of Pretoria, Pretoria 0084, South Africa; [email protected] Correspondence: [email protected]; Tel.: +44-751-920-3720

Received: 30 May 2018; Accepted: 25 June 2018; Published: 26 June 2018

Abstract: In high voltage direct current (HVDC) power transmission of offshore wind power systems, DC/DC converters are applied to transfer power from wind generators to HVDC terminals, and they play a crucial role in providing a high voltage gain, high efficiency, and high fault tolerance. This paper introduces an innovative multi-port DC/DC converter with multiple modules connected in a scalable matrix configuration, presenting an ultra-high voltage step-up ratio and low voltage/current rating of components simultaneously. Additionally, thanks to the adoption of active clamping current-fed push–pull (CFPP) converters as sub-modules (SMs), soft-switching is obtained for all power switches, and the currents of series-connected CFPP converters are auto-balanced, which significantly reduce switching losses and control complexity. Furthermore, owing to the expandable matrix structure, the output voltage and power of a modular converter can be controlled by those of a single SM, or by adjusting the column and row numbers of the matrix. High control flexibility improves fault tolerance. Moreover, due to the flexible control, the proposed converter can transfer power directly from multiple ports to HVDC terminals without bus cable. In this paper, the design of the proposed converter is introduced, and its functions are illustrated by simulation results. Keywords: high voltage direct current (HVDC); power transmission; DC/DC converter; high voltage gain; modular; multi-port

1. Introduction The global number of offshore wind farms has increased in recent years [1,2]. In Europe, 560 new offshore wind turbines were built in 17 wind farms in 2017 with a total generation capacity of 3148 MW, which is about 20% of the total offshore generation capacity [3]. The power generated offshore is typically transmitted over an average distance of 41 km (in 2017) through submarine cables before reaching a connection point with the existing onshore grid [3]. For example, Hornsea wind farm is located around 40 km from the onshore station. Compared with high voltage alternating current (HVAC) transmission, high voltage direct current (HVDC) transmission is the preferred method to transfer power over a long distance (>40 km) in terms of the factors of economy and power efficiency [4,5]. When delivering the same amount of power, the purchase price for the bipolar HVDC cable is lower than that of two parallel 3-core HVAC ones [6]. Additionally, HVDC has a higher transmission efficiency than HVAC since no inductance-reactive power exists within DC transmission cables. Sustainability 2018, 10, 2176; doi:10.3390/su10072176

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transmission efficiency than HVAC since no inductance-reactive power exists within2 ofDC 15 transmission cables. Figure 1 presents three HVDC configurations. The hybrid HVDC system illustrated in Figure 1a 1 presents HVDC configurations. The hybrid HVDC systemhigh illustrated Figure 1a uses Figure a medium voltagethree (MV)—high voltage (HV) AC/DC converter to obtain voltageinDC power. uses a medium voltage (MV)—high voltage (HV) AC/DC converter to obtain high voltage DC power. However, line-frequency (50/60 Hz) AC/AC transformers for low-voltage (LV)—MV conversion still However, line-frequency (50/60 Hz)substation AC/AC transformers low-voltage (LV)—MV conversion occupy a significant portion of the space. In thisfor topology, the transformer is replacedstill by occupy a significant portion of the space. In this topology, the transformer is replaced by a a converter as shown in Figure 1b,substation which significantly reduces the system size and weight [7]. These converter as shown inuse Figure 1b, which significantly system level size and These two two configurations two-stage conversion to reduces meet thethevoltage of weight HVDC [7]. transmission. configurations use two-stage conversion to meet the voltage of HVDC transmission. However, However, Reference [8] points out that the configuration of level two DC/DC conversion stages has the Reference [8] points out that configuration twoofDC/DC conversionstage stages has the highest power highest power loss, which is the around four timesofthat a one conversion configuration presented loss, which1cistaking aroundinto fourconsideration times that of the a one conversion configuration presented in the Figure 1c in Figure winding and stage core losses of transformers and given taking into of consideration the winding core losses of transformers andonly the provides given datasheets of the datasheets the semiconductors. The and converter applied in Figure 1c not a high voltage semiconductors. The converter applied in multiple Figure 1cgenerators not only provides high voltage gainbus butcable. also gain but also transfers power directly from to HVDCaterminals without transfers power design directlyisfrom multiple challenge generatorsfor to HVDC terminals without The converter The converter a technical boosting LV directly to bus HV cable. due to the conflict design is athe technical challenge for boosting directly the conflict between theratings required between required high voltage level,LV e.g., ±800 to kVHV [9]due andto the restricted voltage of high voltage level, e.g., ± 800 kV [9] and the restricted voltage ratings of semiconductor components, semiconductor components, e.g., 22 kV for SiC thyristors, and 15 kV for SiC transistors [10]. e.g., 22 kV forwith SiC thyristors, and 15 kV for SiC transistors [10]. Fortunately, with the development of Fortunately, the development of semiconductors and converter topologies, possible solutions semiconductors and converter topologies, possible solutions are provided [11–13]. are provided [11–13].

Sustainability 2018, 10, 2176

GB

LV AC Bus

LV-MV AC/AC

MV-HV AC/DC

GB

=

AC/DC

HVDC transmission

AC/DC/AC

. . .

GB

Wind Turbine Generators

LV-MV DC/DC

GB

= . . .

AC/DC

MV-HV DC/DC

=

. . .

AC/DC/AC

MV DC Bus

= =

HVDC transimission


= =

(a)

(b) LV-HV DC/DC


GB

=

. . .

= GB

HVDC transimission

AC/DC

AC/DC

(c) Figure 1. High voltage direct current (HVDC) configurations for wind power transmission: (a) DCFigure 1. High voltage direct current (HVDC) configurations for wind power transmission: based connection with two-stage hybrid hybrid conversion; (b) DC-based connection with two-stage DC/DC (a) DC-based connection with two-stage conversion; (b) DC-based connection with two-stage conversion; (c) DC-based connection with the proposed modular converter. DC/DC conversion; (c) DC-based connection with the proposed modular converter.

To address the challenges, DC converters with high voltage gains [14–17], modular multilevel To address the challenges, DC converters with high voltage gains [14–17], modular multilevel converters (MMCs) [18–22] and multi-module converters [23–25] are studied extensively. Although converters (MMCs) [18–22] and multi-module converters [23–25] are studied extensively. dual-active bridge (DAB) converters [14,15] and resonant converters [16,17] can obtain high voltage Although dual-active bridge (DAB) converters [14,15] and resonant converters [16,17] can obtain step-up ratios, the voltage stress on their semiconductor components is high, which can be reduced high voltage step-up ratios, the voltage stress on their semiconductor components is high, which can by applying MMCs. By adding sub-modules (SMs), a high output voltage is achieved without be reduced by applying MMCs. By adding sub-modules (SMs), a high output voltage is achieved increasing the voltage stress. However, the MMC topologies based on half-bridge (HB) or full-bridge without increasing the voltage stress. However, the MMC topologies based on half-bridge (HB) or (FB) [18,19] and resonant MMC [20] cannot provide electrical isolation. The isolated MMCs in full-bridge (FB) [18,19] and resonant MMC [20] cannot provide electrical isolation. The isolated MMCs References [21,22] are presented with DC/AC/DC configuration, where medium-frequency high in References [21,22] are presented with DC/AC/DC configuration, where medium-frequency high turns-ratio transformers are employed, resulting in a vast volume. Although resonant MMCs [26]


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turns-ratio transformers are employed, resulting in a vast volume. Although resonant MMCs [26] achieve galvanic isolation and a small volume of transformers at the same time, its conversion ratio Sustainability 2018, 10, 2176 3 of 15 only satisfies MV applications. Alternatively, transformers can be decentralized into multi-module converters, enabling the installation of high-frequency transformers, which reduces the sizes of achieve galvanic isolation and a small volume of transformers at the same time, its conversion ratio transformers and reactive components. However, by adopting active-clamping flyback–forward only satisfies MV applications. Alternatively, transformers can be decentralized into multi-module converters as SMs, the currents of different SMs are unbalanced because of the non-ideal factors such converters, enabling the installation of high-frequency transformers, which reduces the sizes of as unequable leakage inductances of transformers, and only half of the power switches can achieve transformers and reactive components. However, by adopting active-clamping flyback–forward zero voltage switching (ZVS), resulting in high lossesbecause [23]. of the non-ideal factors such converters as SMs, the currents of different SMsswitching are unbalanced In paper,leakage based on the multi-modular converter in Reference active-clamping currentas this unequable inductances of transformers, and only half of the [23], power switches can achieve fed push–pull (CFPP) converters are adopted replace losses the flyback–forward SMs. The currents of zero voltage switching (ZVS), resulting in hightoswitching [23]. modules in series-connection auto-balanced, and allinpower switches can achieve soft-switching. In this paper, based on are the multi-modular converter Reference [23], active-clamping current-fed push–pull (CFPP) convertersand are adopted to replace flyback–forward SMs. The modules Therefore, control complexity switching loss arethe reduced. Furthermore, thecurrents matrix of configuration in series-connection are auto-balanced, and all power switches can achieve soft-switching. Therefore, brings about high control flexibility, which improves the fault tolerance capability. Additionally, control complexity and switching Furthermore, thanks to the independent operationloss of are eachreduced. port, the converter the can matrix collectconfiguration power frombrings multiple about high control flexibility, which improves the fault tolerance capability. Additionally, thanks to the sources without bus cable. independent operation of each port, the converter can collect power from multiple sources without The paper is organized as follows: The basic cell and two interleaved working modes are bus cable. analyzed in Section 1; the scalable topology design is discussed in Section 3; Section 4 depicts the fault The paper is organized as follows: The basic cell and two interleaved working modes are analyzed tolerance strategies of the topology; simulation resultsinare presented in 4Section to fault demonstrate in Section 1; the scalable topology design is discussed Section 3; Section depicts5the tolerance the effectiveness and efficiency of the converter, and finally, conclusions are drawn in Section 4. strategies of the topology; simulation results are presented in Section 5 to demonstrate the effectiveness and efficiency of the converter, and finally, conclusions are drawn in Section 4.

2. Analysis of the Basic Cell and Working Strategies of Matrix Configuration 2. Analysis of the Basic Cell and Working Strategies of Matrix Configuration

2.1. Operation of the Basic Cell

2.1. Operation of the Basic Cell

The The basic cellcelltopology basedonon CFPP converter in2 Figure 2 has similar operation basic topology based CFPP converter shownshown in Figure has similar operation principles principles and characteristics as the converter presented in Reference [27]. S 1–S2 are the two main and characteristics as the converter presented in Reference [27]. S1 –S2 are the two main switches. switches. Sc1are –Sc2the aretwo theactive two clamping active clamping Cc is the clampLcapacitor. L1 is the input Sc1 –Sc2 switches.switches. Cc is the clamp capacitor. 1 is the input transistor. transistor. The tri-winding transformer hasratio a turns ratio of sN=p11:1:n :Np2:N s =leakage 1:1:n and leakage Linductance The tri-winding transformer has a turns of Np1 :Np2 :N and inductance k at the secondary side. Furthermore, the secondary circuit consists of four rectifier diodes D –D , one output Lk at the secondary side. Furthermore, the secondary circuit consists of four rectifier D1–D4, 1 4 diodes capacitor Cout andCaout load one output capacitor andresistor a loadR.resistor R. L1 Np1

Np2 D1

Sc1

Vin

D3

Sc2 is

Ns

Lk

+ vs Cc

Cout S1

S2

D2

R

D4

Figure 2. Topology of the basic cell based fedpush–pull push–pull (CFPP) converter. Figure 2. Topology of the basic cell basedon onactive-clamping active-clamping fed (CFPP) converter.

The key operating waveforms are depicted depictedinin Figure 3. V–V gs1–Vgs2 are the control The key operating waveformsofofCFPP CFPP cell cell are Figure 3. V gs1 gs2 are the control ◦ . VVgsc1–V signals for the main switches S1–S 2, which have the phase shift angle of 180°. –Vgsc2 gsc2 are signals for two the two main switches S1 –S , which have the phase shift angle of 180 are the gsc1 2 control signals for the two clamp switches S c1 -S c2 . The control signals of the main switches the control signals for the two clamp switches Sc1 -Sc2 . The control signals of the main switches and and clamping switches areare complementary. drain-to-source voltages of the clamping switches complementary. vvds1 –vds2 and vdsc1 –vdsc2 are the drain-to-source voltages of the ds1–v ds2and dsc1–v dsc2are switches clamping switches respectively.iL1iL1 thecurrent currentof ofinput input inductor inductor LL11.. vvss and mainmain switches and and clamping switches respectively. is isthe and iiss are are the secondary voltage and current of the transformer respectively. The following assumptions are are the secondary voltage and current of the transformer respectively. The following assumptions made to simplify the analysis. made to simplify the analysis.

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Vgs1

Vgsc1 t

Vgsc2

Vgs2 t

vdsc1

vds1

vds2

vdsc2

t t

vs

t is

t

iL1 t0

t 1 t 2 t3 t 4 t5

t6 t7 t8 t9 t10

t

Figure 3. 3. Operating Operating waveforms waveforms of of the the basic basic cell. cell. Figure

• • • •

All switches and diodes are identical. All switches and diodes are identical. The capacitance of clamp capacitor is large enough so that its voltage ripple can be ignored. Due The capacitance of operation, clamp capacitor large enough so that its voltage ripple beDignored. to the symmetrical a briefisintroduction of the operation during t0–t5 can when ≤ 0.5 is Due to the symmetrical operation, a brief introduction of the operation during t –t when D ≤ 0.5 0 5 presented in this part. is presented in this part. Mode 1 (t0–t1): In this mode, the main switch S1 and the clamping switch Sc2 are on. The power Mode 1 (t0to–tthe this mode, the main the clamping Sc2secondary are on. The poweris is transferred output. The diodes D2switch and D3Sare forward biased,switch and the current 1 ): In 1 and is transferred to the output. The diodes D2 and D3 are forward biased, and the secondary current decreases. is decreases. Mode 2 (t1–t2): At t1, the main switch S1 is turned off. The leakage inductances Lk resonate with Mode 2 capacitances (t1 –t2 ): At t1, of theS1main S1the is turned leakage inductances Lk resonate with the parasitic and Sswitch c1. Then, voltageoff. of SThe C1 drops to zero at t2 to achieve ZVS turnthe capacitances of S1 and Then, the voltage of SC1 drops to zero at t2 to achieve ZVS on. parasitic At the same time, capacitance CS1Sc1 is.charged. turn-on. At 3the time, capacitance Mode (t2same –t3): At t2, the clampingCswitch SC1 is turned on with zero voltage. Because both the S1 is charged. Modeswitches 3 (t2 –t3 ):SC1 Atand t2, the clamping SC1 is turned on with zeroare voltage. Because Then both clamping SC2 are on, theswitch primary sides of the transformer short-circuited. the switches SC1 SC2 are on, theLprimary of the current transformer are short-circuited. the clamping power is transferred to and the input inductor 1, and thesides secondary is rises rapidly. Then Mode the power is 4transferred the input current inductorreaches L1 , andzero. the secondary current are is rises rapidly. 4 (t3–t ): At t3, the to secondary All four diodes reverse biased. Mode 4 (tthe –t ): At t the secondary current reaches zero. All four diodes are reverse biased. Additionally, secondary voltage recovers to zero within a short time. 3 4 3, Additionally, the recovers short Mode 5 (t 4–tsecondary 5): At t4, thevoltage clamping switchtoSzero C2 is within turned aoff. Thetime. leakage inductances Lk resonate 5 (t4capacitances –t5 ): At t4, the SC2 is turned The leakage inductances Lk resonate withMode parasitic ofclamping S2 and SC2switch . The voltage across Soff. 2 drops to zero at t5 so that ZVS turn-on with capacitances of S2 and SC2 . The voltage across S2 drops to zero at t5 so that ZVS turn-on of S2 parasitic is obtained. of S2 The is obtained. operation in intervals (t0–t5) and (t5–t10) is symmetrical. The power is transferred to the Theload operation intervals (t0 –t5and ) and (t5clamping –t10 ) is symmetrical. The is transferred the output R whenin one main switch one switch are on, andpower then the power flowstofrom output load when one main both switch and oneswitches clamping on, andcan then the power flows the input to R inductor L1 when clamping areswitch on. Allare switches obtain ZVS turn-on from the energy input to inductor bothbyclamping switches are on. All switches switches, can obtainwhich ZVS and the stored in LkL1iswhen recycled the parasitic capacitances of clamping turn-on andto the energyconversion stored in Lefficiency. is recycled by the parasitic capacitances of clamping switches, contributes a higher k whichThe contributes a higher conversion efficiency. voltage oftoclamp capacitor VCc can be obtained according to the flux balance of L1: The voltage of clamp capacitor VCc can be obtained according to the flux balance of L1 : V VCc = in (1) 1V −inD VCc = (1) 1 − D voltage of basic cell Vo,BC can be determined: Additionally, with the turns ratio as 1:1:n, the output Additionally, with the turns ratio as 1:1:n, the of basic cell Vo,BC can be determined: Vin n output n voltage Vo, BC = VCc = (2) 2n (1 −VD) n2 in Vo,BC = VCc = (2) 2 2 (1be − obtained D) The voltage stress of all four power switches Vds can by:

Vds = VCc =

Vin 1− D

(3)


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The voltage stress of all four power switches Vds can be obtained by: Sustainability 2018, 10, x FOR PEER REVIEW Vin Vds = VCc = 1−D

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2.2. Working Strategies of Matrix Configuration

2.2. Working Strategies of Matrix Configuration

A fundamental 2 × 2 modular topology is presented in Figure 4. The primary circuits of power A fundamental 2 × 2 modular topology is presented in Figure 4. The primary circuits of power cells are parallel connected so that they have an equal secondary voltage value with the same duty cells are parallel connected so that they have an equal secondary voltage value with the same duty cycle of main The secondary side ofofeach cellisisconnected connected four rectifier cycle switches. of main switches. The secondary side each cell withwith four rectifier diodes fordiodes for power regulation. power regulation. P_Cell_11

L1

Np1

P_Cell_22

Sc2

P_Cell_21

Sc1

Cc

D01 S_Cell_11 Ns

D10

D11

Np2 P_Cell_12

Vin

D00

S_Cell_21 D20

S1

D21

D02 S_Cell_12 D12 S_Cell_22

Cout

R

D22

S2

Figure 4.Figure 2 × 2 topology of theofisolated high gain DC/DC converter with basic cells. 4. 2 × 2 topology the isolated highvoltage voltage gain DC/DC converter with basic cells. As illustrated in Figure adjacent cellshave have opposite opposite polarities in column interleaved modes. modes. As illustrated in Figure 5a,b, 5a,b, adjacent cells polarities in column interleaved For example, the polarity of cell 11 is opposite to those of cell 21 and 12. In this case, cells in the same For example, the polarity of cell 11 is opposite to those of cell 21 and 12. In this case, cells in the same column are connected in series, and the adjacent columns are in parallel connection. The voltage column are connected in series, and the adjacent columns are in parallel connection. The voltage ratings of diodes in the first and last rows, D00 –D02 and D20 –D22 , are equal to the voltage of power ratings of diodes in thethe first and ratings last rows, D00diodes –D02 and D12 20–D 22,twice are equal to the ofare power cells cells vs . While voltage of other D10 –D have the value of vsvoltage since they connected two cells. The current stresses in the first lastof columns, –D20are andconnected vs. While the voltagewith ratings of other diodes D10–Dof12diodes have twice theand value vs sinceD00 they D –D have the same value as the secondary current of one column. Diodes D –D connect with 02 22 21 20 and D02–D22 have with two cells. The current stresses of diodes in the first and last columns,01D00–D two columns so that they have double the current stress of the others. Additionally, the sum of the the same value as the secondary current of one column. Diodes D01–D21 connect with two columns so average diode currents in all columns is equal to the output current. Therefore, in column interleaved that they have the and current stress ofofthe others. theassum of inthe average diode modes,double the voltage current ratings diodes in an Additionally, expanded topology shown Figure 6 of s rows and p columns be obtained: currents incomposed all columns is equal to the can output current. Therefore, in column interleaved modes, the  voltage and current ratings of diodes in an expanded topology as shown in Figure 6 composed of s n  1s Vo,s× p = Vo,BC = V i = 0, s 2(1− D ) in rows and p columns canVbe ( Dijobtained: )= (4) n 2 

s Vo,s× p

= 2 × Vo,BC =

V (1− D ) in

i = 1, 2, · · ·, (s − 1)

n 1 ( Vin0, p i = 0, s o, BC= =1 Io,s× p j =  s Vo, s p =12 IVo,BC 2p2(1 − D) ( Dij ) = I V ( Dij ) =  Io,BC = 1p Io,s× p 2 nj = 1, 2, · · ·, ( p − 1)  V = 2  Vpo, BC = Vin i = 1, 2, , ( s − 1)  s o, s p (1 − D ) I (D ) = I

∑

ij

o,sp

(5)

(4)

(6)

j =0

where Io,BC is the average output  1 current of1a single basic cell; Vo,s×p and Io,s×p are the output voltage = I o , s p j = 0, p  2 IIno, BC and current of s × p topology. this case, 2 p all semiconductor components have low voltage and  current ratings. I ( Dij ) = 

1 I I o , s p o, BC =  p

(5)

j = 1, 2, , ( p − 1)

p

 I (Dij ) = Io,sp j =0

(6)

p

 I (Dij ) = Io,sp

(6)

j =0

where Io,BC is the10, average output current of a single basic cell; Vo,s×p and Io,s×p are the output voltage6 and Sustainability 2018, 2176 of 15 current of s ×p topology. In this case, all semiconductor components have low voltage and current ratings. D00

D10

D01 + S_Cell_11 D11

+ S_Cell_12 D12

+ S_Cell_21

+ S_Cell_22

D20

D02

D21

D00

D01 + S_Cell_11

D10 Cout

D11

R

D22

D01 D01 + + S_Cell_11 S_Cell_11 D11 D11 + + S_Cell_21 S_Cell_21 D21 D21

D10 D10

D20 D20

D12

+ S_Cell_21 D20

+ S_Cell_22

D21

Sustainability 2018, 10, x FOR PEER REVIEW Sustainability 2018, 10, x FOR PEER (a) REVIEW D00 D00

D02 + S_Cell_12 Cout

R

D22

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(b)

D02 D02 + + S_Cell_12 S_Cell_12 D12 D12 + Cout + S_Cell_22 CoutR R S_Cell_22 D22 D22

D00 D00

D01 D01 + + S_Cell_11 S_Cell_11 D11 D11 + + S_Cell_21 S_Cell_21 D21 D21

D10 D10

D20 D20

(c) (c)

D02 D02 + + S_Cell_12 S_Cell_12 D12 D12 + Cout + CoutR S_Cell_22 R S_Cell_22 D22 D22

(d) (d)

Figure 5. 2 × 2 topology with different interleaved strategies: (a) Column interleaved mode 1; (b) Figure topologywith withdifferent differentinterleaved interleavedstrategies: strategies:(a)(a) Column interleaved mode 1; Figure5.5. 22 ××22topology Column interleaved mode 1; (b) Column interleaved mode 2; (c)2;Series interleaved mode 1; (d) Series interleaved mode 2. 2. (b) Column interleaved mode (c) Series interleaved mode 1; (d) Series interleaved mode Column interleaved mode 2; (c) Series interleaved mode 1; (d) Series interleaved mode 2. WTG 1 WTG 1

··

··

··

P_Cell1-sp P_Cell1-sp

··

P_Cell1-s2 P_Cell1-s2 P_Cell1-s1 P_Cell1-s1

··

··

P_Cell1-2p P_Cell1-2p

··

P_Cell1-22 P_Cell1-22 P_Cell1-21 P_Cell1-21 P_Cell1-1p P_Cell1-1p

P_Cell1-12 P_Cell1-12 P_Cell1-11 P_Cell1-11

WTG 2

··

WTG 2

··

··

··


··


··

··




WTG 3

··

··

WTG 3

··

··

··


··


··

··




··

··

(a) (a) Group 1 D1-00

D1-01

Group D1-02 1

D1-00 D1-01 D1-02 S_Cell1-11 S_Cell1-12

D1-10S_Cell D1-11 1-11

S_Cell D1-12 1-12

D1-10 D1-11 D1-12 S_Cell1-21 S_Cell1-22 1-21 D1-20S_Cell D1-21

D1-20

D1-21

S_Cell 1-22 D1-22 D1-22

Group 2 D1-0p D1-0p S_Cell1-1p S_Cell D1-1p 1-1p

D1-1p S_Cell1-2p S_Cell 1-2p D1-2p D1-2p

D2-00

D2-01

Group 3

Group D2-02 2

D2-00 D2-01 D2-02 S_Cell2-11 S_Cell2-12

D2-10S_Cell D2-11 2-11

D2-20

D2-21

D2-0p S_Cell2-1p

S_Cell D2-12 2-12

S_Cell D2-1p 2-1p


D2-0p

D2-1p S_Cell2-2p

S_Cell 2-22 D2-22

S_Cell 2-2p D2-2p

D2-22

D2-2p

D3-00

D3-01

Group D3-02 3

D3-00 D3-01 D3-02 S_Cell3-11 S_Cell3-12 D3-10S_Cell D3-11 3-11

S_Cell D3-12 3-12


D3-20

D3-21

S_Cell 3-22 D3-22 D3-22

D3-0p D3-0p S_Cell3-1p

Iout Iout

S_Cell D3-1p 3-1p D3-1p S_Cell3-2p

S_Cell 3-2p D3-2p D3-2p

Cout Cout

S_Cell1-s1 1-s1 D1-s0S_Cell D1-s1

D1-s0

D1-s1

S_Cell1-s2 S_Cell 1-s2 D1-s2 D1-s2

S_Cell1-sp S_Cell 1-sp D1-sp D1-sp


D2-s0

D2-s1

S_Cell2-s2

S_Cell2-sp

S_Cell 2-s2 D2-s2

S_Cell 2-sp D2-sp

D2-s2

D2-sp


D3-s0

D3-s1

S_Cell3-s2 S_Cell 3-s2 D3-s2 D3-s2

Vout Vout

S_Cell3-sp S_Cell 3-sp D3-sp D3-sp

(b) (b) Figure 6. Topology of the proposed converter with three input-ports: (a) primary circuits with three Figure 6. Topology of the proposed converter with three input-ports: (a) primary circuits with three power (b) secondary circuitsconverter collectingwith power andinput-ports: delivering it(a)toprimary load. circuits with three Figuresources; 6. Topology of the proposed three power sources; (b) secondary circuits collecting power and delivering it to load. power sources; (b) secondary circuits collecting power and delivering it to load.

From Figure 5c,d, in series interleaved modes, all cells are series-connected. The cells in adjacent From Figure 5c,d, in series interleaved modes, all cells are series-connected. The cells in adjacent rows have the opposite polarities while the cells in the same row have the same polarity. Similar to rows have the opposite polarities while the cells in the same row have the same polarity. Similar to Equation (4), diodes D10 and D12 have twice the voltage rating higher than that of diodes in the first Equation (4), diodes D10 and D12 have twice the voltage rating higher than that of diodes in the first and last rows because they connect with two rows. The currents of all operating diodes have the same and last rows because they connect with two rows. The currents of all operating diodes have the same value since they are in series-connection. Hence, the voltage and current ratings of diodes in series value since they are in series-connection. Hence, the voltage and current ratings of diodes in series interleaved modes can be calculated as: interleaved modes can be calculated as: pn 1 i = 0, s p  n Vin  1Vo, s p = p  Vo, BC =


7 of 15

From Figure 5c,d, in series interleaved modes, all cells are series-connected. The cells in adjacent rows have the opposite polarities while the cells in the same row have the same polarity. Similar to Equation (4), diodes D10 and D12 have twice the voltage rating higher than that of diodes in the first and last rows because they connect with two rows. The currents of all operating diodes have the same value since they are in series-connection. Hence, the voltage and current ratings of diodes in series interleaved modes can be calculated as:   1s Vo,s× p = p × Vo,BC = p×n Vin i = 0, s 2(1− D ) (7) V ( Dij ) =  2 Vo,s× p = 2p × Vo,BC = p×n Vin i = 1, 2, · · ·, (s − 1) s (1− D ) I ( Dij ) =

1 1 I = Io,s× p 2 o,BC 2

j = 0, p

(8)

According to Equation (8), for series interleaved modes, the current rating of diodes is increased with the increase of output power. Besides which, the diodes D01 –D21 are blocked, which benefits the fault tolerance operation to be described in Section 4. 3. Analysis of the Proposed Converter with Multi-Input Ports 3.1. Scalable Topology Thanks to modularity, multi-module converters can be easily expanded by increasing its row number and column number to attain a high voltage gain and the desired high power level. In the normal scenario, the proposed converter operates with column interleaved modes to keep a low voltage/current rating of components. Three wind-turbine-generators, WTGs 1–3, are connected to the proposed converter as illustrated in Figure 6a. Figure 6b shows the secondary circuits that are divided into three independent, Groups 1–3, by diodes D1-0p –D1-sp , D2-00 –D1-s0 and D2-0p –D2-sp , D3-00 –D3-s0 on the basis of input ports. The output power of each group consisting of the s × p expanded topology can be controlled individually, and the bus cable is eliminated. With the same input voltage and power of each port, the voltages and currents of all basic cells are identical. The cells in the same column are in series-connection. Hence, every column has the same terminal voltage which is the sum of the voltages of cells in the same column. For a converter with multi-ports, output voltage Vout equals to the identical terminal voltage of columns and the output current Iout is the sum of secondary currents of all columns. Therefore, the row number s determines the output voltage, and the group number x with column number p determines the output power. (

Vout = Vo,s× p = s × Vo,BC =

s×n V 2(1− D ) in

Iout = x × Io,s× p = x × p × Io,BC

(9)

3.2. Current Balance with Column Interleaved Mode The control complexity is reduced by the auto-balanced currents of cells in the same column. According to the currents through diodes D10 –D13 and D20 –D23, as shown in Figure 7, the relationships among all cells can be obtained as:  Io,BC11+ + Io,BC12+ = Io,BC21+ + Io,BC22+     Io,BC31+ = Io,BC21+  Io,BC23+ = Io,BC13+    Io,BC32+ + Io,BC33+ = Io,BC22+ + Io,BC23+

(10)


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 Io,BC11−     I + Io,BC32− o,BC31−   Io,BC12− + Io,BC13−   Io,BC33−

= = = =

Io,BC21− Io,BC21− + Io,BC22− Io,BC22− + Io,BC23− Io,BC23−

(11)

where Io,BC+ is the average current of secondary circuit in the interval (t0 –t5 ) and Io,BC − is that in the interval (t5 –t10 ). According to the symmetrical operation of the basic cell between the two intervals, it can be derived that Io,BC+ = Io,BC − . Therefore, Equation (12) is obtained with Io,BC = Io,BC+ + Io,BC − .    Io,BC11 = Io,BC21 = Io,BC31 Io,BC12 = Io,BC22 = Io,BC32 Sustainability 2018, 10, x FOR PEER REVIEW Sustainability 2018, 10, x FOR PEER REVIEW I o,BC13 = Io,BC23 = Io,BC33

(12)

8 of 15 8 of 15

According to Equation (12), the average currents for cells in the same column are auto-balanced. According to Equation (12), the average currents for cells in the the same same column column are are auto-balanced. auto-balanced. Therefore, as shown in Figure 8, only the control of output voltage and current sharing in different output voltage and current sharing in different Therefore, as shown in Figure 8, only the control of output columns is employed to achieve the required output voltage and power in the s × p topology, where thethe required output voltage andand power in theins the × p topology, where columns is is employed employedtotoachieve achieve required output voltage power s × p topology, vo,ref is the desired output voltage and iL,i1–iL,ip are the currents collected from columns 1–p. v o,ref is the desired output voltage and i L,i1 –i L,ip are the currents collected from columns 1–p. where vo,ref is the desired output voltage and iL,i1 –iL,ip are the currents collected from columns 1–p. D00 D00

D10 D10

D20 D20

D30 D30

D01 D01 + + S_Cell11S_Cell11 D11 D + 11 + S_Cell 21 S_Cell21 D21 D21 + + S_Cell31S_Cell31 D31 D31

D02 D02 + + S_Cell12 S_Cell12 D12 D12 + + S_Cell 22 S_Cell22 D22 D22 + + S_Cell32 S_Cell32 D32 D32

D03 D03 + + S_Cell13S_Cell13 D13 D + 13 + S_Cell 23 S_Cell23 D23 D23 + + S_Cell33S_Cell33 D33 D33

D00 D00

D01 D01 + + S_Cell11 S_Cell11 D11 D11 + + S_Cell21S_Cell21 D21 D21 + + S_Cell31 S_Cell31 D31 D31

D10 D10 Cout Cout

Vout Vout

D20 D20

D30 D30

D02 D02 + + S_Cell12S_Cell12 D12 D + 12 + S_Cell22 S_Cell22 D22 D22 + + S_Cell32S_Cell32 D32 D32

(a) (a)

D03 D03 + + S_Cell13 S_Cell13 D13 D13 + + S_Cell23S_Cell23 D23 D23 + + S_Cell33 S_Cell33 D33 D33

Cout Cout

Vout Vout

(b) (b)

Figure 7. Auto-balanced currents of cells in the same column with column interleaved working Auto-balancedcurrents currents of cells in same the same column with column interleaved Figure 7.7.Auto-balanced of cells in the column with column interleaved working working strategy: strategy: (a) Column interleaved working mode 1; (b) Column interleaved working mode 2. strategy: (a)interleaved Column interleaved working mode 1; (b)interleaved Column interleaved working (a) Column working mode 1; (b) Column working mode 2. mode 2.

+ +

Vo,ref Vo,ref

+ +

PI PI Vout Vout

-

s s I

-

s s I

-

s s I

+ +

PI PI

Column Column 1 1

PI PI

2 2

PI PI

p p



IL,i1 i=1 L,i1 i=1



IL,i2 i=1 L,i2 i=1

+ +



IL,ip i=1 L,ip i=1

Figure 8. Control scheme of the s × p topology. Figure 8. 8. Control Control scheme scheme of of the the ss × × pp topology. Figure topology.

4. Fault Tolerance 4. Fault 4. Fault Tolerance Tolerance 4.1. Fault Tolerance for WTGs with Different Output Power for WTGs WTGs with with Different Different Output Output Power Power 4.1. Fault Tolerance Tolerance for When disturbances occur, proper control strategies of WTGs and converters should be applied disturbances occur, occur,proper propercontrol controlstrategies strategiesofofWTGs WTGsand and converters should applied When disturbances converters should bebe applied to to ensure system protection and high power efficiency [28,29]. For the proposed converter, the output to ensure system protection and highpower powerefficiency efficiency[28,29]. [28,29].For Forthe theproposed proposedconverter, converter, the the output ensure system protection and high power of one group is determined not only by the column number of the secondary circuits but also, power of one group is determined not only by the column number of the secondary circuits but also, by the duty-cycles of main switches. According to Equation (8), the output power of one group is by the duty-cycles of main switches. According to Equation (8), the output power of one group is obtained as: obtained as: Pgroup = ( p − m) Vout  Io, BC (13) Pgroup = ( p − m) Vout  Io, BC (13) where m is the number of idle column in the corresponding group. where m is the number of idle column in the corresponding group.


9 of 15

by the duty-cycles of main switches. According to Equation (8), the output power of one group is obtained as: Pgroup = ( p − m) × Vout × Io,BC (13) where m is the number of idle column in the corresponding group. The variation of a duty-cycle will cause the change of currents through the cells in one column as: Isub = Io,BC

2 = · Ts

Z ton 0

iout ≈ imax · D

(14)

Hence the output power is: Pgroup = p · Vout · Isub = p · D · Vout · imax

(15)

where imax is the maximum output current of power cells. 4.2. Fault Tolerance for Semiconductor Components Semiconductor components are Sustainability 2018, 10, x FOR PEER REVIEW

vulnerable components in a converter [30]. For offshore HVDC 9 of 15 stations, faulty components take a long time for maintenance, resulting in high cost and loss [31]. 4.2. Fault Tolerance for Semiconductor Components Figure 9 shows the fault tolerance operation derived by installing redundant power cells. To maintain normal operation, the column in a red dotted box containing the damaged Cell 11 Semiconductor components are vulnerable components in a converter [30]. For offshore HVDC is replaced by one redundant column that is in the other red dotted box. For the faulty diodes D00 –Ds0 , stations, faulty components take a long time for maintenance, resulting in high cost and loss [31]. they require only one redundant column since they connect with one column. However, for other Figure 9 shows the fault tolerance operation derived by installing redundant power cells. To diodes, two redundant columns are demanded. For example, when diode D fails, the columns 1–2 in maintain normal operation, the column in a red dotted box containing11the damaged Cell 11 is the blue dotted box are idle, and the redundant columns p1–p2 are applied. replaced by one redundant column that is in the other red dotted box. For the faulty diodes D00–Ds0, they require only one redundant column sinceVthey connect with one column. However, for other 1 o,s× p Vo,FBC = For example, = Vo,BCwhen diode D11 fails, the columns (16) diodes, two redundant columns are demanded. 1–2 2×s 2 in the blue dotted box are idle, and the redundant columns p1–p2 are applied. Failed cell

D00

D01

D02

Cell_11 D10

Cell_12

D11

D12

Cell_21

D20

Cell_22

D21

D22

Cell_31 D30

Cell_32

D31

D32

Failed diode

D03

D0p

Cell_13 D13

D1p

Cell_23

D23

D1p1 Cell_2p1

D2p

Cell_33 D33

D0p1

Cell_1p1

D2p1 Cell_3p1

D3p

D3p1

D0p2

Cell_1p2 D1p2 Cell_2p2

D2p2 Cell_3p2 D3p2 Cout

Cell_s1 Ds0

Cell_s2

Ds1

Ds2

Idle Cells

Cell_s3 Ds3

Cell_sp1 Dsp

Dsp1

Vout

Cell_sp2 Dsp2

Redundant Cells

Figure Figure 9. Fault Fault tolerance tolerance with with redundancy. redundancy.

The proposed topology can also obtain fault Vo, stolerant 1 operation of diodes and power switches p = is Vo, BC (16) o, FBC = without redundancy. In Figure 10a,b, Vwhen diode D 2  s 112 short-circuited, the cells in rows 1–2 are inactive to block the faulty components, while the fault tolerance group still operates with the column The proposed topology can also fault tolerant operation diodesvoltages and power switches interleaved strategy. Additionally, to obtain maintain normal operation, theofoutput of the faulty without redundancy. In Figure 10a,b, when diode D 11 is short-circuited, the cells in rows 1–2 are group are controlled according to Equations (2) and (9) to ensure the output voltage is the same as that inactive to block theWhen faultydiode components, while the faultas tolerance group still operates with the tolerant column in the normal case. D11 is open-circuited illustrated in Figure 10c,d, the fault interleaved strategy. Additionally, to maintain normal operation, the output voltages of the faulty operation group consisting of two columns works under the series interleaved modes to block D11 . group are controlled according to Equations (2) and (9) to ensure the output voltage is the same as Compared with the normal operation group, the number of cells in series connection in the faulty that in the normal case. When diode D11 is open-circuited as illustrated in Figure 10c,d, the fault tolerant operation group consisting of two columns works under the series interleaved modes to block D11. Compared with the normal operation group, the number of cells in series connection in the faulty group is doubled. The voltages of cells in the fault group are adjusted as illustrated in Equation (15) to ensure they have the same terminal voltage. Moreover, the fault tolerant operation of damaged cells without redundancy is similar to that

inactive to block the faulty components, while the fault tolerance group still operates with the column interleaved strategy. Additionally, to maintain normal operation, the output voltages of the faulty group are controlled according to Equations (2) and (9) to ensure the output voltage is the same as that in the normal case. When diode D11 is open-circuited as illustrated in Figure 10c,d, the fault tolerant operation group consisting of two columns works under the series interleaved modes Sustainability 2018, 10, 2176 10 ofto 15 block D11. Compared with the normal operation group, the number of cells in series connection in the faulty group is doubled. The voltages of cells in the fault group are adjusted as illustrated in Equation group is doubled. voltages of terminal cells in the fault group are adjusted as illustrated in Equation (15) to (15) to ensure theyThe have the same voltage. ensure they have the same terminal voltage. Moreover, the fault tolerant operation of damaged cells without redundancy is similar to that fault tolerantFor operation ofwhen damaged cells without redundancy similar to that that whenMoreover, diodes arethe short-circuited. instance, cell 11 fails, cells 11-1p and 21-2pisare idle so when diodes are short-circuited. For instance, when cell 11 fails, cells 11-1p and 21-2p are idle so that the faulty one is blocked. the faulty one is blocked. D00

D01 Cell_11

D10

D11 Cell_21

D20

D21 Cell_31

D30

D31

D02

D00

D0p Cell_1p

Cell_12

D12

D10

D1p Cell_2p

Cell_22 D22

D20

D2p

D32

D02

D11

D12

Vout

D30

D1p

Cell_2p

Cell_22

D21

D22

Cell_31

D3p

D0p Cell_1p

Cell_12

Cell_21

Cell_3p

Cell_32

D01 Cell_11

D2p

Cell_32

D31

Cell_3p D3p

D32

Cell_s1 Ds0

Ds1

Cell_s2

Cell_s1

Cell_sp

Ds2

Ds0

Dsp

Cell_s2

Ds1

Fault tolerance operation group

D01

D10

D11 Cell_21

D20

D21 Cell_31

D30

D31

D02

D0p

D12

D00

D1p

D22

D10

D2p

D20

D32

Vout

D30

D0p

Cell_1p

D12

D1p Cell_2p

Cell_22

D21 Cell_31

D3p

D02 Cell_12

D11 Cell_21

Cell_3p

Cell_32

D01 Cell_11

Cell_2p

Cell_22

10 of 15

(b)

Cell_1p

Cell_12

Dsp


(a)

Cell_11

Cell_sp

Ds2

Sustainability 2018, 10, x FOR PEER REVIEW D00

D22

D2p Cell_3p

Cell_32

D31

D32

D3p

Cout

Cell_s1 Ds0

Ds1

Cell_s2

Cell_s1

Dsp


Ds0

Normal operation group

Vout Cout

Cell_sp

Ds2

Vout

Cout

Cout

Cell_s2

Ds1

Cell_sp1

Ds2

Dsp


(c)

Normal operation group

(d)

Figure 10. Fault tolerance without redundancy: (a) Working mode 1 under diode short-circuit; (b) Figure 10. Fault tolerance without redundancy: (a) Working mode 1 under diode short-circuit; Working mode 2 under diode short-circuit; (c) Working mode 1 under diode open-circuit; (d) (b) Working mode 2 under diode short-circuit; (c) Working mode 1 under diode open-circuit; Working mode 2 under diode open-circuit. (d) Working mode 2 under diode open-circuit.

5. Simulation Results and Discussion 5. Simulation Results and Discussion To illustrate the functionality of the proposed power converter, a simulation model consisting To illustrate the functionality of the proposed power converter, a simulation model consisting of 3 groups × 4 rows × 5 columns with 2 redundant columns is built by software PSIM, which is of 3 groups × 4 rows × 5 columns with 2 redundant columns is built by software PSIM, which is similar to the model shown in Figure 6. The cells in columns 1-3 are active, while those in columns 4similar to the model shown in Figure 6. The cells in columns 1–3 are active, while those in columns 5 are inactive. 4–5 are inactive. For Figure 12, every group has different numbers of rows. Only one row operates in Group 1; in Table 1 presents the initial values for the simulation. It is noted that to verify the auto-balanced Group 2, there are two rows; Group 3 has four rows. The duty-cycle D of cells in each group is current characteristic, the leakage inductances of cells in column 1 are set as 70, 75, 80, 85 µH. regulated to obtain the same terminal voltage, and the voltages of cells are shown in Figure 12 as: Vs_cell 1–11 = 2 × Vs_cell 2–11 = 4 × Vs_cell 3–11Table = Vout.1. Initial values of simulation. The peak current values of different columns are almost equal so that the duty-cycle power transmission control (15) is verified. System presented Parameters in Equation Values Components Values Figure 13 shows the voltages of diodes in Group 1–2. The voltage of diodes in Group 3 has the Input Voltage 650 V Turns ratio 1:1:n 1:1:2 same waveforms as those presented in Figure 10. It can be found that the voltage Output Voltage 6400 V Leakage inductance 80value µH is increased Switching Frequency Input inductance 5 mH as the number of idle rows increases. 5 kHz Output Power14, before turning 40 kW on switches Clamp 20 µF current flows As illustrated in Figure S1 orcapacitor SC1, the drain-to-source through the parasitic diode of the switch to achieve ZVS operation. Similarly, the switches S2 and SC2 can also soft-switching. Therefore, the switching losssame is significantly reduced. Theobtain steady-state waveforms of the converter with the input power from WTGs are shown Table11. 1 presents thework initialunder values the simulation. It is noted that the auto-balanced in Figure All groups thefor column interleaved strategy, and to theverify voltages of the adjacent current characteristic, the leakage inductances of cells in column 1 are set as 70, 75, 80, 85 μH. Table 1. Initial values of simulation.

System Parameters Input Voltage

Values 650 V

Components Turns ratio 1:1:n

Values 1:1:2


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cells in the same column have opposite polarities. Meanwhile, the currents of cells with diverse leakage inductances in column 1 are almost equal. The voltage stress of power switches is 1/4 of the output voltage, and all diodes have the voltage and current stresses as low as 1/4 or 1/2 of the output voltage and current, respectively. Sustainability 2018, 10,12, x FOR PEER REVIEW 11 of 151; For Figure every group has different numbers of rows. Only one row operates in Group Sustainability 2018, 10, x FOR PEER REVIEW 11 of 15 in Group 2, there are two rows; Group 3 has four rows. The duty-cycle D of cells in each group is The peak current of different columns equal so that the duty-cycle regulated to obtain thevalues same terminal voltage, andare thealmost voltages of cells are shown in Figurepower 12 as: The peak current values of different columns are almost equal so that the duty-cycle power transmission control presented in Equation (15) is verified. Vs_cell 1–11 = 2 control × Vs_cellpresented Voutis. verified. transmission 2–11 = 4 ×inVEquation s_cell 3–11 =(15) Figure 13 shows thevalues voltages of diodescolumns in Group 1–2. The voltage of that diodes Group 3 has the The peak current of different almost equal so thein power Figure 13 shows the voltages of diodes in Groupare 1–2. The voltage of diodes induty-cycle Group 3 has the same waveforms as those presented in Figure 10. It can be found that the voltage value is increased transmission control presented in Equation (15) is verified. same waveforms as those presented in Figure 10. It can be found that the voltage value is increased as theFigure number idle rows increases. 13of shows the voltages of diodes in Group 1–2. The voltage of diodes in Group 3 has the as the number of idle rows increases. As illustrated in Figure 14, before on switches S1 or SC1 , the drain-to-source current flows sameAs waveforms presented inturning Figure 10. can be found the voltage value is increased as illustratedasinthose Figure 14, before turning on Itswitches S1 or Sthat C1, the drain-to-source current flows through the parasitic diode of the switch to achieve ZVS operation. Similarly, the switches S 2 and SC2 the number of idle rows increases. through the parasitic diode of the switch to achieve ZVS operation. Similarly, the switches S2 and SC2 can also obtain soft-switching. Therefore, the switching loss is significantly reduced. can also obtain soft-switching. Therefore, the switching loss is significantly reduced. 6.8K 6.8K 6.4K 6.4K 6K 6K 2K 2K 1K 1K 0 0 -1K -1K -2K -2K 2 2

Vout (V) Vout (V)

4K 4K 2K 2K 0 0

vs_cell 11,31 (v) vs_cell 11,31 (v)

vs_cell 21 (v) vs_cell 21 (v)

is_cell 11,31 (A) is_cell 11,31 (A)

is_cell 21 (A) is_cell 21 (A)

0 0 -2 -2 0.2288 0.2288

0.229 0.229 Time (s) Time (s)

0.2292 0.2292

vD10, 30 (V) vD20 (V) vD10, 30 (V) vD20 (V)

vD00, 40 (V) vD00, 40 (V) 2000 2000 1000 1000 0 0 iD00 (A) iD00 (A) 2 2 1 1 0 0 iD01 (A) iD01 (A) 4 4 2 2 0 00.2288 0.2288

(a) (a)

iD03 (A) iD03 (A)

iD02 (A) iD02 (A)

0.229 0.229 Time (s) Time (s)

0.2292 0.2292

(b) (b)

Figure 11. Steady-state waveforms for cells and diode: (a) voltage/current of basic cells; (b) Steady-statewaveforms waveformsforforcells cellsand and diode: voltage/current of basic Figure 11. Steady-state diode: (a) (a) voltage/current of basic cells;cells; (b) voltage/current of diodes. (b) voltage/current of diodes. voltage/current of diodes. 6.8K 6.8K 6.4K 6.4K 6K 6K 10K 5K 10K 0 5K -5K 0 -10K -5K -10K 4K 2K 4K 0 2K -2K 0 -4K -2K -4K 2K 1K 2K 0 1K -1K 0 -2K -1K -2K 4 24 02 -20 -4 -2 -4

Vout (V) Vout (V)

vS_Cell 1-11 (V) vS_Cell 1-11 (V)



iS_Cell 1-11 (A) iS_Cell 2-11 (A) iS_Cell 3-11 (A) iS_Cell 1-11 (A) iS_Cell 2-11 (A) iS_Cell 3-11 (A)

0.3925 0.3925

0.3926 0.3926 Time (s) Time (s)

0.3927 0.3927

0.3928 0.3928

Figure 12. Waveforms of cells when Groups 1–3 have different output power. Figure Figure 12. 12. Waveforms Waveforms of of cells cells when when Groups Groups 1–3 1–3 have have different different output output power. power.


12 of 15


8K

12 of 15

vD1-00 (V)


12 of 15

4K

8K

0 vD1-00 (V) vD1-10,20,30,40 (V)

4K1500 1000

0 500 0

vD1-10,20,30,40 (V) 0.3925

1500 1000 500 0 3000

2000 1000 0

0.3926

Time (s)

0.3927

0.3928

(a) vD2-00 (V)

0.3925

0.3926

Time (s)

0.3927

0.3928

(a)

vD2-10 (V) 8K 4KvD2-00 (V) 3000 0

2000 vD2-20,30,40 (V) 1000 01500 1000 500vD2-10 (V) 0 8K 0.392 5 4K 0

0.392 6

0.392 7

Time (s)

0.392 8

(b)

vD2-20,30,40 (V)

1500 of diodes in each Group when Groups 1–3 have different output power: (a) Figure 13. Voltages Figure 13. Voltages 1000 of diodes in each Group when Groups 1–3 have different output power: (a) Voltages 500in Voltages of diodes 0 Group 1; (b) Voltages of diodes in Group 2.

of diodes in Group 1; (b) Voltages of diodes in Group 2. 0.392 5

0.392 6

0.392 7

Time (s)

Vg1 (V)

Vgc1 (V)

Vg2 (V)

Vgc2 (V)

Vg1 (V)

Vgc1 (V)

0.392 8

ZVS

(b) 0 As illustrated in Figure 14, before turning on switches S1 or SC1 , the drain-to-source current flows through the13. parasitic diode of thein switch to achieve ZVS operation. Similarly, the switches S2 and Figure Voltages of diodes each Group when Groups 1–3 have different output power: (a) SC2 Voltages of diodes in Group 1; diodes in Group 0 (b) Voltages can also obtain soft-switching. Therefore, theofswitching loss is2.significantly reduced. 2K 1K 00

ids1 (A)

02 0 -2 2K

Vg2 (V)

ZVS

idsc1 (A)

Vgc2 (V)

1K 0.2288 0

0.229 Time (s)

0.2292

Figure 14. Zero voltagei switching (A) i (ZVS) (A)of main switches and clamping switches. ds1

dsc1

2 Figure 15a shows the fault tolerance operation with redundancy. At 0.07 s, fault cells 1–2 are 0 idle, and the redundant columns 4–5 start to work to guarantee normal operation. Figure 15b,c presents the fault tolerance -2 without redundancy, where only columns 1–3 are active. In Figure 15b, 0.2288 0.229 0.2292 when the diode D11 is short-circuited, the cells in Time rows(s) 1–2 are blocked. The voltages of cells in row 3–4 are doubled to achieve the same terminal voltage. The diode D11 is open in Figure 15c. The faulty group consisting of columns 1–2 works in the series interleaved mode changing the polarities of Zero voltage voltage Figure 14. Zero switching (ZVS) of main switches andby clamping switches. cells. Moreover, the voltages of cells in the faulty group are reduced to half of that in the normal operation group to obtain the same outputoperation voltage. with redundancy. At 0.07 s, fault cells 1–2 are Figure 15a shows thefault fault tolerance Figure 15a shows the tolerance operation with redundancy. At 0.07 s, fault cells 1–2 are idle,

idle, andredundant the redundant columns start to to guarantee work to guarantee normal Figure operation. 15b,c and the columns 4–5 start4–5 to work normal operation. 15b,cFigure presents the presents the fault tolerance without redundancy, where only columns 1–3 are active. In Figure 15b, fault tolerance without redundancy, where only columns 1–3 are active. In Figure 15b, when the diode when diode D11 isthe short-circuited, the are cellsblocked. in rowsThe 1–2voltages are blocked. Theinvoltages in row D11 is the short-circuited, cells in rows 1–2 of cells row 3–4 of arecells doubled to 3–4 are doubled to achieve the same terminal voltage. The diode D 11 is open in Figure 15c. The faulty achieve the same terminal voltage. The diode D11 is open in Figure 15c. The faulty group consisting group consisting of columns works in the series mode changing the polarities of of columns 1–2 works in the 1–2 series interleaved modeinterleaved by changing the by polarities of cells. Moreover, cells. Moreover, the voltages of cells in the faulty group are reduced to half of that in the normal the voltages of cells in the faulty group are reduced to half of that in the normal operation group to operation to obtain the same output voltage. obtain the group same output voltage.


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8K 4K 0K

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Vout (V)

Vout (V) 8K 4K

VS_cell_idle (V)

0

2K 0K -2K 2K 0K -2K 2K 0K -2K

VS_cell row 1~2 (V) 2K

0

VS_cell_redundancy (V)

-2K VS_cell fault_opration (V) 4K

VS_cell_normal (V)

0 -4K

0.06

0.07

0.08 Time (s)

(a)

0.1

0.06

0.07

0.08 Time (s)

0.1

(b)

Sustainability 2018, x FOR PEER REVIEW Sustainability 2018, x FOR PEER REVIEW Sustainability 2018, 10,10, x FOR PEER REVIEW Sustainability 2018, 10, 10, x FOR PEER REVIEW 1313 of of 1515 Vout (V) 10000 60002018,V10, Sustainability x (V) FOR PEER REVIEW Vout (V) VoutV(V) out (V) out 2000 10000 10000 10000 10000 iD11 (A) 6000 6000 6000 6000 Vout (V) 2000 2000 2000 8 2000 10000 4 iD11iD11 (A)(A) iD11i(A) D11 (A) 0 6000 V (V) 8 11 8 S_Cell 8 8 2000 4 4 4 2000 4 iD11 (A) 0 0 0 0 0 VS_Cell VS_Cell VS_Cell VS_Cell 11 (V) 11 (V) 11 (V) 11 (V) -2000 8 4 2000 2000 2000 2000 VS_Cell 12 (V) 0 0 0 0 0 2000 VS_Cell 11 (V) -2000 -2000 -2000 0-2000 VS_Cell VS_Cell VS_Cell VS_Cell -2000 2000 12 (V) 12 (V) 12 (V) 12 (V) 0 2000 2000 VS_Cell 13 (V) 2000 2000 -2000 0 0 0 0 2000 VS_Cell 12 (V) -2000 -2000 -2000 -2000 0 2000 VS_Cell VS_Cell VS_Cell VS_Cell 13 (V) 13 (V) 13 (V) 13 (V) -2000 0.06 0.1 0.07 0 0.08 2000 2000 2000 2000 -2000 Time (s) 0 0 0 0 VS_Cell 13 (V) -2000 -2000 -2000 -2000 (c) 0.06 0.07 0.08 0.07 0.08 0.06 0.10.1 0.060.06 0.070.07 0.080.08 2000 Time Time Time Time (s) (s) 0 (s)(s) Figure 15. Fault tolerance operation: (a) With redundancy; (b) Without redundancy for D11 short-2000 Figure 15. Fault tolerance operation: (a) With redundancy; for D11 short-circuit; 0.06 redundancy 0.08 0.1 (c)(c) 0.07 (c)(c) (b) Without circuit; (c) Without redundancy for D11 open-circuit. Time (s)

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0.1 0.1

(c) Without redundancy for D11 open-circuit. Figure15.15.Fault Faulttolerance toleranceoperation: operation:(a)(a)With Withredundancy; redundancy; Figure Fault (b) Without tolerance redundancy operation: (a) for D11shortshortredundancy; Without Figure Figure 15.15. Fault (b) tolerance Without operation: (a) for With DWith 11 redundancy; (b)(b) Without redr (c) redundancy Where N is the number of SMs or power cells; n is the turns ratio of transformers. Table 2 shows circuit; Without redundancy Dopen-circuit. 11 open-circuit. circuit; Without redundancy 11 open-circuit. circuit; (c)(c) Without redundancy forfor D11 circuit; (c) (c) Without redundancy forfor D11Dopen-circuit. Where N is comparison the number of SMs or power cells; operation: nDue is the ratioredundancy; of transformers. Table have 2 shows a performance among several literatures. to turns hard switching, References [21,23] Figure 15. Fault tolerance (a) With (b) Without redundancy for D11 shorthigherWhere switching losses. Multi-module converters can achieve a higher voltage step-up ratio by circuit; (c) Without redundancy for D 11 open-circuit. a performance comparison among several literatures. Due to hard switching, References [21,23] Where the number SMs power cells; Where the Nturns isturns the number ratio transformers. of SMs power Table cells; 2 shows is the turns ratio of NN is is the number ofof SMs oror power cells; Where nn is is N the is the number ratio ofof transformers. SMs or or power Table cells; 2 shows n isn the turns ratio of tra

increasing the power cells number and the voltage gain of power cells. For MMCs, fault tolerance ishave have switching losses. Multi-module converters can achieve a switching, higher voltage step-up ratio by ahigher performance comparison among several a performance Due comparison hard among References several literatures. [21,23] have Due to hard switch a performance comparison among several literatures. a literatures. performance Due comparison toto hard switching, among References several literatures. [21,23] Due to hard switchin Where N is the number of SMs or power cells; n is the turns ratio of transformers. Table sho achieved by redundancy. However, the proposed converter has an improved fault tolerance increasing the powerlosses. cells number and theconverters voltage gain of achieve power cells. For MMCs, fault tolerance isby higherswitching switching losses. Multi-module converters higher switching can achieve losses. higher Multi-module voltage step-up converters ratio can achieve a 2high higher Multi-module higher switching can losses. a ahigher Multi-module voltage step-up converters ratio canby achieve a higher capability can maintain normal operation without redundancy. Therefore, to the same a performance comparison among several literatures. Due toachieve hard switching, References [21,23] haF achieved bywhich redundancy. However, the proposed converter an improved fault tolerance capability increasing the power cells number and the voltage increasing gain the of power power cells cells. number For MMCs, and the fault voltage tolerance gain power cells. increasing the power cells number and the increasing voltage gain the ofhas power power cells cells. number For MMCs, and the fault voltage tolerance gain isofisof power cells. For performance, a multi-module converter with CFPP cells requires fewer components. higher switching losses. Multi-module converters can achieve a higher voltage step-up ratio which can maintain normal operation without redundancy. Therefore, to achieve the same performance, achieved redundancy. However, the achieved proposed by converter redundancy. has anHowever, improved fault proposed tolerance converter achieved bybyredundancy. However, the achieved proposed byconverter redundancy. has an However, improved thethe fault proposed tolerance converter hashas an an i increasing the power cells number and the voltage gain of power cells. without For MMCs, fault tolerance a multi-module converter with CFPP cells requires fewer components. capability which can maintain normal operation capability without which redundancy. maintain Therefore, normal to operation achieve the without same redundancy. Th capability which can maintain normal operation capability without which redundancy. cancan maintain Therefore, normal to operation achieve the same redundancy. Ther Table 2. Performance comparison. achieved converter byconverter redundancy. However, the proposed converter has an improved fault toleran performance, a multi-module with performance, CFPP cells a multi-module fewer components. converter with CFPP cells requires fewer c performance, a multi-module with performance, CFPP cells requires a requires multi-module fewer components. converter with CFPP cells requires fewer com capability which maintain normal operation without redundancy. Therefore, to achieve the sam MMCs Multi-Module Converters Tablecan 2. Performance comparison. HB/FB [21,32] Resonant [20]converter Flyback–Forward CFPP Converter performance, aTable multi-module with CFPP[23] cells requires fewer components. Table 2. Performance comparison. Table 2. Performance comparison. 2.MMC Performance comparison. Table 2. Performance comparison.

 Multi-Module Converters ✓ MMCs ✓ MMCs Multi-Module MMCs Converters Multi-M MMCs Multi-Module MMCs Converters Multi-Mod 1 1 Converter Table 2. Performance comparison. HB/FB [21,32] Resonant MMC [20] Flyback–Forward [23] CFPP  N , n  N Conversion ratio  N , , n  N , , n HB/FB [21,32] Resonant Resonant MMC [20] Flyback–Forward Flyback–Forward HB/FB [21,32] [23] Resonant CFPP MMC Converter Flyback–Forwar[ HB/FB [21,32] MMC [20] HB/FB [21,32] [23] Resonant CFPP MMC Converter [20][20] Flyback–Forward 1− D 1− D MMCs Multi-Module Converters   Soft-switching            Soft-switching Soft-switching Soft-switching Soft-switching  Transformer Large Small Small 1 Conversion ratio ∝ N, n ∝N N, 11−11 ∝ N, 1D1, n[23] HB/FB [21,32] Resonant ∝ MMC [20] Flyback–Forward CFPP Converter D,n 1 1 Fault tolerance Low Low Medium High 1− ∝ N , n ∝ N , n ∝ N , n ∝ N , n ∝ N ∝ ∝ N N Conversion ratio ratio Conversion ratio Conversion ratio ∝N ,NSmall , ∝NSmall ∝,N , , n , ∝ , n, n ∝∝ ,N ,N , n, n ∝N Transformer Large  Conversion Soft-switching −D −D 1 −1 D 1 −1 D 1 −1D− D Fault tolerance Low Low Medium High 1Small 1Small  ,Transformer  ,n Transformer Large ratio Small Large Transformer Large Large 6. Conclusions ∝ N n Transformer ∝ NSmall Conversion ∝ N , Small ∝ N ,Small ,n 1High − D 1Medium −D Fault tolerance Low Low Fault tolerance Medium Medium Low Low High Fault tolerance Low Low Fault tolerance Low Low Medium A multi-port high voltage gain modular DC/DC 6. Conclusions  applied in offshore wind Transformer Large power converter Smallfarms Small is proposed in this paper.Fault Thanks to the modularity, the high output voltage and power is achieved tolerance Low Low Medium High Conclusions 6. Conclusions 6.6. Conclusions 6. Conclusions Soft-switching



A multi-port high voltage gain modular DC/DC power converter applied in offshore wind farms is proposed in this paper. Thanks to the modularity, highconverter output voltage and power iswind achieved multi-port high voltage gain modular DC/DC Athe multi-port power converter high voltage applied gain in modular offshore DC/DC wind farms power converter ap AA multi-port high voltage gain modular DC/DC A multi-port power high voltage applied gain in modular offshore DC/DC farms power converter appli 6. Conclusions proposed this paper. Thanks the modularity, is proposed the in high this output paper. voltage Thanks and to the power modularity, achieved high output vo is is proposed inin this paper. Thanks toto the modularity, is proposed the inhigh this output paper. Thanks voltage to and thepower modularity, is is achieved thethe high output volta A multi-port high voltage gain modular DC/DC power converter applied inthe offshore wind farm adding power cells. With the independent operation adding power each cells. port With and the high independent control flexibility, operation of each port and byby adding power cells. With the independent byby adding operation power ofof each cells. port With and the high independent control flexibility, operation the of each port and h is proposed in this paper. Thanks to the modularity, the high output voltage and power is achiev converter can collect power from multi-sources converter without can collect bus cable. power Additionally, from multi-sources the CFPP without cells bus cable. A converter can collect power from multi-sources converter without can collect bus cable. powerAdditionally, from multi-sources the CFPP without cells bus cable. Add bylosses adding power cells. With the operation ofcontrol eachcomplexity. port and high control flexibility, t reduce the switching losses and control complexity. reduce the switching losses and complexity. reduce the switching and control complexity. reduce theindependent switching losses and control converter canwith collect powerThe from multi-sources without bus cable. Additionally, the CFPP ce Theperformances performances MMC withgalvanic galvanic The isolation, performances resonant of MMC, MMC multi-module with galvanic converter isolation, resonant MM The ofofMMC isolation, performances resonant ofMMC, MMC multi-module with galvanic converter isolation, resonant MMC,


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by adding power cells. With the independent operation of each port and high control flexibility, the converter can collect power from multi-sources without bus cable. Additionally, the CFPP cells reduce the switching losses and control complexity. The performances of MMC with galvanic isolation, resonant MMC, multi-module converter with flyback–forwarding cells and CFPP cells are compared. The proposed model appears to be more efficient and reliable, including fewer switching losses, higher conversion ratio, fewer components, smaller volume, and higher reliability. The simulation results verify the advantages of the proposed converter are the soft-switching of all power switches, flexible control, and improved fault tolerance operation. Author Contributions: Conceptualization, Y.H. and G.C.; Formal analysis, S.S. and Y.H.; Investigation, S.S.; Methodology, S.S., Y.H. and G.C.; Software, S.S. and G.C.; Supervision, Y.H.; Validation, S.S.; Writing—original draft, S.S.; Writing—review and editing, K.N., J.Y., H.W. and X.Y. Funding: This study is supported by the State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources under Grant LAPS17022. Conflicts of Interest: The authors declare no conflict of interest.

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