Multilevel Modular Converter with Reduced Device Count for Hybrid and Electric Vehicle Dong Cao, Xiaofeng Lyu, and Yanchao Li North Dakota State University
[email protected] Abstract- This paper presents a low cost multilevel modular switched capacitor dc-dc converter for high power and high voltage conversion ratio application with reduced device count. The switching devices number of the traditional multilevel modular switched capacitor dc-dc converter is increasing fast with the increase of conversion ratio. Large number of switching devices means more gate drive circuit, more complex and higher cost. The proposed circuit has low device number, low device voltage stress and current stress. The proposed circuit also inherits the modular structure, simple control, low conduction loss, high switching frequency operation capability, and soft switching features from the traditional multilevel modular switched capacitor dc-dc converter. Therefore, a high voltage conversion ratio switched capacitor dc-dc converter with low cost and simple structure can be built using the proposed circuit. Simulation results are provided to validate the operating principle and features of the circuit.
I.
makes it very costly for high voltage gain application. The flying capacitor multilevel dc-dc converter (FCMDC) proposed in [5- 13] has low device count and voltage stress features. But it is more suitable for low conversion ratio applications. With the increased conversion ratio of FCMDC, it will suffer excessive conduction loss, high tum off current with high voltage overshoot [9, 14]. Zero current switching of the devices is also difficult to achieve due to the asymmetric structure of charging and discharging loop [5, 9, 10, 12]. A multilevel modular capacitor-clamped single-wing converter
multilevel
dc-dc converter
modular
(SW-MMCCC)
is
(MMCCC)
capacitor-clamped
proposed
to
or
dc-dc
overcome
the
drawback of FCMDC for high voltage gain application [ 1419]. Since SW-MMCCC better descirbe the circuit, in order to keep the terminology consistency of the all the papers writen
INTRODUCTION
by the author, in the following section only SW-MMCCC will
With the increase of oil price and customer expectation of
appear for the simplification purposes. The SW-MMCCC with
high fuel economy passenager vehicle, hybrid and electric
five times conversion ratio main circuit structure is shown in
vehicle with an electric power train become a major approach
Fig. l. Compared with FCMDC with five devices connected in
across
power train
series for the charging/discharging loop, SW-MMCCC at most
normally composes a high voltage battery pack, an inverter
use three devices for each loop. And FCMDC device current
the
automotive
industry.
The
electric
system, and electric motors. The major design considerations
stress is equal to n times of the SW-MMCCC device current
of the electric power train are the total system cost, packaging
stress.
size, and weight. The low cost battery pack design trend tends
overshoot is expected in SW-MMCCC. In order to reduce the
Therefore,
reduced
conduction
loss
and
voltage
to reduce the number of battery cells connected in series with
switching loss and capacitor size SW-MMCCC a zero current
increased cell current capability. To design the motor with the
switching technique by using properly designed PCB trace or
same power rating, a high voltage low current motor is
busbar as the air core inductor has been proposed [20-24]. By
preferred with thinner conductor size and reduced ac loss. A
using this method, device switching loss, capacitor ESR loss
bidirectional boost dc-dc converter is normally used as an
and size can be significantly reduced by proper use of
interface to connect the battery pack and the dc-link capacitor
multilayer ceramic capacitor. The high input current ripple
of the three phase inverter. However, the high power inductor
issue of zero current switching SW-MMCCC can be solved by
in the boost converter is very heavy, bulky, costly, and with
the interleaving strategy, which makes high current and high
many thermal design challenges, which becomes one of the
power SW-MMCCC design more practical [22, 24]. A double
major concerns in the inverter system design to further increase
wing (DW)-MMCCC with even and odd conversion number as
the
system
efficiency,
power
density
and
reduce
cost.
shown in Error! Reference source not found. and Error!
Therefore, to design a high power bidirectional dc-dc converter
Reference source not found., and its simplified version have
with high conversion ratio without using high power inductor
been proposed in [ 19, 25] to further reduce the capacitor
becomes an interesting research topic.
voltage stress and device number. The DW-MMCCC has the
Many switched-capacitor dc-dc converters without using
same device number with SW-MMCCC assuming the same
inductor have been used in the low power area to achieve high
conversion ratio. DW-MMCCC capacitor voltage stress is
efficiency and power density since
reduced by half compared with the SW-MMCCC.
1970s [ 1-3]. Recently,
many multilevel dc-dc converters without using inductor have
This
been proposed high power automotive application [4-13]. The
modular
converter in [4] has low device and capacitor voltage stress
device count for high voltage gain and high power automotive
features, but the parabolic manner increased device count
application. The total device number of the proposed circuits is
978-1-4673-6741-7/15/$31.00 ©2015 IEEE
paper presents
a
low
switched-capacitor
cost
dc-dc
single-wing
converter
multilevel
with
reduced
only about half compared with FCMDC, and about one third compared with SW-MMCCC when the conversion ratio is
Wing Side Switches
Low Voltage Side Switches
high. And all the device voltage stress is the similar to the traditional SW-MMCCC. The low voltage side device current rating is increased due to the reduction of device number. Since the low voltage Silicon/GaN MOSFETs tends to have better performance, the increased current rating will not affect the practical design. The gate drive cost can also be reduced significantly. The total capacitor voltage stress and capacitor number of the proposed circuits is the same with the SW MMCCC.
The proposed circuit combines the benefits of
FCMDC and SW-MMCCC with lowest device and capacitor count and stress. It can be considered as an simplified version of SW-MMCCC with same performance [25][27][32]. It also can be interleaved to reduced input current ripple for high
(a)
Low Voltage Side Switches r······················..·:ls'B 3
Wing Side S���� SB� ST�
_________
.-4-�----���.'T���
I
_________
SB�
•••
power application. Simulation results are provided to validate the proposed circuit operating principle and features.
+
(b) Fig. 2 (a) Proposed LC-sw-MMCCC with five times conversion ratio example. (b) Proposed LC-sw-MMCCC with n times conversion ratio. Fig. I. MMCCC/Sw-MMCCC main circuit structure with five times conversion ratio II.
PROPOSED Cm.CUITS AND OPERATING PRINCIPLE
Fig. 2(a) shows the proposed low cost single-wing multilevel modular
switched-capacitor
dc-dc
converter
(LC-SW
MMCCC) with reduced device count and five times conversion ratio. Fig. 2 (b) shows the proposed circuit with n times conversion ratio. The low voltage side switches and the wing side switches are seperated using dotted boxes.
Fig. 3. Gate signal of the switches of the proposed circuit,only two switching states with 50% duty cycle.
The low
voltage side switches have the same voltage rating which is the same as the low voltage side input voltage which is Vin. One the wing side, the voltage rating of the first switch and the last switch, i.e. SS3 and SS5, or SS3 and SS(n+5)12 are the same as the low voltage side input voltage. For all the other switches on the wing expect the first and the last switch, the voltage rating is 2 Vin. Fig. 3 shows switches gate control signals of the proposed circuit. Similarly with the SW-MMCCC, the proposed circuit only need two complementary control signals with 50% duty
(a)
cycle. The two equivalent circuit of the circuit operation can be shown in Fig. 4. All the switches that are turned on are drawn, and all the switches that are turned off are not shown in the figure. It can be shown in the figure, different from the SW MMCCC the proposed LC-SW-MMCCC used low voltage side devices ST], ST2, SSh SSJ have been used multiple times in different caapcitor charging/discharging loops. And with the increase of the conversion ratio, the current stress of these switches will be about (n- l)/2 times higher than the switches
(b)
on the wing side, i.e. ST3, ST4, SS3, SS4, SS5, which can be easily
Fig. 4 Two switching states. (a) Switching state I: STI- ST4 are turned on (b) Switching state II: SBI - SB5 are turned on
derived from Fig. 4.
III.
DEV[CE STRESS AND PASS[VE COMPONENTS STRESS COMPARISON
Table I shows the comparison of the SW-MMCCC and the
IV. A.
DES[GN CONSIDERATION AND ZERO CURRENT SW[TCHING OPERATION
Design Consideration
proposed LC-SW-MMCCC in terms of total capacitor and
Similialy to the SW-MMCCC, there will be two design
device number, device and capacitor voltage stress and current
points to achieve high efficiency according to the capacitance
stress. The LC-SW-MMCCC is seperated to two columns with
and stray inductance value in each charging and discharging
odd and even conversion ratio, since the low voltage side
loop, as mentioned in [26]. When the capacitance is very large,
switches current stress is slightly different. It can be shown
the circuit will operate at over-damped mode with charing
from the table that, the number of capacitors, capacitor voltage
current shape similiarly to a square waveform. In order to
stress, device voltage stress, as well as the wing side device
achieve
current stress for the proposed LC-SW-MMCC are the same
capacitance value and low switching frequency is normally
high efficiency in
the
over-damped
mode,
high
with SW-MMCCC. And the total device number of proposed
used to minimize the rms current through the switching devices
circuit is only N+4 assuming the conversion ratio is N, which
and capacitors. High capacitor value electrolytic capacitors is
is a significant reduction. The low voltage side devices current
normally preferred for the over-dampled case design. However,
stress are increased with the increase of the voltage conversion
since the ESR of the electrolytic capacitor is still relatively
ratio. If single die the low voltage and high current rating
large, in order to achieve high efficiency and high current
devices are available for certain application, the proposed LC
application,
SW-MMCCC is superior. For the application that very high
connected in parallel, which leads the design with huge
more
electrolytic
capacitors
are
needed
to
current >300 A rating devices have to be used, which means
capacitor banle On the other hand, by properly designing the
multiple dies or multiple devices have to be connected in
busbar or PCB trace of the proposed circuit, the circuit can be
parallel, the traditional SW-MMCCC has more benefits with
designed to operate at under-damped mode. Selecting the
separate gate drive for each devices. The practical circuit
switching frequency properly, which is the same as the circuit
topology that should be used for certain application needs to be
resonant frequency, can help the switching device to achieve
evaluated carefully to have a better tradeoff of cost and
zero current switching. Due to the symetric circuit operation, if
performance.
stray inductance can be carefully designed, the zero current
Table [ ComEarison of SW-MMCCC and LC-SW-MMCCC
No. of Conversion Ratio No. of capacitors
switching for all the switching devices can be achieved. Proposed LC-SW-MMCCC with five times conversion ratio is
SW-MMCCC
LC-MMCCC (odd)
LC-SW-MMCCC (even)
N
N (2n)
N (2n+l)
designed in the circuit as shown in Fig. 5(a). The inductor LSi
N
normally designed smaller than LSi and LS2 due to the influence
NVin
as the equvalent series inductance in each circuit conduction
used as an example for the zero current switching design practice. Three air core inductor using busbar is properly and LS2 can be designed with the same value, LS3 value is
N
N
of load current. These three stray inductance can be considered
Peak capacitor voltage stress
NVin
Total capacitor voltage stress
N(N+I)Vinl2
N(N+I)Vinl2
N(N+I)Vinl2
No. of switches
3N-2
N+4
N+4
Switch voltage stress
' " Vin ,2Vin
Vin,2Vin
Vin,2Vin
10
(n-I)10/2
''' nlo/2 , .... (n-2)[0/2
Low voltage side switches average current stress Wing side switches average current stress ,
NVin
loop. Since there is only three current loop in the example circuits as shown in Fig. 6. Three series equivalent stray inductors are representative enough for all the stray inductance distributed in the circuit.
B.
Proposed New PWM Control Method for Zero Current Switching Considering Parameter Variation Although the previous control method with only two signals
and 50% duty cycle can still be used for zero current switching operation, the distributed stray inductance in the circuit for each resonant loop may be different due to the asymmetric
10
10
[0
include all the switches on the low voltage side,and the first and last switches on the wing ,. all the switches on the wing except the two switches that is close to the low votlage side and high voltage output capacitor side. ... ST!,SBI,SB2 current rating .... ST2 current rating
circuit layout. And the capacitance value could also be varied at different operating points. If only two switching signals are used, the perfect zero current switching operation will be very difficult to achieve.
In order to overcome this issue for
practical application, an new gate control method for LC-SW MMCCC is proposed as shown in Fig. 9(b). Only the switches directly connected to the low voltage side STl,2 and SSJ,2 are still using 50% duty cycle. All the other switches only select portion of the time to conduct which makes the timing fine tune for each switching loop possible. Fig. 9(b) only shows an example where the stay inductance in each current loop are
symmetric
to
demonstrate
the
concept,
if
the
required
conduction time of device ST3 is shorter than others, the
V.
conduction time of device ST3 can be reduced. For example, if the capacitance C] value is lower than other capacitors, while keep all the other switching time the same as before, the conduction time of SS3 and ST3 can be reduced independently to achieve the zero current switching for every switch. The new proposed method makes the zero current switching operation with non-ideal circuit parameter possible. And since the MLCC capacitance value will drop according to the dc bias voltage, the proposed control method makes the fine tune of zero current switching for each loop possible.
SIMULATION RESULTS
A 40 kW l30V input LC-SW-MMCCC with five times conversion ratio is designed and simulated as an example.
A.
Overdamped Case For the first case, the circuit is designed to operate at over
damped case. The capacitance value is 1mF with 1 mn ESR. The switching device tum on resistance is 3 mn. In order to achieve relatively quasi-square current waveform to reduce switch conduction loss, the switching frequency is selected at 200 kHz. And the device switching loss is neglected. The output voltage is about 64 1 V. The conversion ratio is slightly lower than five due to the internal resistance of capacitor as well as the switching device turn on resistance. From the simulation results we can easily derive that the device voltage stress is either equal to input voltage or twice of input voltage. And the switching devices STJ, ST2, SSI, SS2 current stress is twice
as
much
as
other
switching devices,
while
other
switching devices current stress are the same. Except the output capacitor C5, all the other capacitors CI, C2, C3, C4, have very similar current stress which is about twice of the capacitor
(a)
C5 current stress. However 200 kHz is not very practical for
STl,2
high power high current application due to the switching
Sn ST4
SBI.2
SB3,5
device performance limit even using SiC MOSFETs. If the switching frequency is reduced to 10
I
I
I
I
SB4 O
Ts/2
Ts
3 Ts/2
2Ts
5Ts/2
�
20 kHz, the current
waveform using the 1 mF capacitor design will become a
I
t-
3Ts
typical over-damped shape with huge rms value as shown in t
(b) Fig. 5. (a) Proposed LC-MMCCC zero current switching operation mode using three air core inductors, (b) proposed switching gate control diagram for zero current switching operation.
Fig. 8, which evitably increase the power loss of the proposed
converter. The output voltage of the converter is also reduced significantly due to the extra power loss of the switches and the capacitors. Only about 625 V can be achieved for this case only considering the conduction loss. Otherwise, much larger capacitor bank as large as 10 mF
-
20 mF is needed to
designed in order to keep the similar current shape. B.
Under-damped Zero Current Switching Case If the circuit is designed at under-damped with zero current
switching. Much smaller capacitance is needed for the high power converter design. Fig. 9 shows the simulation results of the zero current switching operation mode of the proposed LC SW-MMCCC with five times conversion ratio. The proposed new PWM switching pattern is also been implemented. All the capacitance value is only 47 uF, capacitor ESR is 1 mn, switching device tum on resistance is 3 mn, air core inductor
(a)
LSI and LS2 are 2 16 nH, inductor LS3 is 125 nH. The switching frequency is 50 kHz. VI.
CONCLUSION
This paper proposed a low cost multilevel modular capacitor clamped dc-dc converter with reduced device number. The proposed circuit inherent all the good features of MMCCC with low device voltage stress and low conduction loss.
(b) Fig. 6 (a) Three equivalent circuits when the switches SBI,2,3,4,5 are turned on. (b) Two equivalent circuits when the switches S TI,2,3,4 are turned on.
Besides, the number of devices of the proposed circuit can be significantly reduced which lead to the lower cost and more compact design. By properly designing the circuit busbar, zero
current switching operation of the proposed circuit can be achieved. With the proposed new PWM control method for zero current switching operation, each circuit loop parameter and corresponding switching time can be independently tuned. Therefore, the zero current switching for each switching device can be achieved by fine tuning the conduction time of each switch
even
with
some
different
stray
inductance
and
capacitance in each loop. By using the zero current switching operation mode, a high power density and high efficiency converter
can
inductance
be
built
with
requirement
and
very
low
capacitance
relatively
low
and
� $
switching
to �verify the features of the proposed circuit.
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