Multilevel Multichannel Interleaved AC-DC Converter ...

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ABSTRACT. In this paper an analysis and implementation of a voltage source multi-level multi-channel interleaved ac/dc converter structure will be presented.
Multilevel Multichannel Interleaved AC-DC Converter for High Current Applications ABSTRACT In this paper an analysis and implementation of a voltage source multi-level multi-channel interleaved ac/dc converter structure will be presented. The primary application of the converter is for active rectifiers or grid-tie inverters to interface renewable energy sources or energy storage devices. The multilevel structure ensures reaching higher voltage levels and the parallel interleaved approach allows for reaching higher currents and higher effective carrier frequency. Significant reduction on the size and weight of the passive components such as the ac linkage reactor and the grid side ac filter can be attained, as well as reduction of the ripple and RMS value of the dc bus capacitor’s current. The converter structure has a modular architecture where each converter sub-module will be able to switch at switching frequencies that would comfortably ensure low total switching losses but increased effective carrier frequency. The reduction of the input inductance will also contribute to reduction on copper losses and therefore higher converter efficiency. The reduction on dc bus capacitor’s current will result in lower heat dissipation, thereby extending its lifetime. The paper presents an example with three 3-Level interleaved channels where the control of the circulating currents among the sub-channels is attained by the addition of a closed-loop zero-component controller to the traditional d-q synchronous reference frame. Simulations and experimental results for a down-scale prototype 230 V/15 kVA will be presented and discussed. I. INTRODUCTION In the power electronics community, it is well recognized that a larger number of applications are demanding higher current and more efficient converters. The proliferation of large renewable energy sources is challenging the traditional converter structures to comply with the ever steeper current and voltage levels, and higher efficiency targets. Grid-tie converters, often used to transfer large blocks of power from renewable sources not only need to comply with higher power constraints but also need to comply with more stringent power quality standards [1]-[2]. Volume and weight of magnetic components such as reactor and LC filters are significant in medium-voltage power converters. High-switching-frequency operation without exceeding the semiconductors thermal limits is essential for reducing the volume of the magnetic components. In the search for the optimal topology that complies with all these requirements, multiple approaches have been proposed, studied and commercialized over the years. Multilevel converters have gained significant popularity for its ability to reach higher voltage levels with lower voltage rated devices [4]-[8]. Modular multilevel structures simplify the manufacturing process, reduce cost by economies of scale and provide higher reliability by N+1 redundancy [9] . On the other hand, to reach high currents, several different approaches have been pursued by: a) using high power semiconductors valves like GTO, IGCT, IEGT and more recently the BIGT; these high current valves have the disadvantages that their switching frequency is limited to only a few hundreds of Hertz or in the best case to couple kHz (e.g. BIGT) [10] which consequently demands for large reactors and filters to eliminate the generated current harmonics and ensure controllability; b) hard paralleling of devices like IGBTs at, the semiconductor packaging or module level can operate at higher frequencies but are limited, in practice, also to a few kHz, not high enough to achieve significant benefits in reduction of passive components; and c) paralleling multiple converter channels. This last method can present issues similar to hard paralleling, since significant higher switching frequencies cannot be attained for high power converters. Also, large circulating currents can flow among channels.



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Fig. 1. M-channel N-Level interleaved voltage source converter (VSC).

 

Fig. 2. Multilevel Multichannel Interleaved converter system.

Fig. 3. Three 3-level NPC interleaved voltage source converter.

As a method to improve these limitations, intrinsically given by the semiconductors’ technology, interleaving techniques have risen as a powerful tool to increase the effective carrier frequency, thus reducing the size and weight of linkage inductors and LC filters, and at the same time increasing the converter’s frequency response. This technique has been widely and successfully implemented in low voltage dc/dc converter especially for VRM (Voltage Regulator Modules) for relatively high current and low voltage converters for microprocessors (CPUs) and point-of-load power supplies (POLs) [12][15] , however an slow penetration high power ac/dc conversion has been observed. In this respect, one of the major issues to resolve is the appearance of circulating currents among the parallel converter channels and current balancing. Two type of circulating currents are to be considered; high frequency components which depend on carrier frequency and inductor size, and low frequency components which can be eliminated by a closed-loop zero-sequence controller. In addition, for multilevel topologies the issue of balancing the capacitor voltages of each level is of major concern. Some authors have analyzed the use of 2-level interleaved topologies for UPS, active filters and motor drives [16][22]. However, multilevel interleaved topologies have not been widely studied, mainly due to the high complexity given by the high number of possible states when more than two converters are interleaved. Some examples are reported in [23] and [24]. This paper presents the analysis and implementation of a three-phase multi-channel multilevel interleaved bidirectional voltage source converter. The converter structure comprises of three 3-level voltage source converters connected in parallel through interface reactors (Lk) as shown in Fig. 1. An independent control for each converter channel is proposed. The control approach ensures proper current balancing, dc bus voltage balance and control of the circulating currents. The converter allows for bidirectional power flow necessary when interfacing with energy storage devices. It is envisioned that an arbitrary number of converters in parallel of an arbitrary number of levels could be possible to realize, where the multilevel converter-channels could be the neutral point clamped (NPC) type or flying capacitor type. In order to demonstrate the concept, three 3-level interleaved ac/dc converters interfacing with a 3- grid as depicted in Fig. 2 are analyzed. Simulations and experimental results for a 230V/15kVA system will be presented. II. 3-LEVEL MULTICHANNEL INTERLEAVED AC-DC CONVERTER a) Principle of Operation Each multilevel converter sub-module is comprised of a diode neutral point clamped (NPC) topology. The structure of each converter ensures bidirectional power flow and it can be built with IGBTs or BIGTs. The parallel connection of the submodule channels is done by interconnecting the AC side of each channel through interface reactors (Lk) and direct connection at the DC side (Fig. 3). An interleaving control mode is utilized such that the gating signals for each channel are generated by comparing the modulator with a set of triangle carriers which have a phase shift angle  = 360/M between channels, where M is total number of channels. In this way significant cancelation of the current ripple will be attained at the ac point of common coupling. Fig. 4 shows simulation results describing how the overall current ripple is reduced when using the interleaving approach for different values of interface reactors. Similarly, Fig.5 shows the total THD (including high frequency harmonics) of the input current for the same case evincing the significant advantages when using interleaving. A two to three fold improvement is observed. ia vs. Lg (%)

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Fig. 5. Overall input current THD versus interface reactance, Lk, for interleaving and non-interleaving, when three AC/DC channels are simulated.

  Voltage Balancing Controller

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Fig. 9. Simulation results: Modified duty cycles (red), SVM-equivalent modulator (blue) and zero-sequence duty cycle (pink) for mi = 0.85.

b) Control Scheme The proposed control method is based on the d-q-0 synchronous reference frame and the modulation method is based on a carrierbased equivalent to space vector modulation (SVM) technique. The generation of a carrier base SVM-equivalent modulator for 3Level NPC converter was covered in [25]; however the method has been further modified to be suitable to handle bidirectional power flow and to handle multiple converters in parallel. The control method is depicted in Fig. 6; the currents Ia, Ib, Ic of each converter module are converted to d-q-0 components by the known expression

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Then the d-q-0 components pass through PI controllers. The reference for the Id controller is obtained from the output of the DC bus voltage controller which has been modified depending on the numbers of converters in parallel by Id = 1/M. Similarly, the reference for the Iq controller is also obtained by dividing the total Iq reference by the number of converters in parallel, M. The reference for the Iz controller is zero. This closed loop zero-sequence controller is implemented only in M-1 converter channels. The outputs of the d-q-0 controllers are converted back to abc frame producing the duty cycles Da, Db and Dc; which are amplified by 2⁄√3 and then added to the zero-sequence duty cycle, dz, necessary to generate the SVM equivalence with equal distribution of the zero-states. The zero-sequence duty cycle dz is calculated according to Fig. 7. The abc duty cycles Da, Db, Dc are amplified by 2⁄√3 and then the “floor” of the non-amplified duty cycles is subtracted from the amplified duty cycles to generate a set of modified duty cycles Da’, Db’, Dc’. The range of these modified duty cycles is 2⁄√3 , 2⁄√3 . Then the maximum and minimum , , ) and , , to finally calculate the zero-sequence of these duty cycles are obtained, duty cycle, dz, by the expression (2) 1 , where k is a factor that determines the distribution of the zero states. The expression (2) is similar to the one described in [25] but with the exception that it is not necessary to define a different set of equations to determine dz for duty cycles 0.867 0.867 and 0.867 | , , | 1 as proposed in [25]. The expression (2) is adequate for values of duty cycles , , Da, Db, Dc between [-1, 1]. Fig 8 and Fig. 9 show the modified duty cycles Da’, Db’, Dc’, the zero-sequence duty cycle and the modulator for modulation index 1 and 0.85. It can be seen that the modulator is properly calculated and over-modulation does not occur even when the modified duty cycles are off the -1 to 1 range. In addition, the value k responsible for the distribution of the zero-states is modified by the output of the DC bus voltage balancing controller. The value k should be 0.5 for equally distribution of the zero-states however it is modified around 0.5 by the output of the DC voltage balancing controller as previously mentioned.

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Fig. 10. Current sharing between three 3-level NPC converters (a) without zero-sequence control loop, and (b) with the added zero-sequence control loop.

Lastly, the logic of the DC bus voltage balancing controller is modified by changing the sign of the input error according to the direction of the power flow. If the power flows from the AC to the DC side, the error should be positive when Vc1>Vc2, conversely if the power flows from the DC to the AC side, the error should be negative when the Vc1>Vc2. The zero-sequence current is implemented in only two of the three channels. Fig. 10 shows simulation results in order to demonstrate the effectiveness of the close-loop zero-sequence controller. Fig. 10.a shows the input current in phase-a for each of the three channels when the closedloop zero-sequence controller is disabled. A load step occurs at 0.3 s and 0.4 s. It can be clearly appreciated that the currents of each channel diverge to dangerous levels even though the total current is maintained below rated value (not shown). Fig. 10.b, on the other hand, shows the performance for the same scenario but, when the closed-loop zero-sequence controller is enabled. In this case, the currents of each channel are maintained tightly balanced and no low-frequency zero-sequence current is circulating. In this way it is possible to control multiple NPC converters in parallel, maintaining the zero-sequence (circulating) current near zero and the dc bus voltage balanced for bidirectional power flow. III. EXPERIMENTAL RESULTS Experiments have been conducted on a 3-phase 230V system with a 230/70 V step-down transformer and using two converter channels (Fig. 11). The input ac current for interleaving angles 0° and 180° are depicted in Fig. 12 and Fig. 13. For no interleaving ( = 0°), the maximum current ripple reaches ~ 8 A (at the peak). The current ripple of each channel is ~4 A. For the case when the interleaving angle is 180° (Fig. 13), the current ripple per channel is increased to 18.6 A (460 %) however, the current ripple in the total current is the same order of magnitude than for no interleaving, 8 A. It was found that the maximum current ripple reduction was obtained for interleaving angle equal to 90° (~3.8 A); more than 50% reduction respect to no interleaving. However, the current ripple per each channel increases to 13.5 A (~340 %). This high current ripple is due to the high-frequency circulating current between the parallel channels. Even though this increase, the RMS value of each channel’s current is not appreciably altered. Pictures of parts of the converter prototype are shown in Fig. 15 and Fig. 16. Ia=8 A 

Ia1=4 A 

Fig. 11. Experimental setup: 3-level parallel interleaved converter with two ac/dc channels.

Ia=8 A 

Ia1=18.6 A  :30 V/div  20 A/div : 20 A/div  : 20 A/div – 2 ms/div Fig. 13. Experimental results: Overall current for phase-a and current contribution from channel 1 and channel 2 for  = 180°. Ia= 46 A

:30 V/div  20 A/div : 20 A/div  : 20 A/div – 2 ms/div Fig. 12. Experimental results: Overall current for pahse-a and current contribution from channel 1 and channel 2 for  = 0. Ia= 46 A

Ia=3.8 A 

Ia1=13.5 A  :30 V/div  20 A/div : 20 A/div  : 20 A/div – 2 ms/div Fig. 14. Experimental results: Overall current for phase-a and current contribution from channel 1 and channel 2 for  = 90°. Ia= 46 A

Fig. 15. Ac/dc 3-Level phase-leg module.

Fig. 16. Three-channel ac/dc 3-level converter (9 phase-leg modules).

IV. CONCLUSIONS The analysis and implementation of a three-level multichannel interleaved ac/dc converter is presented in this paper. The advantages of the approach lie on the ability of the converter structure to reach higher current ratings and higher bandwidth than traditional grid tie converters and maintaining high efficiency. The multi-channel multilevel interleaved approach will feature a power electronics converter with higher power density, enabling the utilization of these structures in areas where footprint and weight are of great concern. The topology will enable reduced weight and size by reducing the size of its ac linkage reactors, ac filter and dc bus capacitor. The controller has been successfully tested on a Xilinx FPGA-controlled 230V/15kVA 3-level NPC system with two channels. Further analysis and experimental results for three channels will be provided in the final paper.

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