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Investigation on the non-ideal behaviour of Au/nInP Schottky diodes by the simulation of I–V–T and C–V–T characteristics A. Fritah, A. Saadoune, L. Dehimi & B. Abay To cite this article: A. Fritah, A. Saadoune, L. Dehimi & B. Abay (2016) Investigation on the non-ideal behaviour of Au/n-InP Schottky diodes by the simulation of I–V–T and C–V–T characteristics, Philosophical Magazine, 96:19, 2009-2026, DOI: 10.1080/14786435.2016.1185184 To link to this article: http://dx.doi.org/10.1080/14786435.2016.1185184

Published online: 26 May 2016.

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Date: 15 June 2016, At: 02:29

Philosophical Magazine, 2016 VOL. 96, NO. 19, 2009–2026 http://dx.doi.org/10.1080/14786435.2016.1185184

Investigation on the non-ideal behaviour of Au/n-InP Schottky diodes by the simulation of I–V–T and C–V–T characteristics A. Fritaha, A. Saadounea, L. Dehimia,b and B. Abayc a

Downloaded by [Mr abdallah fritah] at 02:29 15 June 2016

Laboratory of Metallic and Semiconducting Materials (LMSM), Faculty of Sciences and Technology, Department of Electrical Engineering, Biskra University, Biskra, Algeria; bFaculty of Science, Elhadj Lakhdar University, Batna, Algeria; cFaculty of Science, Department of Physics, Atatürk University, Erzurum, Turkey

ABSTRACT

We report the simulation of current–voltage (I–V) and capacitance– voltage (C–V) characteristics of Au/n-InP Schottky contact in the temperature range of 200–400 K by steps of 20 K with and without interface states, traps and tunnelling current. The simulation was carried out using Atlas-Silvaco-Tcad device simulator. The simulation is performed using the appropriate physical models to explain the behaviour of the physical phenomena of the Schottky diode. The simulation results of I–V–T and C–V–T without native oxide, tunnelling current and traps are far away from experimental data. Thus, native oxide, tunnelling current and traps should be considered. Our results strongly suggest that the spatial inhomogeneities at the MS interface did not affect the I–V and C–V characteristics in the simulated temperature range. zero-bias ) ( ) In addition, the extracted (parameters, barrier height ∅b0 , capacitance barrier height ∅CV and the ideality factor (n) were found to be strongly temperature-dependent due to the deviation of the transport mechanism from thermionic emission current. Moreover, the obtained results lead to a coherent explanation of the discrepancy between ∅CV and ∅b0. Good agreement of simulated I–V–T and C–V–T results with existing experimental data are obtained by considering a thin native oxide layer at the interface, traps and tunnelling current.

ARTICLE HISTORY

Received 11 January 2016 Accepted 27 April 2016 KEYWORDS

Schottky diodes; n-InP; I–V–T and C–V–T characteristics; simulation-Silvaco; transport mechanism; interface states and traps

1. Introduction Metal–semiconductor (MS) interface is an essential part of virtually all semiconductor electronic and optoelectronic devices such as microwave field-effect transistors, radio frequency detectors, photo transistors and space solar cells. One of the most interesting properties of the (MS) interface is its Schottky barrier height (SBH), which is a measure of the mismatch of the energy levels for majority carriers across the MS interface [1–3]. Metal film deposition on InP substrates has received much attention due to its high electron mobility, high-saturation drift velocity, direct energy band gap and radiation hardness compared with CONTACT A. Fritah [email protected] This article was originally published with errors. This version has been corrected. Please see Erratum (http://dx.doi.org/ 10.1080/14786435.2016.1196945). © 2016 Informa UK Limited, trading as Taylor & Francis Group


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Si and GaAs [4–6]. However, one of the major problems of the SBH based on n-InP semiconductor is its low barrier height which leads to a high leakage current [7–9]. Also III–V semiconductor technology is faced with new difficulties respect to standard semiconductor such as Si and Ge. Unless specially fabricated, a Schottky diode possesses a native insulator layer between MS Interfaces [6,7]. The formation of the SBH is a complex problem because of the dependence of the SBH on the atomic structure of the MS interface. Existing models of the SBH are too simple to realistically treat the chemistry exhibited at MS interfaces [10].In the laboratory environment, a chemically cleaned semiconductor crystal surface is usually covered with layers of native oxides even when it is exposed to clean room air for a very short time, in addition, if the semiconductor surfaces are prepared by the usual polishing and chemical etching, and the evaporation of metal is carried out in a conventional vacuum system having a pressure of around 10−5 torr, their surfaces are inevitably covered with an undesirable native oxide film [8,9,11]. Schottky barrier diode with low BH has found applications in devices operating at cryogenic temperatures as infrared detectors and sensors in thermal imaging [12]. Therefore, the analysis of the I–V characteristics of the SBD at room temperature does not give a detailed information about their conduction process or the nature of barrier formation at the MS interface. [7,11–16]. However, the analysis of the I–V and C–V characteristics at wide range of temperature based on thermionic emission (TE) theory shows an abnormal decrease in the zero-bias BH, an increase in the ideality factor and the capacitance BH [7,11–16]. Recently, the characterisation of the SBH by hot-electron spectroscopy measurement at low temperature found the BH to be temperature-independent [17]. In the last two decades, the abnormal temperature dependence of the diode parameters was interpreted by the presence of spatial inhomogeneity in the SBH at the M–S interface according to two principal models, Tung [18] model and Werner and Guttler model [19]. Most of the studies on I–V–T and C–V–T measurements uses Werner and Guttler model by assuming a single Gaussian distribution or double Gaussian distributions of the BH [7,11–16]. Such studies do not give a convincing explanation of the ∅b0 and n temperature dependence in high temperature, where the activation energy ln(I0/T2) vs. 1/T plot does not deviate from linearity. Moreover, it does not explain the temperature dependence of ∅CV . It is found that the ionised deep levels cause a change in the semiconductor charge density and consequently a change in the value of the capacitance; furthermore, they modify the slope of the C−2–V in the reverse bias region and affect the intercept Vbi [20,21]. One can perhaps points to the role played by minority carriers and tunnelling current at MS interface as areas which still need some work [1]. In this study, the I–V and C–V characteristics of the Au/n-InP Schottky diode have been simulated in the temperature range 200–400 K by steps of 20 K using Atlas device simulator of the software Silvaco-Tcad.

2. Device structure The structure used in our simulation is the same of the experimental work [13] in order to compare our results. Gold metal on the top of the structure form the Schottky contact with cylindrical geometry of 1.00 mm diameter deposited on n-InP substrate with 1.2 × 1016 cm−3 doping concentration at 300 K, while the ohmic contact constitute the bottom of the diode.


2011


3. The simulation The simulation was performed with Atlas-Silvaco-Tcad which provides general capabilities for physically based two- and three-dimensional simulation of electrical, optical and thermal behaviour of semiconductor devices. The device structure can be defined by specifying the regions, materials, doping profile and doping concentration onto a two- or three-dimensional simulation with specified mesh. The mesh is defined by a series of horizontal and vertical lines and the spacing between them; the intercept between these lines is called nodes. The electrical characteristics of the device can be achieved by solving the continuity equations, Poisson equation and the transport equations with specified numerical method in each node in specified bias conditions using the materials parameters of each region. Poisson equation including the carrier concentrations, the ionised donor and acceptor concentrations calculated by the incomplete ionisation model charge due to traps and defects. Fermi–Dirac statistics and the density of states are used to calculate the electron and the hole concentrations and the quasi-Fermi levels. The generation and recombination rates in the continuity equations includes the generation and recombination rates calculated by the generation and recombination models. For the bias conditions, the DC solution was used to calculate the IV characteristics and the AC small signal solution to calculate the CV characteristics. 3.1. Parameters and physical models The material parameters of the n-InP semiconductor used are an electron affinity equal to 4.38 eV [22] and electron Richardson constant equal to 9.4 A K−2 cm−2 [23]. The work function of the gold is equal to 4.8 eV [24,25]. For carrier statistics, we used Fermi–Dirac distribution and temperature-dependent density of states and band gap models, while other models were used for mobility temperature dependance, carrier generation–recombination, incomplete ionisation of impurities, image force lowering and current transport mechanisms. 3.1.1. Band gap model The temperature dependence of the band gap energy is modelled with Varshni’s empirical relationship [26].

Eg (T) = Eg (0) −

𝛼T 2 T +𝛽

(1)

where, T is the lattice temperature, Eg(0) = 1.42 (eV) is the band gap at 0 K, 𝛼 = 4.9 × 104 (eV K−1) and β = 327 K are material parameters [27]. 3.1.2. Mobility model Since there is no need to the doping concentration dependance according to the diode structure, we used a constant low-field mobility model that does account just for lattice scattering due to temperature [28]. ( ) T −𝛾n ,𝛾p 𝜇n,p = 𝜇n0 , 𝜇p0, (2) 300

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where T is the lattice temperature; μn0 = 4300 m and μp0 = 173 cm2 V−1 s−1 are, respectively, the electron and hole mobility in 300 K of n-InP with 1.2E16 cm−3 doping concentration [29]; γn and γp are the material parameters [30]. 3.1.3. Shockley–Read–Hall model To take into account the effect of the traps used in the simulation on the recombination of the electrons, the standard SRH recombination term is modified as follows [28]: m ∑

R=

(3)

RA 𝛽

𝛽=1


where m is the number of acceptor-like traps, the function R given as flow:

RA𝛽 =

[ 𝜏n p +

1 g

pn − n2ie )] [ ( )] Ei −Et Et −Ei + nie exp kT + 𝜏p n + g + nie exp kT (

L

(4)

L

The electron and hole lifetimes τn and τp are related to the carrier capture cross sections σn and σp through the equations:

𝜏n,p =

1 𝜎n,p vn,p NT

(5)

vn , vp are the thermal velocities for electron and hole, respectively. 3.1.4. Auger recombination Auger recombination is commonly modelled using the expression [32]:

) ( ) ( RAuger = Cn pn2 − nn2ie + Cp np2 − pn2ie

(6)

where Cn and Cp are the Auger coefficients for electron and hole of the InP semiconductor, respectively [33]. 3.1.5. Impact ionisation Zappa developed a model for temperature- and field-dependent ionisation rates in InP semiconductor [34].

� 𝛼,𝛽 �1.14 2 � 𝛼,𝛽 �2 0.5 ⎫ � 𝛼,𝛽 �1.14 ⎧ ⎤ ⎛ ⎞ ⎡ Eth E E qE ⎪ ⎥ ⎪ ⎢⎜0.217 th ⎟ + 𝛼, 𝛽(E, T) = 𝛼 exp⎨0.217 th − (7) 𝛼,𝛽 𝛼,𝛽 𝛼,𝛽 ⎥ ⎬ ⎢⎜ ⎟ Eth , 𝛽 qE𝜆 ER ER ⎪ ⎪ ⎦ ⎣ ⎝ ⎠ ⎭ ⎩ where 𝜆𝛽 , 𝜆𝛼 , ER𝛼 , ER𝛼 , Eth𝛼 , Eth𝛼 are material parameters [34], T is the local temperature and E is the local electric field. 3.1.6. Incomplete ionisation of impurities ( ) The dependence of ionised donor ND+ on temperature is modelled using Fermi–Dirac statistics with the appropriate factor for conduction band and with the introduction of quasi-Fermi level for electron [35] as:


ND+ =

ND ( E −E ) Fn D 1 + 2exp kT

2013

(8)

L

where ND is the n-type doping concentration, EFn is the electron quasi-Fermi level, ED is the donor impurity level and is equal to 0.0057 (eV) for S-doped n-InP according to [30]. 3.1.7. Thermionic emission We can describe TE current flow in terms of an effective recombination velocity at the surface of the semiconductor [36].


) ( J = q nm − n0 vR

vR =

A∗ T 2 qN c

(9)

(10)

where nm is the electron density at xm when the current is flowing, n0 is quasi equilibrium electron density at xm.

( ) n0 = Nc exp −q𝜓B ∕kT

(11)

] } { [ ( ) nm = Nc exp q 𝜑 xm − 𝜓B ∕kT

(12)

( ) ψB is the Schottky barrier at the MS interface, and 𝜑 xm is the applied voltage at xm. 3.1.8. Universal Schottky tunnelling The key feature of the model is that tunnelling current through the barrier is converted into a local generation or recombination process where the local rate, GTun (r) depend on the local Fermi level, ϕn and the potential profile along the tunnelling path [37]. [ ( )] 1 + exp −q(𝜓 − 𝜙n )∕kB T A∗ T ⇀ EΓ(r) ln GTun (r) = ( ) (13) kB 1 + exp −q(𝜓 − 𝜙m )∕kB T where JTun is the total tunnelling current density, A* is the Richardson constant, T is the lattice temperature, EFm = −qϕm is the Fermi level for the metal, EFn = −qϕn is the electron quasi-Fermi level in the semiconductor and Γ(r) is the tunnelling probability.

[ ] √ ( ) 2 r Γ(r) = exp − ∫ 2m 𝜙b ∕q + �m − 𝜓(x) dx ℏ0

(14)

3.1.9. Image force lowering The image force lowering, also known as the Schottky effect or Schottky barrier lowering, is the image force-induced lowering of the barrier energy for charge carrier emission, in the presence of an electric field [3].

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√ Δ� =

qEm 4𝜋𝜀s

(15)

where ɛs and Em are the semiconductor permittivity and the electrical field at the interface.


4. Results and discussion In order to obtain the detailed information on the current transport mechanisms at the MS interface, the barrier temperature dependence and the difference between ∅IV and ∅CV , the work was split into two parts; near ideal diode and real diode. A homogeneous barrier was used for the near ideal diode and the real diode. This assumption was based on the result of the experimental Richardson plot [13]. That is, the curved behaviour in experimental Richardson plot below 160 K was interpreted by the inhomogeneity and potential fluctuation that dramatically affect low-temperature I–V characteristics [13], and other works analyse this behaviour with similar interpretation [13,16]. This interpretation leads us to assume that the inhomogeneity of the barrier does not affect the I–V characteristics above 160 K. In addition, Tung in [18] explained the barrier inhomogeneity by fewer low-SBH regions with lower effective SBH’s and large ideality factor that dominates the junction current when the temperature is lowered, as an example of simulation of a SBD with low-SBH patches. He found that Richardson plot of such diode deviates from linearity in low temperature. Thus, the inhomogeneities are considered below 200 K. 4.1. Near ideal diode In this section, the diode structure does not contain interface state and deep traps; all the physical models described in the section three were used, except universal Schottky tunnelling model. The only transport mechanism used is TE current given as follows [2]:

(

qV I = I0 exp nkT

)[

)] ( qV 1 − exp − kT

(16)

where q is the electron charge, V is the applied voltage, K is Boltzmann constant, T is the absolute temperature, n is the ideality factor and I0 is saturation current derived from the straight line intercept of ln I at V = 0 (Figure 1) and is expressed as:

(

) −q�b0 . I0 = AA T exp kT ∗∗

2

(17)

where A is the diode area, A** is the effective Richardson constant, ∅b0 is the zero-bias BH and can be calculated by rewriting Equation (17) as:

�b0 =

( ∗∗ 2 ) AA T kT ln q I0

(18)

The values of ideality factor are calculated from the slope of the linear regions of the forward ln I vs. V plot according to [2]



2015

Figure 1. The simulated semi-logarithmic current–voltage characteristics of the near ideal diode at various temperature ranges. Table 1. The simulated parameters obtained from I–V characteristic of the near ideal diode. Ideality factor Temperature (K) 200 220 240 260 280 300 320 340 360

n 1.03 1.04 1.05 1.07 1.04 1.05 1.17 1.17 1.94

n=

q dV . kT d(ln I)

Barrier height (eV)

∅b0

∅CV

0.398 0.395 0.390 0.389 0.389 0.391 0.390 0.400 0.400

0.419 0.425 0.426 0.426 0.424 0.423 0.419 0.424 0.422

(19)

Figure 1 shows the I–V characteristics of the simulated Au/n-InP of the near ideal Schottky diode in the temperature range of 200–400 K by step of 20 K in semi-logarithm scale. The simulated current is found to be greater than the experimental current by 1.2 and 1.4 order of magnitude in temperature range of 200–300 K; when the temperature reaches close to 400 K, we observe a large leakage current, which is a result of the littleness of the BH and the effect of the temperature on the reverse saturation current. The obtained values of the SBH and the ideality factor as a function of temperature are shown in Table 1. As can be seen, the n values shows an increase from unity after 300 K, and such a behaviour can be attributed to the voltage drop across the large series resistance. As it is well known, the ideality factor is obtained from the linear region before the region where the curve is strongly affected by the voltage drop across the series resistance. This linear region shrinks and shows more non-linear regime with increasing temperature, until


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Figure 2. Zoom-in of the simulated capacitance–voltage characteristics of the near ideal diode at various temperature ranges (insert figure – the capacitance of the near ideal diode in all reverse bias range).

it disappears in 380 K due to the increase in the series resistance, which prevents the extraction of n and ∅b0 in 380 and 400 K. The ∅IV values are independent from the temperature. Figure 2 shows zoom-in of the simulated reverse bias C−2–V plot at the frequency of 1 MHz over the temperature range 200–400 K while the insert shows the capacitance in all reverse bias range; the depletion layer capacitance is expressed as [2]:

1 = C2

(

2 𝜀s 𝜀0 qN i A2

) )( kT + Vr . Vbi − q

(20)

where Vbi is the built-in voltage determined from the extrapolation of the 1/C2 plot to the voltage axis, A is the area of the Schottky contact, Vr is the reverse voltage, ɛs is the static dielectric constant equal to 12.4 for n-InP, 𝜀0 = 8.85 × 10−14 F∕cm [4,5] and Nd is the concentration of the non-compensated ionised donors and can be obtained from the slope of reverse bias (1/C2) using the next relation [4,5]. [ ] 1 2 Ni = ( ) (21) 𝜀s 𝜀0 qA2 d C −2 ∕dV The capacitance increases with the increase in temperature in the range 200–340 K, then starts to decrease. Also the values of the capacitance show a peak (a minima in the C−2–V plot) after 300 K, shifting to the reverse bias direction and their values decrease with the increase in the temperature. The shifting of the peak and the decrease of the capacitance prevent the extraction of the barrier in the temperature 380 and 400 K. The value of the barrier height can be obtained by the next equation [4,5].

�CV = Vbi + Vn +

kT q

(22)



2017

Figure 3. The simulated semi-logarithmic current–voltage characteristic of the real diode at various temperature ranges.

where Vn is the energy difference between the Fermi level and the bottom of the conduction band. The values of the BH listed in Table 1 are constant and equal to the theoretical values. The little difference between ∅b0 and ∅CV is attributed almost to image force lowering, which affects the ∅b0 and does not affect the ∅CV , because the CV method is an extrapolation to zero electrical field [38]. ) ( As can be seen, the main diode parameters n, ∅b0 , ∅CV does not show a temperature dependence behaviour, also the simulated I–V and C–V characteristics are far away from the experimental ones. Therefore, other phenomena should be considered in the next section. 4.2. Real diode To reproduce the main diode parameter, temperature dependence behaviour, and to acquire the experimental results, we used as interface state a thin native oxide layer with a thickness of 5 Å, permittivity of 7.9ɛ0 [9], positive charge between the n-InP semiconductor and the native oxide layer [8], tunnelling current (universal Schottky tunnelling model) for the transport mechanism and four deep acceptor traps. 4.2.1. I–V–T characteristics The simulated I–V characteristics of the real diode are shown in Figure 3. As can be seen, the leakage current in the high temperatures was reduced compared to the near ideal diode, which is attributed to the interfacial layer [9]. The obtained current is in very good agreement with the experimental current [13] in the temperature range 200–300 K. Since the electron does not have a sufficient energy to surmount the high potential across the interfacial layer, hence, TE current was eliminated. This was verified by carrying out the simulation without using UST model after introducing the native oxide layer. As a result, the transport conduction mechanisms are dominated by quantum mechanical tunnelling through the barrier and the insulator layer in all the temperature ranges. In this case, when

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there is a thin insulator layer at the interface of the Schottky diode, the normalisation of E00 (characteristic tunnelling energy that is related to the tunnel effect transmission probability) to the thermal energy KT cannot be used to determine the dominant current processes, because there is no thermionic current to compare with tunnelling current. The calculated values of the zero-bias BH and the ideality factor with the Equation (18) and the Equation (19) are plotted as a function of the temperature in Figures 4 and 5, respectively. As shown, both parameters exhibit strong temperature dependence, and they are ranged from 0.412 eV and 1.33 (at 200 K) to 0.501 eV and 1.02 (at 400 K). That is, the zero-bias BH decreases while the ideality factor increases with the decrease in temperature; such behaviour is in agreement with literature, and the values in the comparison temperature range are in a good agreement with the experimental ones as listed in Table 2.

( ) ( ) ( ) Figure 4. Temperature dependence of zero-bias BH ∅b0 , flat-band BH ∅fb and capacitance ∅CV BH.

Figure 5. Temperature dependence of ideality factor.


2019

Table 2. The simulated and experimental parameters obtained from I–V characteristics.

∅b0 (eV)

n Temperature (K)


200 220 240 260 280 300

Simul. 1.33 1.27 1.22 1.18 1.13 1.11

Exp. (Ref. [12]) 1.32 1.27 1.24 1.18 1.10 1.08

Simul. 0.412 0.425 0.435 0.446 0.452 0.460

Exp. (Ref. [12]) 0.415 0.429 0.437 0.448 0.459 0.465

∅fb (eV) Simul. 0.529 0.522 0.514 0.505 0.499 0.500

Exp. (Ref. [12]) 0.536 0.530 0.529 0.513 0.503 0.497

Aydogan et al. [39] and Cetin et al. [40] explained the high values of ideality factor n by the presence of a thin interfacial native oxide layer between the metal and semiconductor. Cetin et al. [9] attributed the increase in the BH to the formation of an insulating layer at the interface; in addition, the high values of the ideality factor show that there is a deviation from TE theory in the current conduction mechanism [7]. This is a part of the picture, the ideality factor and the zero-bias BH show a temperature dependence in the simulated temperature range because they were calculated by TE theory, but using the slope and the saturation current of tunnelling current that dominates the transport mechanism and does not have the same slope and the same saturation current of TE current. 4.2.1.1. Flat-band barrier height. The flat-band BH is a fundamental BH defined at a zero electric field and provides a better characterisation of the physical barrier at the MS junction. The shift of the BH becomes zero at zero electric field since, at that point, there is no charge in the surface states. In addition, the semiconductor bands are flat, precluding the tunnelling and image force lowering from affecting the characteristics. It relates the Schottky diode BH and ideality factor from an I–V measurement and is given by [38]:

�fb = n�b0 − (n − 1)

N kT ln C . q ND

(23)

( ) The flat-band BH ∅fb values are shown as function of temperature in Figure 4 by closed squares. It can be seen that ∅fb is larger than ∅b0 and it is almost constant in 300–400 K range. Below 300 K, ∅fb increases with the decrease in temperature. The variation of ∅fb (0.029 eV) in the range 200–300 K is smaller than the variation of ∅b0 (0.049 eV), and the variation is possibly due to the values of the ideality factor. The values of ∅fb are in a good agreement with the experimental ones as listed in Table 2. 4.2.1.2. Richardson and modified Richardson plot. For more investigations on the nonideal behaviour of the forward-bias I–V characteristics, we show the conventional activation energy/Richardson plot of ln (I0/T2) vs. 1000/T in Figure 6. By rewriting Equation (17) as:

( ln

I0 T

2

)

( ) q� = ln AA∗∗ − b0 kT

(24)

We can determine the activation energy (Ea) and Richardson constant (A**) from the slope and the intercept of the straight line of the ln (I0/T2) vs. 1000/T plot (Figure 6), respectively.


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2 Figure plot of ) ln (I0/T ) vs. 1000/T of the real diode (insert figure-modified Richardson plot ) ( ( 6. Richardson ln I0 ∕T 2 − q2 𝜎s2 ∕2K 2 T 2 vs. 1000/T).

The plot is found to be linear in the simulated temperature range (200–400 K); similar results have been reported by Korucu et al. [7] in this temperature range. This linearity of the simulated Richardson plot is a consequence of the barrier homogeneity. While the linearity of the experimental Richardson plot indicates that the current flow through the uniform barrier is the dominant current in that temperature range, that is, when the temperature is lowered, the junction current is dominated by fewer low-SBH regions with lower effective SBH’s [18]. An effective energy (Ea = 0.334) and Richardson constant (A∗∗ = 0.063 A K−2 cm−2) were obtained. This value of Ea (0.334) is lower than half of the energy band gap of InP semiconductor at 300 K; this confirms that the predominant conduction mechanism is not TE, since the activation energy of Richardson plot represents the effective BH. In addition, the value of Richardson constant A∗∗ = (0.063 A K−2 cm−2) is lower than the known value 9.4 A K−2 cm−22 for n-InP [23]. This is a result of the SBH temperature dependence, due to the deviation of the transport conduction mechanism from TE theory. As we discussed above, the linearity of Richardson plot is a consequence of the barrier homogeneity, but some works interpreted the main diode parameters temperature dependence by the barrier inhomogeneity even though Richardson plot does not deviate from linearity [7,41], using Werner and Guttler model [19]. Even the experimental BH values in the temperature range 200–300 K were fitted by this model. As seen in Table 2, these values were acquired using a homogeneous barrier. This contradiction is a strong reason for the investigation of this model with our data of the BH in the temperature range 200–400 K. The model assumes a Gaussian distribution of the BHs with a mean value ∅̄ b0 and a standard deviation σs. The Gaussian distribution of the BH yields the following expression [19].

q𝜎 2 �ap = �̄ b0 − s 2kT

(25)

Figure 7 shows the plot of ∅b0 vs. 1/2KT. The intercept at the ordinate of the linear fitting of the ∅b0 values determines the zero-bias mean BH ∅̄ b0 = 0.573 eV, and the slope gives



2021

Figure 7. The zero-bias BH vs. (2KT)−1 of the real diode.

the standard deviation σs = 0.075 eV. The standard deviation is a measure of the barrier homogeneity, and a lower value of σs corresponds to more homogenous BH. It is seen that the value of σs = 0.075 eV is not small compared to the mean BH ∅̄ b0 = 0.573 eV (≈13%). To confirm that the BH temperature dependence obeys this model, we plotted the modified Richardson plot in the insert of Figure 6. The plot can be obtained by combining Equations (24) and (25) as follows:

( ln

I0 T2

)

( −

q2 𝜎s2 2k2 T 2

)

) q�̄ ( = ln AA∗∗ − b0 kT

(26)

( ) ( ) As can be seen in the insert of Figure 6, the modified Richardson plot ln I0 ∕T 2 − q2 𝜎s2 ∕2K 2 T 2 vs. 1000/T according to Equation (26) should give a straight line with the slope directly yielding the mean ∅̄ b0 and the intercept (= ln AA∗∗ ) at the ordinate determining A∗∗ for a given diode area A. The values of ∅̄ b0 and A∗∗ were obtained as 0.576 eV and 9.37 A cm−2 K−2, respectively. The values of A∗∗ = 9.37 A K−2 cm−2 and �̄ b0 = 0.576 eV of this plot are in close agreement with the theoretical value of 9.4 A K−2 cm−2 for electrons in n-type InP and �̄ b0 = 0.573 eV from the plot of ∅b0 vs. 1/2KT, respectively. According to [11,13,17], the results obtained from the insert of Figures 6 and 7 refer to the existence of a spatial inhomogeneities of the BH at the MS interface. But we know that we used a homogeneous BH along the interface of the diode in all the simulated temperature range 200–400 K. This fact proves that the evidence based on ∅b0 vs. 1∕2KT and modified Richardson plots does not mean necessarily that the spatial inhomogeneities of the barrier at the MS interface affect the transport in all investigated temperature range, especially in the range where the conventional Richardson plot is linear. That is, this approach does not address the lateral length scale of the inhomogeneities [11]. Unlike Tung model [18] that takes into account the length scale of the low-SBH regions, which affects the current transport in low temperatures when the current becomes lower.


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4.2.2. C–V–T characteristic We saw in the Section 4.1 that the values of the simulated reverse bias C−2–V characteristics of the near ideal diode (Figure 2) are lower than the experimental ones in the comparison temperature range 200–300 K. And we know from Equation (20) that the C−2 depends on 1/Ni, which means that the decrease of Ni makes increases the C−2. This can be done by the presence of a deep acceptor traps (negatively charged when full) in the depletion region [20]; this causes a net decrease in the depletion region charge density and consequently an increase in the values of C−2. We studied the effect of several traps mentioned by works made spectroscopy measurements on Au/n-InP samples [42–44]. By changing the density and the location of each combination of traps, finally we found four acceptor traps that give the same values and especially the same slope of the experimental C−2–V characteristics in the temperature range 200–300 K. The traps are E1 (Ec-0.69), E2 (Ec-0.62), E3 (Ec-0.51) and E4 (Ec-0.43) with a density close to 10% of the doping concentration. Figure 8 shows simulated C−2–V plot of the real diode as a function of temperature at frequency of 1 MHz. We observe the absence of the capacitance peak (the minima in C−2–V plot), except in the temperatures 380 and 400 K. The position of the peak in these two temperatures was shifted to the forward-bias direction with a few hundred mV, and the value of the peak was reduced compared to the capacitance of the near ideal diode; this behaviour attributed to the thin insulator layer at the interface. The C−2 values of the real diode are in very good agreement with the experimental data, and this is a strong evidence that proves the presence of the previous traps (E1, E2, E3 and E4) in the experimental sample. The values of ΦCV were calculated using Equation (20) and are shown in Figure 4 by open diamonds as a function of temperature. The corresponding values in the temperature range 200–300 K are given in Table 3 with the experimental ones. As shown in Figure 4, ΦCV increases with the decrease in temperature; this temperature dependence of ΦCV is attributed to the deep acceptor in the depletion region. The ionised acceptor traps below the Fermi level decrease the capacitance making the built-in voltage to increase and consequently the increase of the BH. In more details, the major role of the

Figure 8. Plot of reverse bias C−2–V characteristic of the real diode at various temperature ranges.


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Table 3. The simulated and experimental parameters obtained from C–V characteristics of the real diode.

𝜙CV (eV) Temperature (K)


200 220 240 260 280 300

Simul. 0.529 0.527 0.522 0.515 0.512 0.506

Exp. (Ref. [12]) 0.531 0.527 0.525 0.517 0.518 0.508

ΦCV temperature dependence is the level E4, due to the dependence of its ionisation on bias and temperature. Because of the low activation energy of this level, its ionisation density decreases with the increase in reverse bias, which consequently raises the built-in voltage. When the temperature decreases, the Fermi level moves up, which increases the ionisation density of the level E4 compared to the previous temperature in the same reverse bias, which in turn increases the built-in voltage compared to the previous temperature. ( ) As can be seen from Figure 4, the(BH )values from C–V characteristics ∅CV are larger than those from I–V characteristics ∅b0 in the temperature range 200–340 K. This difference is larger than the image force lowering values, on contrary to the case of the near ideal diode. After 340 K, the ∅CV values become lower than ∅b0 values, and similar results have been found by [15,45]. Based on the previous results obtained from I–V–T and C–V–T characteristics, we can explain the discrepancy between ∅CV and ∅b0. If the barrier at the MS interface is homogeneous and thermionic current is the dominant conduction mechanism and there are no deep traps in the depletion region of the semiconductor, the values of ∅CV and ∅b0 will be equal, if we neglect the image force lowering. However, when there is an interfacial layer at the MS interface, the tunnelling current dominates the transport mechanism, which causes the temperature dependence of the ∅b0, while the ∅CV is insensitive to tunnelling current. On the other hand, the presence of deep traps in the depletion region of the semiconductor causes the temperature dependence of the ∅CV , while the ∅b0 is insensitive to the traps, because the low-density traps do not affect the forward current.

5. Conclusion In the first time, both current–voltage (I–V) and capacitance–voltage (C–V) characteristics of the Au/n-InP SBD have been simulated with Atlas-Silvaco-Tcad in the temperature range 200–400 K. By analysing the main diode parameters behaviour with the change of temperature in the absence and presence of interfaces states, tunnelling current and traps (near ideal and real diode), we are able to explain the abnormal temperature dependence of the main diode parameters and the discrepancy between ∅b0 and ∅CV . The presence of thin native oxide layer with atomic dimensions thickness at the interface of the diode eliminates TE current because it does not have a sufficient energy to surmount the high potential across the native oxide layer, which makes the tunnelling current the dominating transport mechanism. As a result of the deviation of the transport mechanism from TE current, the ideality factor and the zero-bias BH show strong temperature dependence. On the other hand, the deep levels are found to be the responsibility for the temperature dependence of

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∅CV . The discrepancy between ∅b0 and ∅CV in the simulated temperature range can clearly be explained by the difference of the temperature dependence causes, that is, the ∅b0 temperature dependence is due to the deviation from TE current, and the ∅CV temperature dependence is due to the deep acceptor traps. In addition, the results have shown that the linearity of Richardson plot is a consequence of the barrier homogeneities, which mean that the inhomogeneity of the barrier does not affects the transport in the temperature range where Richardson plot has a linear form.

Disclosure statement No potential conflict of interest was reported by the authors.


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