Nanocrystalline silicon thin film transistors - IEEE Xplore

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Abstract: P-channel and n-channel thin film transistors (TFTs) can be made from ... integrated for p- and n-channel TFT fabrication on single glass or Kapton E ...

Nanocrystalline silicon thin film transistors I-C. Cheng and S. Wagner Abstract: P-channel and n-channel thin film transistors (TFTs) can be made from directly deposited nanocrystalline silicon (nc-Si:H) at temperatures as low as 1501C. A staggered top gate, bottom source/drain geometry, which is adapted to the structural evolution of nc-Si:H, ensures that the channel is the last-to-grow layer, avoids plasma etch damage, and opens a wide process window for source/drain patterning. The TFT structure is fabricated on top of a B50 nm thick intrinsic nc-Si:H seed layer, which serves to develop the crystalline structure of the channel layer. A hole mobility of B0.2 cm2 V1 s1 and an electron mobility of B40 cm2 V1 s1 are obtained in TFTs on glass substrates, at a maximum process temperature of 1501C. The processes have been integrated for p- and n-channel TFT fabrication on single glass or Kapton E polyimide substrates. The p-channel TFTs reach a hole mobility of B0.2 cm2 V1 s1 on glass and B0.17 cm2 V1 s1 on Kapton, and the n-channel TFTs have an electron mobility of B30 cm2 V1 s1 on glass and B23 cm2 V1 s1 on Kapton. These mobility values suggest that directly deposited nc-Si:H is an attractive channel material for realising CMOS on plastic. However, high gate leakage and shifts in the TFT characteristics indicate that the gate dielectric and the channel layer/dielectric interface are not yet ready for CMOS fabrication.

1

Introduction

Flexible electronics are attracting great attention because they possess the desired features, light weight and ruggedness, for many new generation large-area electronic products. Applications include display wallpaper, rugged X-ray sensor arrays, sensor skin and e-textiles. To realise these large flexible conformable electronic systems, a versatile transistor backplane, which provides power and signal to the functional front plane, is the basic prerequisite. The ideal backplane should be fully integrated to drive, switch and perform the specific cell (pixel) function, and to provide computation, memory and signal transmission. These electronic functions require a CMOS capable transistor technology. The substrate needs to be lightweight, flexible, foldable, and deformable; organic polymer (plastic) and metal foils both are good candidates. The advantages of using metal foils are dimensional stability and process temperature that can go up to 10001C, but metals are opaque and introduce parasitic capacitance. On the other hand, plastic substrates can be transparent and even clear, but restrict the temperature for extended deposition and processing to approximately 1501C or less. Hydrogenated amorphous silicon thin film transistors (aSi:H TFTs) are the current industrial standard in large-area electronics. Several studies have focused on fabricating aSi:H TFTs on plastic substrates [1–5]. However, complementary circuits are out of reach of a-Si:H because its hole mobility is insufficient for p-channel operation. Combining fully integrated circuits with plastic substrates calls for radical innovation in transistor technology and fabrication. This is the driver behind present programs on transistors of r IEE, 2003 IEE Proceedings online no. 20030573 doi:10.1049/ip-cds:20030573 Paper first received 20th January and in revised form 8th April 2003 The authors are with the Department of Electrical Engineering, Princeton University, Princeton, NJ, 08544, USA IEE Proc.-Circuits Devices Syst., Vol. 150, No. 4, August 2003

excimer laser crystallised polycrystalline silicon [6–9], organics [10–13], p-channel organic/n-channel a-Si:H hybrids [14], and silicon microblocks [15]. We are pursuing the highly attractive alternative of nanocrystalline silicon (nc-Si:H) directly deposited at 1501C, and have demonstrated high electron and usable hole field-effect mobilities [16, 17]. 2

Experiments

We work with both glass (1.1-mm thick Corning 1737 glass) and plastic (50-mm-thick Kapton polyimide) substrates. The Kapton E polyimide is chosen because of its (i) high thermal stability, with a glass transition temperature of B3501C, (ii) low coefficient of thermal expansion, 12  106/1C and (iii) good TFT film adhesion. While we fabricate devices directly on glass substrates, both faces of the Kapton substrate are first passivated by B500-nm-thick PECVD SiNx:H at 1501C. During most fabrication steps the Kapton is kept as a free-standing film, except in photolithography when we temporarily bond the Kapton to glass. All the process steps are first developed and optimised on glass substrates and then are moved to plastic substrates.

2.1

Nanocrystalline silicon film deposition

High crystallinity, which leads to high field-effect mobility, and low dark conductivity, which gives low OFF current, are the two goals for intrinsic nc-Si:H film deposition. The intrinsic film is deposited by PECVD at 80 MHz VHF excitation frequency from a gas mixture of hydrogen, silane, and dichlorosilane (DCS). The deposition parameters are a pressure of 500 mtorr (66.7 Pa), an absorbed power of 86 mW/cm2 and a hydrogen dilution ratio of R ¼ [H2]/ [SiH4+SiCl2H2] ¼ 20 to 30. The high hydrogen dilution ratio and VHF excitation frequency produce high film crystallinity even at a substrate temperature as low as 1001C [18–21]. To achieve low dark conductivity, 20B30 vol.% of dichlorosilane is added to the SiH4 source gas, to reduce the 339

dark conductivity of a B300-nm-thick film at room temperature to B6  107 S cm1 for R ¼ 20 and B3  106 S cm1 for R ¼ 30 [22]. Diborane and phosphine are used as dopant gases for p-type and n-type nc-Si:H film deposition, respectively. The deposition parameters for the doped layers are a pressure of 500 mtorr (66.7 Pa), an absorbed power of 103 mW/cm2 and a hydrogen dilution ratio of R ¼ [H2]/ [SiH4+B2H6] ¼ B200 for p-type and R ¼ [H2]/[SiH4+ PH3] ¼ B100 for n-type. The hydrogen dilution ratio is kept high to compensate for the degradation of crystallinity by the dopants. Higher electrical conductivities are obtained when the film is deposited at 80 MHz excitation frequency than at 13.56 MHz RF frequency. At present we obtain a conductivity of B0.5 S cm1 for p-type nc-Si:H films and B20 S cm1 for n-type films, both deposited at 1501C on glass substrates.

2.2 Monolithic fabrication of p- and n-channel TFTs After developing separate n-channel and p-channel TFTs to identify optimal process parameters, we moved to a monolithic CMOS process. The TFTs are fabricated in a staggered top-gate, bottom source/drain geometry adapted to the nc-Si:H structure evolution. The maximum process temperature is 1501C. The fabrication sequence for the integrated devices is shown in Fig. 1. First, a 50-nm-thick intrinsic nc-Si:H seed layer is deposited on the substrate, followed by a 50-nm evaporated Cr as the bottom source/ drain contact metal, a 60-nm PECVD p+ nc-Si:H layer and a 100-nm thick PECVD SiO2 layer. The purpose of the SiO2

1. 50 nm i nc−Si seed layer deposition on substrate at 150°C

2. 50 nm Cr evaporation followed by 60 nm p+ nc−Si and 100 nm SiO2 protection layer deposition at 150°C

layer is to provide physical separation between the p+ layer and the following n+ nc-Si:H layer; it also serves as the etch-stop layer during the patterning of the n+ layer. To expose the region for n+ nc-Si:H deposition, the SiO2 and p+ nc-Si:H are patterned by first wet chemical etching and then dry plasma etching. After deposition of the 60-nm PECVD n+ nc-Si:H layer, the portion of the n+ on top of the SiO2, and the SiO2 itself, are removed by plasma etching and wet chemical etching. Both of the doped nc-Si:H layers and the contact metal are then patterned into source/drain regions. During the dry etching of the doped nc-Si:H, the Cr layer serves as the etch-stop layer to prevent any overetching into the seed layer. The sample is piranha cleaned before channel layer deposition. A 50-nm thick intrinsic ncSi:H layer is deposited as the channel layer, followed by deposition of a 300-nm-thick PECVD SiO2 gate dielectric. Before opening the contact holes, the samples are annealed in nitrogen gas at 1501C for 1 h and then in oxygen, also at 1501C for 1 h. After opening the contact holes to the source/ drain Cr layer by wet chemical etching and dry reactive ion etching, 200-nm Al is thermally evaporated and patterned for contacts. No post-annealing is performed. 3

3.1

Results and discussion

Nanocrystalline silicon film

The structural evolution of nc-Si:H depends on several factors: (i) H2 dilution, (ii) deposition temperature, (iii) film thickness and (iv) type of substrate. To reach high mobility and low OFF current, nc-Si:H films must be grown as thin as possible but reach contiguous crystallinity at their top.

6. p+/n+ nc−Si and Cr S/D patterning

7. 50 nm i nc−Si channel layer deposition followed by gate dielectric deposition

3. SiO2 and p+ nc−Si patterning to open n+ nc-Si deposition region

8. contact hole opening

4. 60 nm n+ nc-Si deposition at 150°C

9. 200 nm Al evaporation

PMOS 5. n+ nc−Si region patterning

Fig. 1 340

NMOS

10. Al gate source/drain contact opening

Fabrication sequence for integrated nc-Si:H p- and n-channel TFTs with staggered top-gate, bottom-source/drain geometry IEE Proc.-Circuits Devices Syst., Vol. 150, No. 4, August 2003

With the high hydrogen dilution ratio of R ¼ [H2]/ [SiH4+SiCl2H2] ¼ 30, we obtain two weak bands in the ultraviolet reflectance at l ¼ 276 nm and 365 nm for B200nm-thick intrinsic nc-Si:H films on glass substrates, shown in Fig. 2, which indicate that the film becomes nanocrystalline at a substrate temperature as low as 1001C.

(a)

ultraviolet reflectance, a.u.

0.7

150°C

0.6

0.5

100°C

0.4

200

250

300

350

400

450

(b)

wavelength, nm

Fig. 2 Ultraviolet reflectance of B200-nm thick intrinsic nc-Si:H films deposited by PECVD at hydrogen dilution ratio R ¼ [H2]/ [SiH4+SiCl2H2] ¼ 30 at substrate temperatures of 1501C and 1001C

Because the evolution of the nc-Si:H structure depends strongly on the substrate [23–25], we introduced the seed layer to develop the crystallinity of the channel layer for the staggered top gate, bottom source/drain geometry. We have gradually reduced the seed layer thickness from initially 230 nm down to 50 nm–75 nm in recent experiments. We use a slightly smaller H2 dilution ratio for seed layer deposition than for channel layer deposition. The ultraviolet reflectance spectrum shows that the channel layer is crystalline on top of both the nc-Si:H seed layer and the doped layers on Cr. We inspected the nc-Si:H channel layer on top of the seed layer by scanning electron microscopy. Figure 3 shows that the isolated crystal clusters of the seed layer have coalesced to a continuous crystalline layer of clusters with diameter of B50 nm.

Fig. 3 Scanning electron micrographs of 75-nm thick intrinsic ncSi:H seed layer deposited on a glass substrate, and the 50-nm thick intrinsic nc-Si:H channel layer deposited on top of the seed layer a 75 nm seed layer b 50 nm channel layer Note that in b the crystal clusters have coalesced to a fully-developed, contiguous crystalline channel layer

3.2 Fabrication issues for TFTs on plastic substrates Fabricating devices on plastic substrates raises several issues. It is essential that the substrate satisfies high thermal and chemical stability, high glass transition temperature, low coefficients of thermal and humidity expansion, low permeability by water and oxygen, low shrinkage during circuit fabrication to reduce misalignment in photolithography, low surface roughness and good film adhesion. Encapsulating the substrates may further (i) enhance its resistance to chemicals and reduce degassing during processing, (ii) modify the surface roughness and (iii) improve adhesion [2, 3]. Pre-shrinking the substrates by heating to their maximum allowable process temperature for a few hours before processing reduces shrinkage during later thermal processing. In our standard fabrication procedure, Kapton E is first degassed in the deposition chamber for 1 h at the deposition temperature of 1501C, and then encapsulated with PECVD SiNx:H on both faces. IEE Proc.-Circuits Devices Syst., Vol. 150, No. 4, August 2003

Another important issue is thermal expansion mismatch, which induces significant thermal stress through each heating and cooling cycle, and may lead to cracking and delamination of the thin films, or curling of the sample. In our 1501C process, sample curling is a major challenge. The stress inside the SiNx:H film tends to be tensile when deposition power is low and compressive when deposition power is high [26]. Our intrinsic nc-Si:H film and the gate SiO2 are under compression, while Cr and doped nc-Si:H are under tension as deposited. By adjusting the deposition power of the SiNx:H encapsulating layers, the samples with the stack of device films can be made flat, to reduce difficulties with lithography. Cr serves not only as the bottom contact metal, but also as the etch-stop layer in our TFT fabrication. But because it is brittle and under tension as deposited, it cracks easily on a compliant substrates. By lowering the thermal evaporation 341

VDS = 10 V

5 4

*

S lin = 0.226

3 2 1 0

20 30 gate voltage, V a

40

50 40 30 20 10 0 0

Fig. 4

10

saturation mobility, cm2 V−1 s−1

linear mobility, cm2 V−1 s−1

0

source-drain current1/2, 10−3 A1/2

source-drain current, 10−4A

6

10

20 30 gate voltage, V c

40

25

VDS = 10 V 20 15 10

Ssat = 9.1×10−4 *

5 0 0

10

20 30 gate voltage, V b

40

0

10

20 30 gate voltage, V d

40

50 40 30 20 10 0

Extraction of mobility values

a Transfer characteristic with manually fitted S*lin b Square root of transfer characteristic with manually fitted S*sat c Linear mobilities d Saturation mobilities Values for an n-channel TFT at VDS ¼ 10 V are determined from moving five-point averages c and d are obtained from the differential slopes of a and b

rate of Cr, the tensile stress in the as-deposited Cr film reduces. This tensile stress can be lowered by replacing the single Cr layer with a bi-layer composed of a ductile metal covered with a thin Cr layer [27].

3.3

TFT characteristics

The TFT characteristics are evaluated with an HP 4155A parameter analyser. At VDS ¼ 0.1 V in n-channel TFTs and VDS ¼ 1 V in p-channel TFTs the gate leakage current is comparable to the source-drain current; therefore, we use the transfer characteristic at VDS ¼ 10 V to evaluate the field effect mobility. We extract the linear and saturation mobilities using conventional MOSFET theory, as 1 2 1 1 mlin ¼ SlinLW1 e1 ox toxVDS and msat ¼ 2SsatLW eox tox, where Slin is the slope of the source-drain current against gate voltage, Ssat is the slope of the square root of the source-drain current against gate voltage, and L, W, eox, tox denote the channel length, channel width, oxide dielectric constant and oxide thickness. Because of the high gate leakage current and of charge trapping in the dielectric, the transfer characteristics are not ideal in the linear region nor in the saturation region. We use two procedures to extract mobility values. They are illustrated in Fig. 4. Figures 4a, b show manual fits of S*lin and S*sat to ISD (linear plot) and I1/2 SD (saturated plot) from which a single value for mlin or msat is determined. The mobility values of Figs. 4c, d were determined from moving average slopes taken over five points. The following mobility values are determined by manual fits of S*lin. In our early research on separate p-channel and nchannel TFTs made on glass substrates, we obtained a hole mobility of B0.2 cm2 V1 s1 and an electron mobility of B40 cm2 V1 s1 at a maximum process temperature of 1501C [28]. Now we have integrated the TFTs together on single glass or Kapton substrates, using the process 342

parameters obtained before. The transfer characteristics of the p-channel portion and the n-channel portion are shown in Fig. 5 for glass substrate and Fig. 6 for Kapton substrate. The hole mobilities in the p-channel are mhB0.2 cm2 V1 s1 on glass and mhB0.17 cm2 V1 s1 on Kapton, and the electron mobilities in the n-channel are meB30 cm2 V1 s1 on glass and meB23 cm2 V1 s1 on Kapton. We observe slightly lower mobilities and higher gate leakage currents in devices on Kapton than on glass. While the value of the hole mobility is adequate for onpixel CMOS in combination with a-Si:H NMOS, it is too low for off-pixel, fully nc-Si:H CMOS. We believe that the value of 0.2 cm2 V1 s1 reflects contact resistance rather than intrinsic hole mobility [29]. Indeed, a hole mobility of 2 cm2 V1 s1 has been determined from a contact-free measurement [30]. While the carrier mobilities lie close to values required for CMOS, high gate leakage currents, high threshold voltages and shifts in the TFT characteristics indicate that the gate dielectric and the channel layer/ dielectric interfacial properties need improvement. We use SiO2 instead of SiNx as the gate dielectric because it produces a less defective interface in nanocrystalline silicon field-effect devices [31, 32]. However, when SiO2 is deposited at ultra-low temperature, 1501C in this case, it contains excessive hydrogen, B3  1020 atoms/cm3, is electrically unstable and at times even porous. The porosity produces leakage current, and the electrical instability is manifest in charge trapping. By drawing channel current away, the high gate leakage current results in non-ideal turn-on in the transfer characteristics, especially in the p-channel with its relatively low current. Therefore, the 1501C devices are not yet ready for CMOS operation. The gate leakage current at small gate-source voltage, VGSo20, is reduced by annealing the sample in nitrogen at 1501C for 1 h, and then in oxygen at 1501C for another IEE Proc.-Circuits Devices Syst., Vol. 150, No. 4, August 2003

10−4

VDS = −10 V

10−6

10−8

source-drain and gate leakage current, A

source-drain and gate leakage current, A

10−4

VDS = −1 V

10−10

10−12 −40

−30

−20

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0

VDS = −10 V

10−6

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VDS = −1 V

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10−12 −40

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a

a

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source-drain and gate leakage current, A

source-drain and gate leakage current, A

−10

gate voltage, V

gate voltage, V

VDS = 10 V VDS = 0.1 V

10−5

10−7

10−9

10−3 VDS = 10 V 10−5

VDS = 0.1 V

10−7

10−9

10−11

10−11 0

gate voltage, V

20 gate voltage, V

b

b

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20

30

0

40

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30

40

Fig. 5 Transfer characteristics of a p-channel TFT portion and an n-channel TFT portion of nc-Si:H fabricated in a staggered top-gate, bottom source/drain geometry at 1501C and integrated monolithically on glass

Fig. 6 Transfer characteristics of a p-channel TFT portion and an n-channel TFT portion of nc-Si:H fabricated in a staggered top-gate, bottom source/drain geometry at 1501C and integrated monolithically on Kapton

The triangles denote the gate leakage current W ¼ 200 mm; L ¼ 30 mm a p-channel b n-channel

The triangles denote the gate leakage current W ¼ 200 mm, L ¼ 30 mm a p-channel b n-channel

hour, right after oxide deposition. However, no obvious change is observed at large VGS. We have not yet found a good procedure for post-fabrication annealing at 1501C.

5

4

Summary

Nc-Si:H directly deposited and processed at 1501C is capable of both p-channel and n-channel operation. An inverted staggered top-gate bottom-source/drain geometry ensures that the channel lies in the last-to-grow layer, and avoids plasma etch damage to the channel. A 50-nm-thick intrinsic nc-Si:H seed layer serves to evolve the crystalline structure of the channel layer. Mobilities close to those required for CMOS operation are obtained. The quality of the SiO2 gate dielectric deposited at 1501C is inadequate for CMOS operation. The channel/dielectric interface and ptype doped source/drain layer also need to be improved. Finally, we need a post-fabrication anneal procedure that does not exceed the TFT process temperature. Our overall conclusion is that we have brought 1501C nc-Si:H to device readiness. Now is the time to begin working on the ancillary materials: the gate dielectric and its interface with the channel, and also the doped layers. IEE Proc.-Circuits Devices Syst., Vol. 150, No. 4, August 2003

Acknowledgments

The authors thank Dr. Punchaipetch, Dr. Pant and Prof. Gnade of the University of North Texas for suggesting the post-deposition annealing procedure. They gratefully acknowledge early support from DARPA’s HDS Program, and current support from the New Jersey Commission on Science and Technology, and the Princeton Plasma Physics Lab under a PPST Fellowship. 6

References

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IEE Proc.-Circuits Devices Syst., Vol. 150, No. 4, August 2003

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