nanowire-fets

PERFORMANCE ANALYSIS OF GATE-ALL-AROUND JUNCTIONLESS 𝑰𝒏𝒙 𝑮𝒂𝟏−𝒙 𝑨𝒔 NANOWIRE-FETS: A QUANTUM MECHANICAL STUDY Submitted By:

Md. Rakesh Iqbal Student ID. EEE120300235

SM Nahian Student ID. EEE 130200309

Supervised By:

Ashraful Arefin Assistant Professor Department of Electrical and Electronic Engineering Northern University Bangladesh

Bachelor of Science in Electrical and Electronic Engineering Northern University Bangladesh

September 2016

Declaration of Authorship It is hereby declared that this thesis ‘‘Performance Analysis of Gate-All-Around Junctionless 𝑰𝒏𝒙 𝑮𝒂𝟏−𝒙 𝑨𝒔 Nanowire-FETs: A Quantum Mechanical Study’’ or any part of it has not been submitted to any other Institute or University for the award of any degree of diploma.

Signature of Candidates:

___________________ Md. Rakesh Iqbal Student ID. EEE120300235

___________________ SM Nahian Student ID. EEE130200309

i

Certification This is to certify that the thesis titled ‘‘Performance Analysis of Gate-All-Around Junctionless 𝑰𝒏𝒙 𝑮𝒂𝟏−𝒙 𝑨𝒔 Nanowire-FETs: A Quantum Mechanical Study’’ submitted to the Northern University Bangladesh by Md. Rakesh Iqbal, EEE120300235, and SM Nahian, EEE130200309, for the award of the degree of Bachelor of Science in Electrical and Electronic Engineering, is a bona fide record of the thesis work under the supervision of Ashraful Arefin, Assistant Professor of the Department of Electrical and Electronic Engineering, NUB on, September 2016.

Board of Examiners ______________________________ Ashraful Arefin Assistant Professor Department of Electrical and Electronic Engineering Northern University Bangladesh ______________________________ A.S.M. Shamsul Arefin Assistant Professor Department of Electrical and Electronic Engineering Northern University Bangladesh ______________________________ Mohammad Shafiul Alam Senior Lecturer Department of Electrical and Electronic Engineering Northern University Bangladesh

______________________________ Dr. Moinul Bhuiyan Associate Professor & Head Department of Electrical and Electronic Engineering Northern University Bangladesh

ii

Abstract Enormous Research efforts have been dedicated to the development of unconventional device structures in pursuit of addressing the requirements of future generation nanoscale devices. Nanowire FETs appear to be a superior alternative to replace the conventional bulk MOSFETs as well as FinFET to continue scaling down to a 10 nm feature size. Scaling MOSFETs beyond 10 nm gate lengths is extremely challenging using planar device architecture due to the stringent criteria required for the transistor switching. Gate-allaround architecture with a junctionless InGaAs nanowire channel is a promising candidate for future technology generations. The gate-all-around geometry enhances the electrostatic control and hence gate length scalability. In addition, it enables the use of an undoped channel, which has the potential to minimize threshold voltage variation due to reduced random dopant fluctuations. A well-established technique of incorporating the QM effect is the self-consistent method where Schrödinger and Poisson’s equation are solved initiatively is used in this work. Here, a simulator which is working by numerical method called the Fast Uncoupled Mode Space (FUMS) approach is used. With this method threshold voltage, sub-threshold swing slope and ON/OFF current ratio for various stress of 𝐼𝑛𝐺𝑎𝐴𝑠 have been determined. For all three above mention cases the best form achieved is 𝐼𝑛0.57 𝐺𝑎0.43 𝐴𝑠.

iii

Acknowledgements

First of all, we want express our gratitude to almighty Allah. We are grateful to our parents and family members for their patience, love and endless prayers. Without their prayers, this work would never have come into existence. We like to convey our cordial gratitude to Md. Saber Nazim, Lecturer of the Department of Electrical and Electronic Engineering, NUB, for supervising our thesis from the very beginning, showing us the path and guiding us through solid state theory as well as quantum mechanics and quantum transport. As a true enlightener, without his active help participation throughout the whole research work, this work would never have been possible. We are greatly indebted to Ashraful Arefin, Assistant Professor of the Department of Electrical and Electronic Engineering, NUB, for his support and inspiration during the absence of our thesis supervisor for higher study. We specially thank Dr. Moinul Bhuiyan, Associate Professor and Head of the Department of Electrical and Electronic Engineering, NUB, A.S.M. Shamsul Arefin, Assistant Professor of the Department of Electrical and Electronic Engineering, NUB, Mohammad Shafiul Alam, Senior Lecturer of the Department of Electrical and Electronic Engineering, NUB, Md. Abidur Rahman, Lecturer of the Department of Electrical and Electronic Engineering, NUB and Sarah Nahar Chowdhury, Lecturer of the Department of Electrical and Electronic Engineering, NUB for their guidance in making this thesis successfully.

Authors September 2016

iv

Contents Declaration of Authorship ............................................................................................... i Certification ..................................................................................................................... ii Abstract ........................................................................................................................... iii Acknowledgements ........................................................................................................ iv Contents ........................................................................................................................... v List of Figures .................................................................................................... vii List of Tables .................................................................................................... viii Abbreviations ................................................................................................................. ix

1

2

Introduction 1.1

Preface ..................................................................................... 1

1.2

Literature Review ....................................................................... 3

1.3

Objective .................................................................................. 6

1.4

Organization of the Thesis ........................................................... 7

Surrounding Gate Devices: A structural Perspective 2.1

A Short History of Multiple Gate Devices ....................................... 8

2.2

Advantages of Surrounding Gate NWTs ........................................ 11

2.3

Gate All Around Devices ............................................................ 11

2.4

Junctionless Transistor ............................................................... 12

2.5

Performance Scaling .................................................................. 13

2.6

2.5.1

Subthreshold Leakage Currents .......................................... 14

2.5.2

Time Dependent Dielectric Breakdown ............................... 14

2.5.3

Hot Electron Effects ........................................................ 14

2.5.4

Short Channel Effects ...................................................... 15

Major Quantum Phenomena in Nano devices .................................. 15 v

3

4

5

Simulator Design 3.1

Simulated Devices ..................................................................... 17

3.2

Self-Consistent Analysis ............................................................. 20 3.2.1

Poisson’s Equation .......................................................... 20

3.2.2

Effective Mass Consideration ............................................ 21

3.2.3

Schrödinger’s Equation .................................................... 22

3.2.4

Transport Calculation ....................................................... 23

3.3

Ballistic Current Calculation ........................................................ 25

3.4

Threshold Voltage Calculation ..................................................... 27

3.5

Sub-threshold Swing Slope Calculation ......................................... 28

3.6

On/Off Current Ratio Calculation ................................................. 28

3.7

Implementation of the Simulator .................................................. 28

Results and Discussion 4.1

Solver Benchmarking ................................................................. 31

4.2

Charge Concentration ................................................................. 31

4.3

Threshold Voltage Variation Due to Change of Stress ...................... 32

4.4

SS Slope Variation Due to Change of Stress ................................... 33

4.5

ON/OFF Current Ratio Variation Due to Change of Stress ................ 34

4.6

Results Summary ...................................................................... 35

Conclusion 5.1

Summary ................................................................................. 36

5.2

Future Prospects ........................................................................ 36

Appendix A

Flow Chart For FUMS Approach ........................................... 38

References ...................................................................................................................... 39

vi

List of Figures FIGURE 1.1: Transistors in Intel microprocessors compared to that projected by Moore’s Law. ................................................................................................................. 2 FIGURE 2.1: A short history of different devices. ....................................................... 10 FIGURE 2.2: A 3D structure of common Gate-All-Around (GAA) MOSFET. .......... 12 FIGURE 2.3: 1st Junctionless transistor by Tyndall National Institute, Ireland in 2010. ..................................................................................................................................... 13 FIGURE 3.1: Cross section of the cylindrical gate all around device under our study. ..................................................................................................................................... 18 FIGURE 3.2: The conversion from a cylindrical gate all around device into an omega gate device if 𝑎 arises. ................................................................................................. 18 FIGURE 3.3: The conversion from a cylindrical gate all around device into an omega gate device. The substrate has overlapped a portion denoted cut from the radius. This incidentally, makes the omega parameter, a of the device equal to cut/r. .................. 19 FIGURE 3.4: Flow chart for iterative procedure for calculating N and U self consistently. ................................................................................................................. 27 FIGURE 4.1: Stress vs Threshold voltage. ................................................................... 32 FIGURE 4.2: Stress vs Subthreshold Swing Slope....................................................... 33 FIGURE 4.3: Stress vs ION/IOFF current ratio. ............................................................... 34 FIGURE A.1: Flow chart for simulator design in the Fast Uncoupled Mode Space approach. ...................................................................................................................... 38

vii

List of Tables Table 4.1: Simulation data for stress vs. threshold voltage…………...………… 32 Table 4.2: Simulation data for stress vs. sub-threshold swing slope ……...……. 33 Table 4.3: Simulation data for stress vs. ON/OFF current ratio……...…….…… 34

viii

Abbreviations ITRS

International Technology Roadmap for Semiconductor

MOSFET

Metal Oxide Semiconductor Field Effect Transistor

GAA

Gate All Around

SG

Surrounding Gate

NWT

Nano Wire Transistor

SNWT

Silicon Nano Wire Transistor

SCE

Short Channel Effects

SOI

Silicon On Insulator

DG

Double Gate

TG

Tri-Gate

DIBL

Drain Induced Barrier Lowering

SS

Subthreshold Swing

TSNWFET

Twin-Silicon Nano Wire Field Effect Transistor

EI

Electrostatic Integrity

OSG

Omega Shaped Gate

MuGFET

Multiple Gate Field Effect Transistor

FEM

Finite Element Method

PDE

Partial Differential Equation

CMS

Coupled Mode Space

UMS

Uncoupled Mode Space

FUMS

Fast Uncoupled Mode Space

EME

Effective Mass Equation

NEGF

Non Equilibrium Green’s Function

LDOS

Local Density of State

ix

Chapter 1

Introduction

1.1

Preface

The basic concept of the field effect transistor (FET) was first patented by Lilienfeld in 1930 [1]. But it took another thirty years to finally introduce it into practice in 𝑆𝑖 − 𝑆𝑖𝑂2 in 1960 by Kahng and Atalla [2]. By the year 1963, Frank Wanlass put the MOSFETs in complementary metal oxide semiconductor or CMOS [3] circuitry that quickly grew into an entire industry. The CMOS technology has been proven as one of the most important achievements in modern engineering history. CMOS also allows a high density of logic functions on a chip that allowed the CMOS technology to become an integral part of the Vary Large Scale Integration or VLSI. The steadfast compliance to Moore’s Law can largely be attributed to Scaling of MOS devices to smaller and smaller device dimensions. The scaling of devices goes on unrelentingly down from a gate length 1 µm to as small as current 22 nm. It is projected by International Technology Roadmap for Semiconductor (ITRS) as of 2016, 10 nm devices are still under commercial development. Commercial release is expected to commence in 2017 by Intel [4]. However such a rigorous scaling discloses the limitations of conventional bulk MOSFETs. As the transistor dimensions are shrunk, the proximity between the source and the drain reduces the ability of the gate electrode to control the potential distribution. As the scaling continues, the MOSFETs become fraught with such desirable effects, known as the short-channel effects (SCEs) [5]. The shortened gate length allows the drain to compete with the gate electrode for the control of the channel potential resulting SCEs like drain-induced barrier lowering and punch through, surface scattering, velocity saturation, impact ionization and hot electrons. In fact for all practical purposes, it appeared to be impossible to scale classical bulk MOSFETs below 20 nm [6].

1

FIGURE 1.1: Transistors in Intel microprocessors compared to that projected by Moore’s Law.

Many reviews have been written about the current state and future prospects for Si MOSFETs and CMOSs [7-10]. In order to scale devices down to 10 nm regime as well as to suppress the short channel effects numerous novel device structures and materials have been proposed. Towards the end of 1990s the Silicon-On-Insulator or the SOI devices became popular. SOI technology devices offer the advantages of reducing parasitic capacitances and enhanced current drive and thus brings about improvements in both circuit speed and power consumption. However, inability of the transistor to turn off the channel still remained an inadequacy of shortened channel devices. To tackle such problems the concept of multiple gate SOI devices such as double-gate (DG), delta-gate, DG or TG FinFET, pi-gate, omega-gate and gate all around (GAA) SOI MOSFETs were brought about. These “unconventional” devices provide higher current drive per unit area than conventional MOSFET devices and offer optimal short-channel effects [11]. In order to further suppress the SCEs, more promising structure known as the FinFETs were proposed, fabrication and demonstrated their fascinating characteristics [12, 13]. The term 2

FinFET was first coined in the year 1999 when the researchers in University of California, Berkeley fabricated a sub-50 nm self-aligned, DG pMOSFET using conventional planar MOSFET technology [14]. However these devices cannot be directly fabricated with advanced fabrication process and inherently encountered several difficulties [15-17]. Considering the issues of mass production, gate all around FinFET structures [12, 13] have been proposed to make a compromise between device performance and manufacturability. Soon afterwards, the nanowire transistors emerged with promising theoretical and practical aspects. These devices can be seen as the ultimate integration of the innovative nanodevices and is one of the candidates which have gained significant attention from both the device and circuit developers because of its potential for building highly dense and high performance electronic circuits. Recent advances in nanoscale fabrication techniques have shown that semiconductor nanowires may become the candidate for next generation technologies. Si and Ge nanowire transistors are also important because of their compatibility with the CMOS technology. The silicon nanowires FinFETs have attracted considerable attention due to their proven robustness against Short-Channel Effect (SCE) and relatively simple fabrication.

1.2

Literature Review

Hisamoto et al., in the year 1998 successfully demonstrated a quasi-planar folded channel transistor with gate scale length scaled down to 20 nm [18] all thought the term FinFET was at first put to use in the year 1999 [14]. A year later in 2000, Hisamoto et al. reported the successful fabrication of 17 nm gate length FinFET [19]. Two years later in 2002, a DG CMOS FinFET was fabricated with the smallest gate length of 10 nm along a silicon fin or film thickness of 12 nm [20].All of the devices have attracted increasing interest for their integrated process not seen so far in conventionalplanar bulk devices, and with the potential advantages of higher drive current, better short-channel effect control, and/or less Drain Induced Barrier Lowering (DIBL). However it was quickly realized that in order to obtain better transistor gate control over the channel potential when transistor structure goes from UTB-SOI to double-gate FinFET, triple-gate MOSFET, Pi(π)-gate MOSFET, to the gateall-around (GAA) or surrounding-gate (SG) MOSFET. The gate-all-around structure offers the best gate control over the channel; however it suffers from process complexity [15-17].

3

The nanowire transistor (NWT) is a promising device structure for future integrated circuits. In addition to experimental exploration of nanoscale devices, physics based simulation for such devices can offer valuable insight into their operation and can help their design optimization. Numerical simulation proves to be valuable guide for conducting experimentation as well as to explain their results. It is also powerful tool for identifying the strength and weaknesses of different approaches in the emerging field of nanoelectronics. An important consideration for the nanoscale devices is the incorporation of the quantum mechanical effects, a consideration too eminent to be avoided in these devices [21, 22]. Massimo V. Fischetti et al. [23] theoretically (by employing local empirical pseudo potentials) showed that for ultra-thin 𝑆𝑖 and 𝐼𝑛𝐴𝑠 bodies, the leakage current in the gate reaches worrisome values for gate lengths of 5 nm. They also made suggestions that to continue the scaling down the 5 nm node one dimensional channels (nanowire), especially channels based on intrinsically 2D (e.g. graphene/graphane or transition-metal dichalcogenides) or 1D (e.g. carbon nanotubes) structure are required. The quantum mechanical effects in MOS inversion layers (carrier penetration in oxide) arise due to high surface electric field makes the quantum well for inversion carriers very steep and narrow which results in the quantization of electron energies in the direction normal to the interface. A significant amount of study has been carried out to realize and model theses effects in MOS device. A well-established method to explore such phenomenon is the selfconsistent method. In the self-consistent analysis scheme, the Schrödinger’s equation quantum mechanically computes the electron density and their transmission probability for a given potential profile. Poisson’s equation, on the other hand, checks whether the charge profile is consistent with the potential profile. Stern was the pioneer to formulate the detail of self-consistent modeling for 𝑛-type silicon inversion layer [24], where coupled one dimensional Schrödinger’s and Poisson’s equations were solved relatively to explore the importance of QM effects on inversion layer parameters in conventional bulk MOSFET. In that calculation, the author made several approximations, e. g. effective mass approximation instead of periodic lattice potential, the wave function vanishing at the 𝑆𝑖 − 𝑆𝑖𝑂2 interface and the potential wellbeing triangular. For triangular potential well, the solution of Schrödinger’s equation is the Airy function which Stern used in his self-consistent formulation. In that work, he presented numerical results for different surface orientation, temperature and inversion layer concentrations to understand the importance of QM effects on inversion layer parameters such as the average penetration of inversion layer charge 4

density from the surface and distribution of carries among the sub-bands. He also calculated gate capacitance and found that the self-consistently calculated values agree with the experimental data. In 2006, J. P. Colinge et al. employed the self consistent Poisson – Schrödinger solver for current calculation in the triple gate (TG) variant of 𝑛-channel FinFET [25] using computational tool MATLAB [26] and finite element analysis and solver software package COMSOL Multiphysics [27]. Reduction of Si fin width from 20 𝑛𝑚 × 20 𝑛𝑚 to 2 𝑛𝑚 × 2 𝑛𝑚 dimension showed the threshold voltage to be higher than as predicted by classical Poisson solver because of the increased QM effects. He also demonstrated that the current drive was belittled and the subthreshold swing slope (SS) was degraded in devices with small cross sections. To deeply understand device physics of junctionless gate-all-around (GAA) nanowire transistors and to assess their ultimate performance limits, a 3D quantum simulator is needed. Thus it’s quite impossible to fabricate a junctionless 𝐼𝑛𝐺𝑎𝐴𝑠 gate-all-around nanowire transistor in Bangladesh, so we aim to simulate the vary device to understand its performances. Integrated circuits based on InGaAs transistors are widely used in many RF devices for electronics, defense and space communication systems [28]. Currently, 𝐼𝑛𝐺𝑎𝐴𝑠 ICs are also being studied for new millimeter wave devices for collision avoidance and terahertz (THz) applications. Due to scaling limitations faced by 𝑆𝑖 CMOS, 𝐼𝑛𝐺𝑎𝐴𝑠channel MOSFETs have emerged as a potential alternative. These new domains of research are generating new prospects for 𝐼𝑛𝐺𝑎𝐴𝑠 FETs to be used for future THz and post- CMOS applications. 𝐼𝑛𝑥 𝐺𝑎1−𝑥 𝐴𝑠 is a ternary III-V semiconductor that can be regarded as an alloy of 𝐺𝑎𝐴𝑠 and 𝐼𝑛𝐴𝑠 systems. As the In composition varies from 0% to 100%, the optical and electronic properties vary strongly. The electron mobility of 𝐼𝑛𝐺𝑎𝐴𝑠 varies from 6000 to 30000 cm2 /V. s depending on the composition. The high 𝐼𝑛 content 𝐼𝑛𝑥 𝐺𝑎1−𝑥 𝐴𝑠 layers allow the device to operate at very high frequencies. Furthermore, 𝐼𝑛𝑥 𝐺𝑎1−𝑥 𝐴𝑠 based quantum well FET and MOSFET have demonstrated excellent characteristics for low-power, high-speed logic applications. Due to higher mobility than 𝑆𝑖, 𝐼𝑛𝑥 𝐺𝑎1−𝑥 𝐴𝑠-based devices can operate in the THz regime with unparalleled performance. For example, an 𝐼𝑛𝐴𝑠 HEMT with 𝐼𝑛0.65 𝐺𝑎0.35 𝐴𝑠 subchannels has delivered record-high 𝑓𝑇 (current-gain cut-off frequency) beyond 700 GHz and 5

devices capable of 𝑓𝑇 = 1 THz are currently being examined. Additional progress in device technology is necessary to further improve the device operating frequency. In HEMT devices, the barrier separating the channel from the gate also separates the contacts from gate, contributing to contact resistance. By using dielectric materials and slightly modifying the design, Ohmic contacts can be realized. The hurdle to date is mainly due to difficulty in scaling the barrier thickness while maintaining the carrier mobility. In the past few years, the prospect of 𝐼𝑛𝐺𝑎𝐴𝑠 MOSFETs has attracted the attention of researchers for logic circuit applications. This also coincides with 𝑆𝑖 scaling path based on Moore's law. With a correct combination of channel composition design and proper oxide deposition, 𝐼𝑛𝐺𝑎𝐴𝑠 MOSFETs can deliver outstanding logic performance. The 𝐼𝑛𝐺𝑎𝐴𝑠 MOSFETs fabricated using ALD-deposited aluminum and hafnium oxides can achieve a very low interface state density in the 𝐴𝑙2 𝑂3/𝐼𝑛𝐺𝑎𝐴𝑠 MOS structure. This reveals that low interface state density in the conduction band can be achieved for a 𝑛 −channel device. Excellent results have been demonstrated with high-permittivity dielectrics deposited by ALD on 𝐼𝑛𝐴𝑠- rich 𝐼𝑛𝐺𝑎𝐴𝑠. High-performance deep-submicron inversion-mode 𝐼𝑛𝐺𝑎𝐴𝑠 MOSFETs with record 𝑔𝑀 exceeding 1.1 mS/μm have been reported. 𝐻𝐵𝑟 pre-cleaning, retrograde structure and halo implantation processes have been used for III-V MOSFETs to steadily improve high/𝐼𝑛𝐺𝑎𝐴𝑠 interface quality and on/off current ratio. Much more work on high-/InGaAs interface and 𝐼𝑛𝐺𝑎𝐴𝑠 ultra-shallow junctions is being carried out to make III-V a viable alternative technology at the 15 nm CMOS technology nodes. Overall, from the present experimental results, 𝐼𝑛𝐺𝑎𝐴𝑠 based devices looks very promising for THz and post-CMOS applications.

1.3

Objective

Nano device simulation is very important and necessary today as it helps us better understand the devices and model them accordingly. This is even more significant for the novel device structures as well as testing novel materials. The urge to assess the device performance before the device enters full scale production line is the underlying force that motivates to gain more insight into the device. The only way to gain such insight is by numerical simulations with the aid of various simulation tools or solver packages. As 6

mentioned before, a number of simulation works have already been carried out on surrounding gate (SG) and junctionless (JL) devices. However, to the best of our knowledge, the following issue of those two devices are yet to be covered: 

A self-consistent analysis of the Junctionless Surrounding Gate (JLSG) devices has not been covered yet. There are several articles on Silicon Junctionless or Surrounding Gate transistors individually. But, none of them tried with InGaAs.



A more generalized and simplistic view of Junctionless devices performance from the point of surrounding gate devices.



The changes in the threshold voltage due to changes in the device geometry from cylindrical all around device to Junctionless device.

Based on these facts, the following issues are covered in this work:  Simulation of a Surrounding Gate (SG) junctionless device.  Study the threshold voltage variation with varying ‘𝑥’composition of 𝐼𝑛𝑥 𝐺𝑎1−𝑥 𝐴𝑠.  Study of Sub threshold swing slop with varying ‘𝑥’using the simulator.  Study of 𝐼𝑂𝑁 /𝐼𝑂𝐹𝐹 current with varying ‘𝑥’ using the simulator.

1.4

Organization of This Thesis

Illustration description of the evolution and structure of NWT is presented in Chapter 2. Chapter 3 provides the theory behind the work and detailed simulation technique. The simulated results and corresponding discussions are given in chapter 4. Finally concluding remarks and suggestions for future works are presented in chapter 5.

7

Chapter 2

Surrounding Gate Devices: A Structural Perspective

Surrounding gate devices are structures where the whole semiconductor region is surrounded by the gate oxide. With the passage of time, Silicon on Insulator (SOI) MOS transistors have evolved from conventional, planar single-gate devices into three dimensional, unconventional devices with a multi-gate structure due to the requirement of increased current drive capability and better control of short channel effect (SCE) [5, 6]. Such multiple-gate devices include double gate and triple gate structures such as quantum wire [29], the FinFET and two channel SOI MOSFET [30] and quadruple-gate devices such as gate all around (GAA) Device [31], the DELTA transistor [32], Omega MOSFETs [33], Pi-gate SOI MOSFETs [34]. Surrounding gate devices have a single gate surrounding the whole semiconductor region.

2.1

A Short History of Multiple Gate Devices

The first article on the double-gate MOS (DGMOS) transistor was published by T. Sekigawa and Y. Hayashi in the year 1984 [35]. That paper showed that one can obtain significant reduction of short-channel effects by sandwiching a fully depleted SOI device between two gate electrodes connected together. The device was called XMOS because its cross section looks like the Greek letter χ. Using this configuration in 1993, a better control of the channel depletion region is obtained in a “regular” SOI MOSFET and in particular, the influence of the drain electric field on the channel is reduced, which reduces short channel effect [36]. The first fabricated double-gate SOI MOSFET was the “fully depleted Lean-channel transistor (DELTA, 1989)”, where the device is made in a tall and narrow silicon island called “finger”, “leg” or “fin”.

8

The FinFET structure is similar to DELTA, except for the presence of a dielectric layer called the “hard mask” on top of the silicon fin. The hard mask is used to prevent the formation of parasitic inversion channels at the top corners of the devices. Other implementations of vertical-channel, double-gate SOI MOSFETs include the “Gate-AllAround” (GAA), which is a planar MOSFET with the gate electrode wrapped around the channel region, the Silicon-on-Nothing MOSFET, the Multi-Fin XMOS (MFXMOS), the triangular-wire SOI MOSFET and the delta channel SOI MOSFET. The triple-gate MOSFET is a thin-film, narrow silicon with a gate on three of its sides and development first in the year 1993 [37]. Some further implementations were included in the year 1999 which resulted in the quantum-wire SOI MOSFET [38] and the tri-gate MOSFET. In the year 2001, another research showed that the Electrostatic Integrity of triple-gate MOSFETs can be improved by extending the sidewall portions of the gate electrodes to some depth in the buried oxide and underneath the channel region (pi-gate device and omega gate device) [33]. From an electrostatic point of view, the pi-gate and omega gate MOSFETs have an effective number of gates between three and four. The use of sustained silicon, a metal gate and/ or high-k dielectric as gate insulator can further enhance the current drive of the device [39]. The structure that theoretically offers the best possible control of the channel region by the gate, and hence the best possible Electrostatic Integrity is the surrounding-gate nanowire transistor or NWT. The first surrounding-gate NWTs were fabricated in 2005 by wrapping a gate electrode around a vertical pillar. Such devices include the CYNTHIA device (circular-section device) [40]. And the pillar surrounding-gate MOSFET (square-section devices) [41]. More recently, planar surrounding-gate devices with square or circular cross section have been reported [42]. Surrounding-gate MOSFETs with a gate length as small as 5 nm have shown to be fully functional [43]. To increase the current drive per unit area, multiple surrounding-gate channels can be stacked on top of one another, while sharing common gate, source and drain. Such devices are called the Multi-Bridge Channel MOSFET (MBCFET) [44], the twin-silicon-nanowire MOSFET (TSNWFET) [45], or the Nano-Beam Channel GAA MOSFETs [46].

9

10

FIGURE 2.1: A short history of different devices.

2.2

Advantages of Surrounding Gate NWTs

Short-channel effects arise when control of the channel region by the gate is affected by electric field lines from source to drain. Surrounding-gate devices have a better control over channel. There is a parameter called the “Electrostatic Integrity” (EI) that can be related to the DrainInduced Barrier Lowering (DIBL) and the threshold voltage roll-off Short-Channel Effect (SCE), and which describes how well the gate controls the actions, the minimum gate length that can be used with the different technologies has been calculated and surrounding gate devices show an improved performance [47]. Surrounding-gate devices also have a high current drive capability.

2.3

Gate-All-Around Devices

Gate-all-around (GAA) MOSFET is one of the most promising multi-gate structures to extend the scaling of the CMOS devices as it provides the best channel electrostatic control, which improves further with the shrinking of channel thickness. GAA MOSFETs have potential to offer enhanced carrier transport properties compared to planar devices, because of the high carrier mobility on sidewall planes. Careful design and fabrication are critical for GAA MOSFETs for obtaining better transport properties in such structures [48]. Using GAA MOSFETs can lead to the increase of the ratio of the fin width to the gate length. If the design parameters of GAA MOSFETs are optimized, it is expected that the short-channel effects are adequately suppressed even if the fin width is larger than the gate length. The nanowire gate-all-around (GAA) structure is a promising successor to the FinFET structure because it can provide ultimate gate electrostatic control to suppress short channel effects. 𝐼𝑛𝐺𝑎𝐴𝑠 NW GAA MOSFETs integrate a 𝐼𝑛𝐺𝑎𝐴𝑠 channel and high-𝑘 dielectric into the gate-all-around device structure [49]. The radiation hardness of these devices is therefore of interest for potential future space applications. Moreover, as CMOS technology is approaching the sub-10 nm node, with the possible adoption of EUV lithography, device fabrication processes can also cause radiation damage. Therefore, it is useful to understand

11

FIGURE 2.2: A 3D structure of common Gate-All-Around (GAA) MOSFET.

radiation effects in future-generation device candidate technologies, such as 𝐼𝑛𝐺𝑎𝐴𝑠 nanowire (NW) gate-all-around (GAA) MOSFETs.

2.4

Junctionless Transistor

The classical transistors with multi-gates still have to face the challenge of ultra sharp doping profile. Recently, junctionless (JL) MOSFETs which have no doping concentration gradient between source/drain (S/D) region and body region are proposed. The JL MOSFET contains a silicon nanowire which needs a high doping concentration to realize amount of current flowing in the ON state [50]. The channel of the JL MOSFET is depleted by piping out the electrons (n-channel) or holes (p-channel) from the body region at lower gate bias, which causes low current in the OFF state. With the increase of gate bias, the depletion is reduced gradually. When the channel region under the gate becomes electrically neutral, an accumulation of carriers appear at the interface between the silicon nanowire and oxide near the gate electrode with further rise of gate bias. While, take an n-type JL MOSFET as an example; the valence and conduction bands of electrons in the silicon nanowire under the gate are higher than source and drain regions due to the depletion in the channel of the de-

12

FIGURE 2.3: 1st Junctionless transistor by Tyndall National Institute, Ireland in 2010.

vice. The exacerbation of the depletion creates an overlap between the valence and conduction bands in the channel and the drain separately, which results in a tunneling of electrons between the two bands. This is the effect of band-to-band tunneling (BTBT) that leads to a significant leakage current in the OFF state [51]. It means that the higher doping concentration of silicon nanowire triggers larger effect of BTBT.

2.5

Performance Scaling

Performance scaling seeks to scale each fabrication parameter to provide the highest performance device possible [52]. The fact that current power supplies are much higher than predicted by Denard shows that the industry as a whole is not interested in maintaining constant Fields. More realistic motivations for scaling device parameters are performance and reliability. Therefore, to predict the scaling of future technologies we should scale each parameter to provide the highest performance device possible while satisfying certain basic electrical and reliability requirements. These fundamental limits include the following:

13

2.5.1 Subthreshold Leakage Currents To keep power consumption down we must limit leakage currents by maintaining reasonably high thresholds. For high performance operation the power supply voltage must be significantly above the threshold. These requirements of low leakage and high performance limit how small a power supply voltage may be used. Time Dependent Dielectric Breakdown High electric fields in the gate oxide can cause gradual deterioration of the oxide layer until eventually dielectric breakdown is reached. Long term reliability of the gate oxide limits how thin an oxide layer may be used. Hot Electron Effects High lateral Fields in the channel can accelerate some electrons to high enough energies to pass into the gate oxide and change the device threshold over time. Long term threshold stability limits how short a channel length may be used. To maintain at least 5 orders of magnitude between on and off currents and high performance operation we need: VT > 0.3 V VDD > 1.2 V

(2.1)

2.5.2 Time Dependent Dielectric Breakdown High electric fields in the gate oxide can cause gradual deterioration of the oxide layer until eventually dielectric breakdown is reached. Long term reliability of the gate oxide limits how thin an oxide layer may be used. For a 10 year oxide lifetime at 125ºC we specify: 𝐸𝑂𝑋 = 𝑉𝐷𝐷 /𝑇𝑂𝑋 < 4.24 MV/cm

(2.2)

2.5.3 Hot Electron Effects High lateral fields in the channel can accelerate some electrons to high enough energies to pass into the gate oxide and change the device threshold over time. Long term threshold stability limits how short a channel length may be used. For less than a 10% shift in device transconductance over 10 years we specify: IG/ ID < 10−15

(2.3) 14

2.5.4 Short Channel Effects As we move the source and drain of a MOSFET closer physically together, it becomes more and more difficult to electrically isolate them. In deep sub-micron MOSFETs the depletion regions of the source and drain can significantly deplete the channel region making the threshold a function of the device length and drain voltage. These effects limit how low a doping concentration may be used. The minimum channel doping is determined by the DIBL requirement: ΔVT < 0.25VT

2.6

(2.4)

Major Quantum Phenomena in Nano Devices

The thickness and/or width of multi-gate FETs is reaching values that are less than 10 nanometers. Under these conditions the electrons in the “channel” (if we take the example of an n-channel device) from either a two-Dimensional Electron Gas (2DEG) if we consider a double-gate device or a one-Dimensional Electron Gas (1DEG) if we consider a triple or quadruple-gate MOSFET. This confinement is at the origin of the “volume inversion” effect [53] and yields an increase in the threshold voltage when the width/ thickness of the devices are reduced [54, 55]. An important consequence of scaling down of MuGFETs is volume inversion. It was first introduced by Balestra et al. [53]; if the 𝑆𝑖 thickness is reduced, the whole 𝑆𝑖 film is depleted and an important interaction appears within the 3D potential well. In such condition, the inversion layer is formed not only at the 𝑆𝑖 − 𝑆𝑖𝑂2 interface but throughout the entire 𝑆𝑖 film thickness. Thus the carriers are distributed throughout the entire 𝑆𝑖 volume in spite of confining at the interfaces which gives rise to “volume inversion”. Volume inversion enhances the number of minority carriers, increases carrier mobility and velocity, decrease low frequency noise and limits shot carrier effects. Another major quantum phenomenon in nano devices is the corner effect. Multiple gate devices show non planar silicon-gate oxide interface with corner. Because of charge sharing effects between two adjacent gates, premature inversion occurs at the corners of these devices. The corner accumulation influences the device parameters like threshold voltage and sub-threshold slope. Multiple threshold voltage and degraded sub-threshold slope are 15

two important drawbacks of this phenomenon. Though in case of MOSFETs it increases the leakage current at the edge of active region, for nanowire transistors it improves performance by increasing the current. The corner effect can be eliminated by using either a low doping concentration in the channel or corners with a large enough radius of curvature [56].

16

Chapter 3

Simulator Design

This chapter is organized into several sections explaining the complete self-consistent simulation procedure that is necessary for the theoretical study of Nano Wire Transistors (NWTs). The calculations are calculated after the convergence of Schrödinger – Poisson equation. The Fast Uncoupled Mode Space approach or FUMS involves solving one 2D Schrödinger equation in a self-consistent loop. This gives quite satisfactory result for the SNWT simulation of the selected devices with relative less computational effort [57]. Since our device has a dimension that is in the 10 nm regime, we consider that the flat band condition is inherently present in the device.

3.1

Simulated Devices

In our work we studied mainly two types of (Nanowire Transistor) NWT devices, namely the cylindrical surrounding gate device and the junctionless device. Figure 3.1 shows the cross section of a cylindrical gate all around nanowire transistor (NWT). Here, 𝑡𝑜𝑥 and 𝑡𝑆𝑖 represent gate oxide thickness and the 𝐼𝑛𝑥 𝐺𝑎1−𝑥 𝐴𝑠 channel thickness respectively. Here, the carrier transport takes place in the +x direction. In all the simulations, we had [110] oriented 𝐼𝑛𝑥 𝐺𝑎1−𝑥 𝐴𝑠 wafer with transport direction in the [100] direction. The surrounding gate nanowire transistors (NWTs) are excellent in terms of performance at in the vicinity of gate lengths below 10 nanometers. However due to some inherent fabrication difficulties, at the present stage it is quite difficult to fabricate such a surrounding gate cylindrical device at a massive commercial scale. The device that closely resembles the characteristics of that of a cylindrical surrounding gate is a circular cross section. In [58] the author showed that the gate all around device can be considered to be

17

FIGURE 3.1: Cross section of the cylindrical gate all around device under our study.

FIGURE 3.2: The conversion from a cylindrical gate all around device into an omega gate device if 𝑎 arises.

18

FIGURE 3.3: The conversion from a cylindrical gate all around device into an omega gate device. The substrate has overlapped a portion denoted cut from the radius. This incidentally, makes the omega parameter, a of the device equal to cut/r.

a multiple gate FET device with an equivalent number of gates. In [59, 60], the authors have used the term coverage ratio to satisfy the geometrical and structural differences of the two devices. They used the term coverage ratio to point out the amount of cylindrical nanowire channel being “covered” with the oxide substrate. In this thesis, however, we devise a separate representation relating these two devices on the based on the self-consistent analysis. We take a surrounding gate cylindrical device and a separate insulating substrate along with a thin metal layer at the bottom. When these two entities are completely separated from one another, we simply have the cylindrical device. By simply overlapping some of the portion of the cylindrical channel radially (like solar eclipse) with the oxide substrate as shown in the figure 3.2 we have a gate all around device. Depending on the amount of overlapping portion, we have different geometrical gate all around devices. To mathematically quantify such an overlapping, we introduce the concept of a variable named omega parameter or omega factor, a. It is defined by the ratio shown in the figure 3.3, 𝑎 = 𝑐𝑢𝑡/𝑟

19

(3.1)

In this text both of the terms are used interchangeably. It is straight forward to conclude that for 𝑐𝑢𝑡 = 0 we have the cylindrical gate all around device. In other words, for GAA devices we would have 𝑎 = 0.

3.2

Self-Consistent analysis

Our simulator is based on the Fast Uncoupled Mode Space (FUMS) approach for the selfconsistent loop and Uncoupled Mode Space (UMS) approach for transport calculations. In a three dimensional quantum transport simulator, most of the simulation resources are consumed in the process of finding out the Eigen functions and Eigen values by solving a 3D Schrödinger equation just after solving a 3D Poisson’s equation. The solution of the 3D Poisson’s equation is inevitable, because to obtain the full electrostatic of a NWT (where the charge distribution is three dimensional), 3D Poisson’s equation must be solved. This huge computational burden of solving two consecutive three dimensional PDEs is tactfully overcome in the Fast Uncoupled Mode Space (FUMS) approach which involves solving the 2D Schrödinger equation once in a self-consistent loop after solving a 3D Poisson’s equation. The 2D slice of the device is located at exactly the half way in the channel of the device. The transport part of calculation in FUMS is the same as that in UMS.

3.2.1 Poisson’s Equation The electrostatics inside the NWT is dictated by Poisson’s equation; which gives us the potential profile inside the device upon the application of gate voltage. The general form of it in three dimensions in given by, – 𝛻(𝜀𝛻 𝑈) = 𝜌 𝑑

𝑑

(3.2)

𝑑

where, ∇ ≡ (𝑥̂ 𝑑𝑥 + 𝑦̂ 𝑑𝑦 + 𝑧̂ 𝑑𝑧), U is the electrostatic, potential (volt), ρ is the charge density, ε is the permeability (𝐶 2 𝑁 −1 𝑚−2 ). Both U and ρ are functions of space coordinates. ε is a medium dependent constant and remains fixed for a particular isotropic medium. So, in three dimension equation (3.2) becomes 𝜕2

(𝜕𝑥 2 +

𝜕2

𝜕2

𝜕𝑦

𝜕𝑧 2

+ 2

20

𝜌

)𝑈 = − 𝜀

(3.3)

Proper boundary conditions are necessary in order to solve this differential equation accurately. In our simulation we have two types of boundary condition imposed on the device structure, namely, Dirichlet Boundary Condition imposed on the metal interfaces where the potential is known i.e. V(x, y, z) = 𝑉𝑔 where 𝑉𝑔 is the applied gate voltage. Also the substrate interfaces are kept at a ground potential in case of omega devices, so at the substrate V(x, y, z) = 0. The boundary conditions at the source and drain interfaces are 𝑉𝑠 and 𝑉𝑑 respectively. Neumann Boundary Condition imposed on the Si-SiO2 interfaces where the flux is considered to be continuous i.e. 𝜀1 𝐸1 = 𝜀2 𝐸2 where 𝐸1 and 𝐸2 are the corresponding normal electric fields at the interface.

3.2.2 Effective mass consideration The simplest way of obtaining effective masses in the different geometrical axes is to employ the effective mass equation (EME). Effective mass is an important issue for any kind of study of nano devices. We have also considered the variation of effective mass as it has a significant effect on band structure and many other device properties. In case of Silicon, the effective mass changes along with wafer variation. Silicon [100] wafers are universally used by the semiconductor industry for the CMOS integrated circuit fabrication. Therefore, motivated by technological importance, NWT device simulation is performed on [100] wafers most of the cases. The quantum simulation of Si [100] devices substantially reduced by the fact that the principal axes of the six fold degenerate conduction band ellipsoids are aligned along the device coordinate axes, effectively decoupling the kinetic energy along the device coordinate axes. In general the principal axes are not aligned with the device coordinate axes, so the associated kinetic energy becomes coupled and the effective mass equation becomes non-trivial. In this work, we have followed the procedures pointed out in [61] to generalize the EME approach to any arbitrary wafer orientation. Conduction band minima of a cubic semiconductor material appear either at multiple points for indirect band-gap materials i.e. Si and Ge. For Silicon, as mentioned before, the conduction band minima are located at six equivalent points, making it a six fold degeneracy and the constant energy surfaces are ellipsoids of revolutions around Δ and Λ axes, requiring

21

two effective masses, longitudinal 𝑚𝑙 and transverse 𝑚𝑡 [61]. In case of Silicon at delta region, 𝑚𝑙 = 0.916𝑚0 and 𝑚𝑡 = 0.19𝑚0 . In case of our device, the wafer direction is [110], transport [100] and width [010]. Let the effective mass along X, Y and Z axes be 𝑚𝑥 , 𝑚𝑦 and 𝑚𝑧 respectively. Therefore, from the calculations as in [61], we have, Valley with the four fold degeneracy: 𝑚𝑥 = 𝑚𝑡 , 𝑚𝑦 = (𝑚𝑡 + 𝑚𝑙 )/2 and 𝑚𝑧 = 2(𝑚𝑙 )(𝑚𝑡 )/(𝑚𝑙 + 𝑚𝑡 ). Valley with the two fold degeneracy: 𝑚𝑥 = 𝑚𝑙 , 𝑚𝑦 = 𝑚𝑡 and 𝑚𝑧 = 𝑚𝑡

3.2.3 Schrödinger’s Equation Once the potential profile is obtained, a 2D Schrödinger equation is solved at an arbitrary slice located approximately at the middle of the channel. The average wave functions ̅̅̅̅ 𝜉𝑚 (y, z) are the Eigen functions of the following 2D Schrödinger equation [−

ħ2 𝜕 2

1

𝜕

( )− 𝜕𝑦 𝑚∗ (𝑦,𝑧) 𝜕𝑦 𝑦

ħ2 𝜕

(

1

𝜕

2 𝜕𝑧 𝑚𝑧∗ (𝑦,𝑧) 𝜕𝑧

𝑚 ̅(𝑦, 𝑧)] ̅̅̅̅ )+ 𝑈 𝜉 𝑚 (𝑦, 𝑧) = ̅̅̅̅̅̅̅̅̅̅ 𝐸𝑠𝑢𝑏 𝜉 𝑚 (𝑦, 𝑧)

(3.4)

Here, 𝑚𝑦∗ (𝑦, 𝑧) and 𝑚𝑧∗ (𝑦, 𝑧) are the effective masses of electron in the y and z directions. ̅(𝑦, 𝑧) is obtained by, The average conduction band-edge 𝑈 ̅(𝑦, 𝑧) = 𝑈

1 𝐿𝑥 ∫ 𝑈(𝑥, 𝑦, 𝑧)𝑑𝑥 𝐿𝑥 0

(3.5)

where, 𝐿𝑥 is the length of the simulated NWT including source/drain extensions. After 𝑚 computing the eigen values 𝐸𝑠𝑢𝑏 and eigen functions ̅̅̅̅ 𝜉 𝑚 (𝑦, 𝑧) the first order stationary

perturbation theory was invoked to obtain the sub-band profile as [62], 22

𝑚 𝑚 2 2 𝑚 𝑚 ̅̅̅̅̅̅ ̅̅̅̅ ̅̅̅̅ ̅ (𝑥) = = 𝐸 𝐸𝑠𝑢𝑏 𝑠𝑢𝑏 + ∮𝑦,𝑧 𝑈(𝑥, 𝑦, 𝑧) |𝜉 (𝑦, 𝑧)| 𝑑𝑦𝑑𝑧-∮𝑦,𝑧 𝑈(𝑦, 𝑧) |𝜉 (𝑦, 𝑧)| 𝑑𝑦𝑑𝑧

(3.6)

3.2.4 Transport Calculation It is already mentioned that the transport part of calculation in FUMS is similar to that of UMS. In our simulation, we assume that the shape of the silicon body is uniform in the transport direction. As a result, the confinement potential (in the y-z) plane) varies very slowly along the transport direction (x). For example, the conduction band edge U (x, y, z) takes the same shape but different values at different x. For this reason, the Eigen functions 𝜉 𝑚 (𝑦, 𝑧; 𝑥)are approximately same along the channel, however the Eigen values are different. As a consequence we assume, 𝜉 𝑚 (𝑦, 𝑧; 𝑥) = ̅̅̅̅ 𝜉 𝑚 (𝑦, 𝑧)

(3.7)

which implies, 𝜕 𝜕𝑥

𝜉 𝑚 (𝑦, 𝑧; 𝑥) = 0

(3.8)

The very first requirement in modeling transport in any nanoscale device is to find out a suitable Hamiltonian [63]. In our simulation, the Hamiltonian matrix was a 3 dimensional and blocks tri-diagonal one. Each “plane” of it is given by:

𝛼1 𝛽 0 0 𝐻𝑚 = 0 0 0 (0

𝛽 𝛼2 𝛽 … … … … …

0 𝛽 𝛼3 … … … … …

0 0 𝛽 … … … … …

0 … … … … … … …

… … … … … … … … … … … … … 𝛼𝑚−1 … 𝛽

0 0 0 0 0 0 𝛽 𝛼𝑚 )

(3.9)

Here, the diagonal elements 𝛼𝑘 (𝑘 = 1,2, … … … , 𝑁𝑋 ) and off-diagonal elements 𝛽 are given by, 𝛼𝑘 =

ħ2 𝑎2 𝑚𝑥 𝑞

𝑚 + 𝐸𝑠𝑢𝑏 (𝑘)

23

(3.10)

Here, 𝑘 = 1,2, … … … , 𝑁𝑋 and 𝛽=

−ħ2

(3.11)

2𝑎2 𝑚𝑥 𝑞

where, 𝑚𝑥 = effective mass of electron in the transport direction. After calculating the Hamiltonian matrix, the Non Equilibrium Green’s Function was invoked. The NEGF formalism provides a sound conceptual basis for the development of quantum mechanical simulators [64, 65]. The Green’s function G (E) calculated at energy E is computed from: G (E) = 𝐸𝑆 𝑚 − 𝐻 − ∑𝑠(𝐸) − ∑1(𝐸) − ∑2(𝐸) 𝑚 Here, S, ∑𝑚 𝑆 , ∑1

and ∑𝑚 2

(3.12)

are all 𝑁𝑥 × 𝑁𝑥 matrixes.

S is the 𝑁𝑋 × 𝑁𝑋 identity matrix. ∑𝑚 𝑆

is the self energy that accounts for the scattering inside the device (i.e. the channel).

In this ballistic realm, this is equated to zero. The ∑𝑚 1

and ∑𝑚 2

are the self energy matrices for the source and drain extensions

respectively. These matrices are defined in the following manner: 𝜎1 ∑𝑚 (𝐸) = [ 0 1 0

0 0 0

0 0] 0

(3.13)

and ∑𝑚 2 (𝐸)

0 0 0 0 ] = [0 0 0 0 𝜎𝑁𝑥

(3.14)

The terms σ is defined as 2 𝜎 = −𝑡𝑚𝑠 ×𝑔

Here, −𝑡𝑚𝑠 =

−ħ2 2𝑚𝑎2 𝑞

and g is the solution of the following quadratic equation

𝑚 2 ]𝑔 − 1 = 0 −𝑡𝑚𝑠 𝑔2 + [(𝐸 + 𝑧𝑝𝑙𝑢𝑠) − 2𝑡𝑚𝑠 − 𝐸𝑠𝑢𝑏

where, 𝑧𝑝𝑙𝑢𝑠 is an infinitesimal imaginary number.

24

(3.15)

Afterwards the spectral density functions due to source and drain contact can readily be calculated as [63], 𝑚 𝑚 𝑚ϯ 𝐴1𝑚 (𝐸) = 𝐺 𝑚 (𝐸)Г1𝑚 (𝐸)𝐺 𝑚ϯ (𝐸), 𝐴𝑚 (𝐸) 2 (𝐸) = 𝐺 (𝐸)Г2 (𝐸)𝐺

(3.16)

ϯ ϯ where, Г1𝑚 (𝐸) ≡ 𝑗(∑1 (𝐸) − ∑1(𝐸))andГ𝑚 2 (𝐸) ≡ 𝑗(∑2 (𝐸) − ∑2(𝐸)), which determine

the electron exchange rates between the active device region and the source/drain reservoirs at energy E. In this coupled mode space, the diagonal elements of the spectral function matrixes represent the local density of states (LDOS) in the device for each mode. We define the LDOS for mode m, 𝐷1𝑚 (due to the source) and 𝐷2𝑚 (due to the drain). Here 𝐷1𝑚 and 𝐷2𝑚 are both 𝑁𝑥 × 1 vectors obtained as 𝐷1𝑚 [𝑝] =

𝐷2𝑚 [𝑝] =

1 𝜋𝑎

𝐴1 [(𝑚 − 1)𝑁𝑋 + 𝑝(𝑚 − 1)𝑁𝑋 + 𝑝], (𝑝 = 1,2, … , 𝑁𝑋 )

(3.17)

𝐴2 [(𝑚 − 1)𝑁𝑋 + 𝑝(𝑚 − 1)𝑁𝑋 + 𝑝], (𝑝 = 1,2, … , 𝑁𝑋 )

(3.18)

1 𝜋𝑎

Then the 1D electron density (In𝑚−1) for mode 𝑚 can be calculated by +∝

𝑚 𝑛1𝐷 = ∫−∝ [ 𝐷1𝑚 𝑓(𝜇𝑠 , 𝐸) + 𝐷2𝑚 𝑓(𝜇𝐷 , 𝐸)]𝑑𝐸

(3.19)

where, 𝑓 is the Fermi-Dirac statistics function, and 𝜇𝐷 (𝜇𝑆 ) is the source (drain) Fermi level, which is determined by the applied bias. The electron density obtained by Eq. (3.19) is a 1D distribution (along the x direction). To obtain a 3D electron density, we need couple eq. (3.19) with the quantum confinement wave function for mode𝑚, 𝑚 𝑚 (𝑥)|𝜉 𝑚 (𝑦, 𝑛3𝐷 = (𝑥, 𝑦, 𝑧) = 𝑛1𝐷 𝑧; 𝑥)|2

(3.20)

The total 3D electron density needs to be evaluated by summing the contributions from all the sub-bands in each conduction band valley. 𝑚 𝑁3𝐷 (𝑥, 𝑦, 𝑧) = ∑𝑚=1,2,3 𝑛1𝐷 (𝑥) |𝜉 𝑚 (𝑦, 𝑧; 𝑥)|2

25

(3.21)

Then this 3D electron density is fed back to the Poisson solver for the self-consistent calculations. Now, the total transmission coefficient, 𝑇(𝐸) can be written as a summation of the transmission coefficient 𝑇 𝑚 (𝐸) for each mode𝑚, 𝑚 𝑇(𝐸) = ∑𝑀 𝑚=1 𝑇 (𝐸)

(3.22)

where, 𝑇 𝑚 (𝐸) is obtained as [63] 𝑚ϯ 𝑇 𝑚 (𝐸) = 𝑡𝑟𝑎𝑐𝑒[Г1𝑚 (𝐸)𝐺 𝑚 (𝐸)Г𝑚 (𝐸) 2 (𝐸)𝐺

3.3

(3.23)

Ballistic Current Calculation

The ballistic current gives the upper limit of the device performance. Once self consistency is achieved, the ballistic electron current is computed by 𝐼𝑆𝐷 =

𝑞

+∝

∫ 𝑇(𝐸)[𝑓 (𝜇𝑠 , 𝐸) − 𝑓(𝜇𝐷 , 𝐸)]𝑑𝐸 𝜋ħ −∝

(3.24)

Where, 𝑇(𝐸)is the transmission coefficient calculated in equation (3.22), 𝑓is the Fermi function and ħ is the reduced Planck’s constant. Since we have two separate sets of effective masses with different degeneracy levels, the Schrödinger equation and the subsequent transport equations were calculated twice and their current contribution was simply added to get the total current in the device [57].

26

Poisson’s equation

Electrostatic

N

U SelfConsistent Calculation

Schrödinger’s equation

U

Transport

N

Converged U

Calculate current and other parameters FIGURE 3.4: Flow chart for iterative procedure for calculating N and U self consistently.

3.4

Threshold Voltage Calculation

The threshold voltage was defined as the applied gate voltage required to achieve the threshold inversion point [66]. So, 𝐼𝑥 = −𝑊µ𝑛 𝐶𝑜𝑥

𝑑𝑉𝑥 𝑑𝑥

[(𝑉𝐺𝑆 − 𝑉𝑥 )− 𝑉𝑇 ]

(3.25)

Where, 𝐸𝑥 = − 𝑑𝑉𝑥 ⁄𝑑𝑥 and 𝑉𝑇 is the threshold Voltage is defined by the equation, 𝑉𝑇 =

|𝑄 ′ 𝑆𝐷 (𝑚𝑎𝑥)| 𝐶𝑜𝑥

− 𝑉𝐹𝐵 + 2ø𝑓𝑝

(3.26)

For a given semiconductor material, oxide material and gate material, the threshold voltage is a function of semiconductor doping, oxide charge 𝑄′𝑆𝐷 and oxide thickness. The threshold voltage must be within the voltage range of a circuit design. The threshold voltage is the 27

point at which the transistor turns on. If a circuit is to operate between 0 and 5 V and the threshold voltage of a MOSFET is 10 V, for example, the device and the circuit cannot turn ‘on’ and ‘off’. The threshold voltage, then, is one of the important parameters of the MOSFET.

3.5

Sub-threshold Swing Slope Calculation

In a Field-Effect transistor (FET), the minimum voltage swing needed to turn a transistor “ON” is an important figure of merit that ultimately sets the minimum power supply voltages and the minimum power dissipation of a technology [67]. The sub-threshold swing is defined as the gate voltage required changing the drain current by one order of magnitude, one decade. In the MOSFET, the sub-threshold swing is limited to (kT/q) ln10 or 60 mV/dec at room temperature, and with scaling, the sub-threshold swing increases.

3.6

On/Off Current Ratio Calculation

Because of the decrease of the tunneling current in longer channels, the off-current decreases when the channel length is increased. On-current and off-current values for channel lengths of 10 to 60 nm is very important. We demonstrate a new type of FET device, which enables a controllable transition from NMOS digital to bipolar characteristics [68]. In the NMOS digital regime, the report [69] have a very high room temperature on/off current ratio (ION/IOFF) in comparison to InGaAs-based FET devices without sacrificing the field-effect electron mobilities in InGaAs. By engineering the source/drain contact area, we further estimate that a higher value of ION/IOFF up to 100 can be obtained in the device architecture considered.

3.7

Implementation of the simulator

In the self consistent analysis scheme of any dimension, the Schrödinger equation quantum mechanically computes the electron density and their transmission probability for a given potential profile. Poisson’s equation, on the other hand, checks whether the charge profile is consistent with the potential profile. So, ultimately any computer sub-routine for self 28

consistent analysis follows the flow-chart given in fig. (3.4). The implementation of the 3D self consistent simulator is done with the aid of scripting language of COMSOL Multiphysics 4.4 [27] invoked from MATLAB [26]. This involves numerical solution of two partial differential equations (PDE) in a coupled manner, namely Poisson’s equation (3.3) and Schrödinger’s equation (3.4) along with a number of numerical integration. Finite Element Method (FEM) is used to solve the PDEs. In COMSOL Multiphysics 4.4 [27], there is a build in template for Poisson’s equation under the classical PDE tab. The solution procedure of any equation in COMSOL starts with defining the geometry of the device. In COMSOL Multiphysics, Poisson’s equation template in 3D is given by, – 𝛻. (𝑐𝛻 𝑢) = 𝑓

(3.27)

where, c is the diffusion coefficient, 𝑓 is the source term and u is the dependent variable. Comparing eq. (3.3) and (3.27) the following relationships between the coefficients can be established as, 𝑢 ≡ Electrostatic Potential, 𝑈(𝑥, 𝑦, 𝑧) 𝑐 ≡ Dielectric Permittivity, 𝜀 𝑓 ≡ Charge Density, 𝜌 ∂2

In 3D, ∇ is translated to (∂x2 +

∂2

+ ∂y2

∂2 ∂z2

). After setting the necessary Dirichlet boundary

conditions for various regions, the Poisson’s equation was solved. Neumann boundary condition is applied to boundaries where this value is not exactly known but any kind of continuity can be applied. The Schrödinger equation is solved using the General form PDE (coefficient form) after a 2D cross section of the device is defined. This equation in COMSOL is given by 𝜆2 𝑒𝑎 𝑢 − 𝜆𝑑𝑎 𝑢 + 𝛻. (𝑐𝛻 𝑢 − 𝛼𝑢 + 𝛾) + 𝛽. 𝛻𝑢 + 𝑎𝑢 = 𝑓

where, 𝑐 ≡ Diffusion coefficient, 𝑎 ≡ Absorption coefficient, 𝑓 ≡ Source term, 𝑒𝑎 ≡ Mass coefficient, 𝑑𝑎 ≡ Damping coefficient, 29

(3.28)

𝛼 ≡ Conservative flux convection coefficient, 𝛽 ≡ Convection coefficient, 𝛾 ≡ Conservative flux coefficient, 𝑢 ≡ Dependent variable, ψ Comparing eq. 3.4 with the eq. 3.28, we find that,

𝑐=

ħ2 2𝑚𝑦

0

0

ħ2 2𝑚𝑧 ]

[

̅(𝑦, 𝑧) as calculated in eq. (3.5). 𝑎 = Average conduction band-edge 𝑈 𝑓 = 𝑒𝑎 = 0. 𝑑𝑎 = 1. 𝛼 = 𝛽 = 𝛾 = 0. These two PDE solver packages of finite element method are invoked from MATLAB, so that Poisson’s equation and the Schrödinger’s equation can run in a coupled manner, i.e. one can except the product of the other. We assumed all of the initial charge profile to be zero. Then Poisson’s equation is solved taking the NWT channel to be fully depleted to obtain initial potential profile. This potential profile is given input to the Schrödinger’s equation to obtain the Eigen energies and corresponding Eigen functions. Then the charge profile is calculated using these outputs by numerical integration. That charge profile was fed back to update the Poisson’s equation and also to check for consistency from the MATLAB domain. The simulation process was carried out using the Gauss-Siedal method, with an error margin of 1%. After the convergence of basis self-consistent solver, carrier concentrations and ballistic current are obtained using the model described before. The benchmarking of our solver is given in Chapter 4 and the flow chart of the FUMS sub routine is provided in the appendix section.

30

Chapter 4

Results and Discussions

The simulator was designed according to the design procedure described in chapter 3, and simulation was carried out on cylindrical surrounding gate devices with compound semiconducting element like 𝐼𝑛𝑥 𝐺𝑎1−𝑥 𝐴𝑠. Channel length of 10 nm was studied with channel radius of 1.5 nm. For the same gate lengths for the same lengths, threshold voltage variation with varying x composition of 𝐼𝑛𝑥 𝐺𝑎1−𝑥 𝐴𝑠 and Sub threshold swing slop with varying ‘x’ is studied. All of the devices have also been simulated for oxide thickness of 1 nm and 1.5 nm. In all the cases, we had source and drain extension of 2 × 1023 𝑚−3 is considered. In case of Junctionless surrounding gate MOSFET devices, the substrate was kept at a ground potential.

4.1

Solver Benchmarking

The solver was based on the procedures by Wang et al. [57]. As said to its inventor, the simulator is accurate to within ±2% of the simulator designed in [57]. Slight deviation was observed due to numerical procedures and probable data mishandling between COMSOL and MATLAB domains.

4.2

Charge Concentration

The charge concentration is studied for gate voltage above the threshold voltage. This ensures that the device do not operate in accumulation region. As a consequence, we can neglect the hole concentration compared to the electron concentration. Hence, in all succeeding discussions, ‘charge concentration would preponderantly refer to ‘electron concentration’.

31

4.3

Threshold Voltage Variation Due to Change of Stress

Since the threshold voltage determines the requirements for turning the MOS transistor on or off, it is very important to be able to adjust Vt in designing the device. For example, if the transistor is to be used in a circuit driven by a 3 V battery, it is clear that a 4 V threshold voltage is unacceptable. Some applications require not only a low value of Vt, but also a precisely controlled value to match other devices in the circuit [70]. So, in our thesis we determined the lowest value of threshold voltage, Vt in respect to a specific stress of 𝐼𝑛𝑥 𝐺𝑎1−𝑥 𝐴𝑠. As we can see in figure 4.1 the value of stress, ‘x’ is 0.57.

FIGURE 4.1: Stress vs Threshold voltage.

Table 4.1: Simulation data for stress vs. threshold voltage Stress, x Threshold voltage, VT (V)

4.4

0.1

0.2

0.25

0.35

0.5

0.57

0.6

0.3

0.33

0.38

0.47

0.3

0.27

0.63

SS Slope Variation Due to Change of Stress

In recent years, a growing number of transistors have beenreported, which explore the use of the field effect to gate an interband tunneling current [71–75]. Several of these 32

authorshave characterized the sub-threshold swing. In the carbonnanotube field-effect transistor of Appenzeller et al. [74], a sub-threshold swing of 40 mV/dec was measured in a double-gated transistor in which interband tunnel current flows throughan n-p-n channel modulated by a top gate. In simulations, Bhuwalka et al. [73] have shown in a vertical gated p-i-n Si/SiGe interband tunneling transistor that sub-threshold swings of 44 mV/dec can be achieved. In a lateral embodiment of the p-i-n Si interband tunnel transistor, Wang et al. [72] have shown by simulation that sub-threshold swings of 15 mV/dec and even smaller are achievable and conclude that the sub-threshold swing is not limited by kT/q. In this thesis, we outline the reasons for the low sub-threshold swing for GAA transistors and analyze a new transistor configuration for low Sub-threshold swing transistor action. We could not achieve the lowest value, but 63 mV/dec is not bad either. (Figure 4.2)

FIGURE 4.2: Stress vs Subthreshold Swing Slope.

Table 4.2: Simulation data for stress vs. sub-threshold swing slope Stress, x

0.1

0.2

0.25

0.35

0.5

0.57

0.6

SS slope

76

82

78

80

82

63

87

(mV/dec) 33

4.5

ON/OFF Current Ratio Variation Due to Change of Stress

On off current ratio is often used in field effect transistors (FET). It characterizes how much the difference between the on state current and off state current. Typically, it is around106 − 1010 . ION/IOFF is the figure of merit for having high performance (more ION) and low leakage power (less IOFF) for the CMOS transistors. Typically more gate control leads to more ION/IOFF. In our thesis, we got the ION/IOFF is ≅ 104 .

FIGURE 4.3: Stress vs ION/IOFF current ratio.

Table 4.3: Simulation data for stress vs. ON/OFF current ratio Stress, x

0.1

0.2

0.25

0.35

ON/OFF

103

102

4 × 102

5 ×103

current ratio

34

0.5

0.57

0.6

6.77 × 103

≅ 104

≅ 104

4.6

Results Summary

From the data and with respect to figures, we can see that at the stress value of 0.57; the threshold voltage, subthreshold swing slope is minimal, and ION/IOFF ratio is maximum. In this point our estimated transistor’s formation is 𝐼𝑛0.57 𝐺𝑎0.43 𝐴𝑠 which indicates the best value all around for fabrication process.

35

Chapter 5

Conclusion

5.1

Summary

In this thesis, a well-organized method to study the electro statistics and transport characteristics has been conducted for nanowire Junctionless GAA FETs. Our proposed stress value of our FET is 𝐼𝑛0.57 𝐺𝑎0.43 𝐴𝑠. At first, a surrounding gate device was taken having a channel length of 10 nm and channel thickness of 2.5 nm. For such small scaled devices, QM effects like splitting of the energy levels into sub-bands, carrier quantization, quantum confinement and wave function penetration become prominent. To properly take into account these QM effects, coupled 3D Poisson 2D Schrödinger equations were solved self consistently. Systematic simulations have been performed to investigate the threshold voltage, Subthreshold Swing Slope and ION/IOFF ratio from the simulator. For the purpose of this work, a self-consistent simulator based on the Fast Uncoupled Mode Space approach was adopted. In this work, basically we generalized the performance of the junctionless gate-all-around FET.

5.2

Future Prospects

The results obtained from this work can be used to derive compact expressions relating the performances of the two devices. The compact models are much more flexible tools for future use rather than running lengthy simulations in computers. In this work, we use 𝐼𝑛𝑥 𝐺𝑎1−𝑥 𝐴𝑠 as the semiconductor. Varying the semiconductor material can vary the device performance as well. This is another future prospect of this work; we would like to generalize the simulator for different semiconducting materials.

36

The gate oxide thickness is an important process parameter. In our study the gate oxide thickness was kept at a constant 1nm. The study of the variation of different parameters with respect to the gate oxide thickness is yet to be added in our simulation. Finally, the simulator algorithm can be modified to have a faster and more efficient solver and develop a cross platform “3D Simulator Application” that will be able to run in all operating system platforms in a “moderate” computer. From our data sheet, the transistor fabricators can realize their necessary values for fabricating 𝐼𝑛𝑥 𝐺𝑎1−𝑥 𝐴𝑠 gate all around junctionless FET and after the fabrication process we can compare the actual values with our experimental values.

37

Appendix A

Flow Chart for FUMS Approach The fast uncoupled mode space approach follows a basic flow chart as explained in detail in chapter 3. Now we graphically present the flow chart here.

Start: Initial charge profile Poisson’s equation Potential profile Schrödinger’s Equation

Eigen functions and Eigen values st

1 order stationary perturbation theory Sub band Device Hamiltonian [H] NEGF formalism: N1D, LDOS

Consistent with initial carrier concentration?

No

Yes Output calculation Stop FIGURE A.1: Flow chart for simulator design in the Fast Uncoupled Mode Space approach.

38

References [1] Julius Edgar Lilienfeld, "Method and apparatus for controlling electric currents," US1745175 A, January 28, 1930. [2] Dawon Kahng and John M. Atalla, "Silicon-silicon dioxide field induced surface devices," in IRE Device Research Conference, Pittsburgh, PA, 1960, pp. 3:120-125. [3] Frank M. Wanlass, "Low stand-by power complementary field effect circuitry," US3356858 A, December 5, 1967. [5] Yuan Taur and Tak H. Ning, Fundamentals of Modern VLSI Devices, 1st ed. Cambridge, UK: Cambridge University Press, 1998. [6] Jean- Pierre Colinge, FinFETs and Other Multi-Gate Transistors, 1st ed., JeanPierre Colinge and Anantha Chandrakasan, Eds. New York, United States of America: Springer Science+ Business Media, 2008. [7] Yuan Taur et al., "CMOS scaling into the nanometer regime," Proceedings of the IEEE, vol. 85, no. 4, pp. 486-504, April 1997. [8] Bijan Davari, Robert H. Dennard, and G. G. Shahidi, "CMOS scaling for high performance and low power-the next ten years," Proceedings of the IEEE, vol. 89, no. 4, pp. 595-606, April 1995. [9] Shojiro Asai and Yasuo Wada, "Technology challenges for integration near and below 0.1 um," Proceedings of the IEEE, vol. 85, no. 4, pp. 505-520, April 1997. [10] H.-S. Phillip Wong, David J. Frank, P. M. Solomon, C. H.J. Wann, and J. J. Welser, "Nanoscale CMOS," Proceedings of IEEE, vol. 87, no. 4, pp. 537-570, April 1999. [11] Jean - Pierre Colinge, "Novel gate concepts for MOS devices," in Proceeding of the 34th European Solid-State Device Research Conference, 2004. ESSDERC 2004., Leuven, 2004. [12] T. Park et al., "PMOS body-tied FinFET (Omega MOSFET) characteristics," in Device Research Conference, Salt Lake City, 2003. [13] T. Park et al., "Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers," in Digest of Technical Papers - Symposium on VLSI Technology, 2003, pp. 135-136. [14] Xuejue Huang et al., "Sub 50-nm FinFET: PMOS," in Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International, 1999. [15] Shiying Xiong and Jeffrey Bokor, "Sensitivity of double-gate and FinFETDevices to process variations," IEEE Transactions on Electron Devices, vol. 50, no. 11, pp. 2255 - 2261, November 2003. 39

[16] Bich- Yen Nguyen et al., "Integration challenges of new materials and device architectures for IC applications," in International Conference on Integrated Circuit Design and Technology, 2004, pp. 237-243. [17] Jong- Tae Park and Jean- Pierre Colinge, "Multiple-gate SOI MOSFETs: device design guidelines," IEEE Transactions on Electron Devices, vol. 49, no. 12, pp. 2222 - 2229, December 2002. [18] D. Hisamoto et al., "A folded-channel MOSFET for deep-sub-tenth micron era," in International Electron Devices Meeting, Technical Digest, San Fransisco, 1998. [19] D. Hisamoto et al., "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm," IEEE Transactions on Electron Devices, vol. 47, no. 12, pp. 2320 - 2325, December 2000. [20] Bin Yu et al., "FinFET scaling to 10 nm gate length," in International Electron Devices Meeting, San Fransisco, 2002, pp. 251-254. [21] Y. Omura, S. Horiguchi, M. Tabe, and K. Kishi, "Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs," IEEE Electron Device Letters, vol. 14, no. 12, pp. 569 - 571, December 1993. [22] Frank Stern and W. E. Howard, "Properties of Semiconductor Surface Inversion Layers in the Electric Quantum Limit," Physical Review, vol. 163, no. 3, pp. 817820, November 1967. [23] Massimo V. Fischetti, Bo Fu, and William G. Vandenberghe, "Theoretical Study of the Gate Leakage Current in Sub-10-nm Field-Effect Transistors," IEEE Transactions on Electron Devices, vol. 60, no. 11, pp. 3862 - 3869, November 2013. [24] Frank Stern, "Self-Consistent Results for n-Type Si Inversion Layers," Physical Review B, vol. 5, no. 12, pp. 4891-4899, June 1972. [25] Jean - Pierre Colinge, J. C. Alderman, Weize Xiong, and C. R. Cleavelin, "Quantum-mechanical effects in trigate SOI MOSFETs," IEEE Transactions on Electron Devices, vol. 53, no. 5, pp. 1131 - 1136, May 2006. [26] The MathWorks, Inc. [Online]. http://www.mathworks.com/ [27] COMSOL Inc. [Online]. https://www.comsol.com/ [28] Edward Yi Chang, Yueh - Chin Lin, Hung - Wei Yu, and Sankalp Kumar Singh. Stony Brook University. [Online]. http://www.ece.stonybrook.edu/~serge/ARW8/ABSTRACTS/Chang.pdf [29] Jean - Pierre Colinge, Xavier Baie, Vincent Bayot, and E. Grivei, "A silicon-oninsulator quantum wire," Solid-State Electronics, vol. 39, no. 1, pp. 49-51, January 1996.

40

[30] Zheng Jiao and C. Andre T. Salama, "A fully depleted del-channel SOI nMOSFET," in The Electrochemical Society, 2001, pp. 403-408. [31] Jean - Pierre Colinge, M. H. Gao, A. Romano Rodriguez, H. Maes, and C. Claeys, "Silicon-on-insulator 'gate-all-around device'," in International Electron Devices Meeting, 1990, pp. 595-598. [32] D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takeda, "A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET," in International Electron Devices Meeting, 1989, pp. 833-836. [33] Fu - Liang Yang et al., "25 nm CMOS Omega FETs," in International Electron Devices Meeting, 2002, pp. 255-258. [34] Jong - Tae Park, Jean - Pierre Colinge, and C. H. Diaz, "Pi-Gate SOI MOSFET," IEEE Electron Device Letters, vol. 22, no. 8, pp. 405 - 406, August 2001. [35] Toshihiro Sekigawa and Yasuhiro Hayashi, "Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate," Solid-State Electronics, vol. 27, no. 8-9, pp. 827-828, September 1984. [36] B. Agrawal, V. K. De, J. M. Pimbley, and J. D. Meindl, "Short channel models and scaling limits of SOI and bulk MOSFETs," IEEE Journal of Solid-State Circuits, vol. 29, no. 2, pp. 122 - 125, February 1994. [37] M. Lemme et al., "Subthreshold characteristics of p-type triple-gate MOSFETs," in European Solid-State Device Research, 2003, pp. 123 - 126. [38] Xavier Baie, Jean - Pierre Colinge, V. Bayot, and E. Grivei, "Quantum-wire effects in thin and narrow SOI MOSFETs," in IEEE International SOI Conference, 1995, pp. 66 - 67. [39] Zoran Krivokapic et al., "High performance 25 nm FDSOI devices with extremely thin silicon channel," in Symposium on VLSI Technology, 2003, pp. 131 - 132. [40] S. Miyano, M. Hirose, and F. Masuoka, "Numerical analysis of a cylindrical thinpillar transistor (CYNTHIA)," IEEE Transactions on Electron Devices, vol. 39, no. 8, pp. 1876 - 1881, August 1992. [41] A. Nitayama et al., "Multi-pillar surrounding gate transistor (M-SGT) for compact and high-speed circuits," IEEE Transactions on Electron Devices, vol. 38, no. 3, pp. 579 - 583, March 1991. [42] V. Passi, B. Olbrechts, and J. P. Raskin, "Fabrication of a Quadruple Gate MOSFET in Silicon-On-Insulator Technology," in Abstracts of the NATO Advanced Research Workshop on Nanoscaled Semiconductor-On-Insulator Structures and Devices, 2006, p. 11.

41

[43] Hyunjin Lee et al., "Sub-5nm All-Around Gate FinFET for Ultimate Scaling," in Symposium on VLSI Technology, 2006, pp. 58 - 59. [44] Sung - Young Lee et al., "Three-dimensional MBCFET as an ultimate transistor," IEEE Electron Device Letters, vol. 25, no. 4, pp. 217 - 219, April 2004. [45] Donggun Park, "3 Dimensional GAA Transitors : twin silicon nanowire MOSFET and multi-bridge-channel MOSFET," in IEEE International SOI Conference, 2006, pp. 131 - 134. [46] T. Ernst et al., "Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack," in International Electron Devices Meeting, 2006, pp. 1 - 4. [47] Thomas Skotnicki, "Heading for decananometer CMOS - Is navigation among icebergs still a viable strategy?," in 30th European Solid-State Device Research Conference, 2000, pp. 19 - 33. [48] Jae Young Song, Woo Young Choi, Ju Hee Park, Jong Duk Lee, and Byung - Gook Park, "Design optimization of gate-all-around (GAA) MOSFETs," IEEE Transactions on Nanotechnology, vol. 5, no. 3, pp. 186 - 191, May 2006. [49] J. J. Gu et al., "20–80nm Channel length InGaAs gate-all-around nanowire MOSFETs with EOT=1.2nm and lowest SS=63mV/dec," in IEEE International Electron Devices Meeting (IEDM), 2012, pp. 27.6.1 - 27.6.4. [50] Jean - Pierre Colinge et al., "SOI gated resistor: CMOS without junctions," in IEEE International SOI Conference, 2009, pp. 1 - 2. [51] Suresh Gundapaneni et al., "Effect of Band-to-Band Tunneling on Junctionless Transistors," IEEE Transactions on Electron Devices, vol. 59, no. 4, pp. 1023 1029, April 2012. [52] Grant McFarland and Michael Flynn, "Limits of Scaling MOSFETs," Stanford University, California, Technical Report CSL-TR-95-662 1995. [53] Francis Balestra, Sorin Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, "Doublegate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance," IEEE Electron Device Letters, vol. 8, no. 9, pp. 410 - 412, September 1987. [54] Y. Omura, S. Horiguchi, M. Tabe, and K. Kishi, "Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs," IEEE Electron Device Letters, vol. 14, no. 12, pp. 569 - 571, December 1993. [55] T. Poiroux et al., "Multiple gate devices: advantages and challenges," Microelectronic Engineering, vol. 80, pp. 378-385, June 2005.

42

[56] W. Xiong, J. W. Park, and Jean - Pierre Colinge, "Corner effect in multiple-gate SOI MOSFETs," in IEEE International SOI Conference, 2003, pp. 111 - 113. [57] Jing Wang, Eric Polizzi, and Mark Lundstrom, "A three-dimensional quantum simulation of silicon nanowire transistors with the effective-mass approximation," Journal of Applied Physics, vol. 96, no. 4, pp. 2192 - 2203, August 2004. [58] Te - Kuang Chiang, "A Novel Scaling Theory for Fully Depleted Omega-Gate MOSFETs Included With Equivalent Number of Gates," IEEE Transactions on Electron Devices, vol. 61, no. 3, pp. 926 - 929, March 2014. [59] Yiming Li, Hung - Mu Chou, Bo - Shian Lee, Chien - Sung Lu, and Shao - Ming Yu, "Computer Simulation of Germanium Nanowire Field Effect Transistors," in International Conference on Simulation of Semiconductor Processes and Devices, 2005, pp. 227 - 230. [60] Yiming Li, Hung - Mu Chou, and Jam - Wem Lee, "Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETs," IEEE Transactions on Nanotechnology, vol. 4, no. 5, pp. 510 - 516, September 2005. [61] Anisur Rahman. (2005, December) Exploring new channel materials for nanoscale CMOS devices: A simulation approach. [Online]. https://nanohub.org/resources/1316/download/arthesis_submitted_to_committee.pdf [62] E. Polizzi and N. Ben Abdallah, "Self-consistent three-dimensional models for quantum ballistic transport in open systems," Physics Review B, vol. 66, no. 24, p. 245301, 2002. [63] Supriyo Datta, Electronic Transport in Mesoscopic Systems. Cambridge, UK: Cambridge University Press, 1995. [64] Supriyo Datta, "Nanoscale device modeling: the Green’s function method," Superlattices and Microstructures, vol. 28, no. 4, pp. 253 - 278, 2000. [65] M. P. Anantram, Mark S. Lundstrom, and Dmitri E. Nikonov, "Modeling of Nanoscale Devices," Proceedings of IEEE, vol. 96, no. 9, pp. 1511 - 1550, 2008. [66] Donald A. Neamen, Semiconductor Physics and Devices: Basic Principles. New York: McGraw-Hill, 2003. [67] Qiang Chen, B. Agrawal, and J. D. Meindl, "A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs," IEEE Transactions on Electron Devices, vol. 49, no. 6, pp. 1086 - 1090, 2002. [68] Jen Chih - Shih et al., "Tuning On–Off Current Ratio and Field-Effect Mobility in a MoS2–Graphene Heterostructure via Schottky Barrier Modulation," ACS NANO, vol. 8, no. 6, pp. 5790–5798, 2014.

43

[69] Mohammad Hadi Tajarrod and Hassan Rasooli Saghai, "High Ion/Ioff current ratio graphene field effect transistor: the role of line defect," Beilstein Journal of Nanotechnology, vol. 6, pp. 2062–2068, 2015. [70] Nezih Pala. Florida International University. [Online]. https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=3&cad=rja &uact=8&ved=0ahUKEwiq6usodPOAhUIGhQKHSTcCDoQFggxMAI&url=http% 3A%2F%2Fweb.eng.fiu.edu%2Fnpala%2FEEE6397ex%2FEEE_6397_Ch7_FETs_ PART3.pdf&usg=AFQjCNFIaIJvN08emhfDfGy87hIEcCcsLQ [71] C. Aydin et al., "Lateral interband tunneling transistor in silicon-on-insulator," Applied Physics Letters, vol. 84, no. 10, pp. 1780 - 1782, 2004. [72] P. F. Wang et al., "Complementary tunneling transistor for low power application," Solid-State Electronics, vol. 48, no. 12, pp. 2281 - 2286, 2004. [73] Krishna Kumar Bhuwalka, Jörg Schulze, and Ignaz Eisele, "Performance Enhancement of Vertical Tunnel Field-Effect Transistor with SiGe in the δp+ Layer," Japanese Journal of Applied Physics, vol. 43, no. 7A, pp. 4073 - 4078, 2004. [74] J. Appenzeller, Y. M. Lin, J. Knoch, and Ph. Avouris, "Band-to-Band Tunneling in Carbon Nanotube Field-Effect Transistors," Physical Review Letters, vol. 93, no. 19, p. 196805, 2004. [75] Kyung Rok Kim et al., "Field-induced interband tunneling effect transistor (FITET) with negative-differential transconductance and negative-differential conductance," IEEE Transactions on Nanotechnology, vol. 4, no. 3, pp. 317 - 321, 2005.

44