IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 7, JULY 2014

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New Parallel ZVS Converter With Less Active Switches and Smaller Output Inductance Bor-Ren Lin, Senior Member, IEEE, and Shih-Kai Chung

Abstract—This paper presents a new three-level zero-voltage switching (ZVS) dc/dc converter for high input voltage applications. There are two ZVS circuits in the proposed converter to share load current. Thus, the size of the output chokes is reduced. These two circuits use the same power switches. Thus, the proposed converter has less switch counts compared with the conventional parallel three-level ZVS dc/dc converter. In the proposed converter, each circuit combines one half-bridge converter and one three-level converter. The transformer secondary windings of two converters are connected in series to reduce the size of output inductor. The voltage stress of each power switch is limited at one-half of input voltage due to three-level circuit topology. Based on the resonant behavior by the output capacitance of active switches and the leakage inductance (or external inductance) at the transition interval, power switches are turned on at ZVS within the desired load range. Experiments based on a 1.5 kW prototype are provided to demonstrate the performance of the proposed converter. Index Terms—DC/DC power conversion, zero-voltage switching (ZVS).

I. INTRODUCTION HREE-LEVEL dc/dc converters/inverters [1]–[5] have been proposed to use low voltage stress MOSFETs with high switching frequency instead of insulated gate bipolar transistors (IGBT) for switching mode power supplies (SMPSs) in medium power applications or use low voltage stress IGBT with low switching frequency for ac motor drives and active power filters. Three-phase SMPS systems are normally used for medium power applications such as modern cloud power units. In order to meet the power quality demand, three-phase power factor correctors with one, four or six active switches have been proposed for the past twenty years. Therefore, threephase line currents are controlled to be sinusoidal waveforms with nearly unity power factor. Thus, the reactive power and line current harmonics are eliminated. Since power factor correctors with boost type voltage conversion are widely adopted in three-phase ac/dc converters, the dc bus voltage after the three-phase power factor corrector may be higher than 750– 800 V. Thus, MOSFETs with 900 V voltage stress can be used in the second stage dc/dc converters such as phase-shift full-

T

Manuscript received January 13, 2013; revised March 20, 2013, May 12, 2013, and August 18, 2013; accepted August 26, 2013. Date of current version February 18, 2014. This work was supported by the National Science Council under Grant NSC 102-2221-E-224-022-MY3. Recommended for publication by Associate Editor F. L. Luo. The authors are with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin 64002, Taiwan (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2013.2280451

bridge converters, or MOSFETs with 500 V or 600 V voltage stress can be adopted in the three-level dc/dc converters. The series connection of MOSFETs scheme and the three-level dc/dc converters [1]–[3] have been proposed to overcome high voltage stress problem. However, the balance issue of the voltage across the series switches at the static and dynamic load conditions is not easy to overcome. The semiconductor switches in three-level dc/dc converters can be reduced at one-half of the input voltage. In order to realize the low size, light weight and high circuit efficiency SMPS, three-level converters with zerovoltage switching (ZVS) or zero-current switching (ZCS) have been proposed in [6]–[13]. Three-level converters with auxiliary circuits [14], [15] have been proposed to extend ZVS operation range. However, the design procedure of the auxiliary circuit is very complicated. Series resonant converters [16]–[20] with variable switching frequency have proposed to regulate output voltage with the advantages of high voltage gain and high conversion efficiency. However, the resonant converters have a wider range of switching frequency from light load to full load. Thus, the magnetic components are very difficult to be designed at the optimal condition. A new parallel ZVS converter is presented in this paper to reduce the switch counts and decrease the output ripple current. For high load current and high input voltage applications, the conventional parallel three-level converter with fixed frequency PWM is usually adopted. There are eight power switches in the conventional parallel three-level converter. In the proposed converter, there are two dc circuit cells with the same MOSFETs. Thus, there are only four active switches in the proposed converter. Two dc circuit cells are connected in parallel at the secondary side for high load current applications so that the current stresses of the transformer windings, rectifier diodes and output inductors are reduced. Three-level ZVS converter is adopted in the primary side for high input voltage applications, such as three-phase ac/dc converter with/without power factor correction (PFC) so that MOSFETs with low voltage stress can be used in three-phase SMPS power units. In each circuit cell, one half-bridge converter and one three-level converter are adopted at the high voltage side and the transformer secondary windings of two converters are connected in series at low voltage side so that the voltage across the output inductors is reduced and the output inductor ripple current is decreased compared with the output inductor ripple current in the conventional three-level converter. Based on the resonant behavior by resonant capacitance and resonant inductance at the transition interval, MOSFETs can be turned on at ZVS. Finally, experiments with a 1.5 kW prototype are provided to verify the effectiveness of the proposed converter.

0885-8993 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information.

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Fig. 2.

Fig. 1. Circuit configuration: (a) conventional three-level dc converter; (b) three-level hybrid converter with low output ripple current.

II. CIRCUIT CONFIGURATION Fig. 1(a) shows the conventional three-level dc converter. In order to reduce the voltage stress of active switches at Vin /2, two clamped diodes and one flying capacitor are adopted in the circuit. Due to the added flying capacitor, two spilt input capacitor voltages can be automatically balanced in a switching cycle. The rectified voltage vrect at the secondary side has two voltage levels Vin /(2n) and 0. In order to further decrease the ripple current of output inductor, it is a way to reduce the voltage across the output inductor. Thus, one more half-bridge converter can be added to the conventional three-level dc converter as shown in Fig. 1(b). The voltage stress of active switches is also equal to Vin /2. Cf 1 , Cf 2 , S3 , S4 , T2 , and Lr 2 work as an uncontrolled half-bridge converter. Since the secondary windings of T1 and T2 are connected in series, two voltage levels, Vin /(2n1 )+Vin /(4n2 ) and Vin /(4n2 ), are generated on the rectified voltage vrect . Thus, the lower ripple current of output inductor can be obtained due to lower voltage across the output inductor compared with the conventional three-level dc converter. For high load current applications, the parallel dc/dc converters were usually adopted in industry power converters. However, these solutions will increase the circuit components and also reduce the circuit reliability. Fig. 2 shows the circuit configuration of the proposed ZVS converter. The voltage stress of all switches in Fig. 2 is equal to Vin /2. The input dc bus voltage Vin is obtained from a three-phase ac/dc converter with PFC. The dc input voltage Vin is about 750–800 V for a three-phase 380 Vrm s /480 Vrm s ac/dc converter. Cin1 and Cin2 are equal and large enough to have the equal voltages VC in 1 = VC in 2 = Vin /2. S1 − S4 are power MOSFETs with Vin /2 voltage stress. Thus, MOSFETs with 500 V voltage rating can be used in the proposed converter. Cr 1 − Cr 4 are the output capacitances of S1 − S4 ,

Circuit configuration of the proposed converter.

respectively. The average voltage of flying capacitor is VC f = Vin /2. C1a − C2b are dc blocking capacitances. The average capacitor voltages VC 1a = VC 2a = Vin /2 and VC 1b = VC 2b = Vin /4. Lr 1a − Lr 2b are the resonant inductances. Lo1 and Lo2 are the output inductances. D1 − D4 are the rectifier diodes. T1a − T2b are the isolated transformers. Co and Ro denote the output capacitance and load resistance, respectively. The proposed converter has two dc/dc circuits sharing the same power switches S1 − S4 , flying capacitor Cf , and freewheeling diodes Da and Db . Each dc/dc circuit includes a three-level ZVS converter and a half-bridge converter. The transformer secondary sides of these two converters are connected in series to reduce the voltage ripple across the output inductor. Thus, the output inductance Lo1 and Lo2 can be reduced. The pulsewidth modulated (PWM) signals of S1 and S4 are complementary each other with a dead time to allow ZVS operation. Similarly, the PWM signals of S2 and S3 are also complementary each other. The components Cin1 , Cin2 , Da , Db , Cf , S1 − S4 , Cr 1 – Cr 4 , C1 a, Lr 1a , and T1a are the basic three-level PWM converter. Three voltage levels Vin , Vin /2, and 0 are generated on the terminal voltage vab . Since the average voltage of C1a is equal to Vin /2, three voltage levels Vin /2, 0 and –Vin /2 are generated on the primary side of T1a and inductor Lr 1a . The components Cf , S2 , S3 , Cr 2 , Cr 3 , C1b , Lr 1b , and T1b are an uncontrolled half-bridge converter with 50% duty cycle. Two voltage levels Vin /4 and –Vin /4 are generated on the primary side of T1b and inductor Lr 1b . In the same manner, three voltage levels Vin /2, 0 and –Vin /2 are generated on the primary side of T2a and inductor Lr 2a , and two voltage levels Vin /4 and –Vin /4 are generated on the primary side of T2b and inductor Lr 2b . The current rating of output inductors Lo1 and Lo2 is equal to Io /2. The center-tapped rectifiers are adopted at the secondary side to have only one diode conduction loss. Based on the resonant behavior by the output capacitance of MOSFETs and the resonant inductance (or leakage inductance of transformer), MOSFETs S1 − S4 can be turned on under ZVS. Compared with the conventional parallel three-level dc/dc converter with low output ripple current [see parallel connection of Fig. 1(b)], the proposed converter has less switch counts, clamped diodes and flying capacitor.

LIN AND CHUNG: NEW PARALLEL ZVS CONVERTER WITH LESS ACTIVE SWITCHES AND SMALLER OUTPUT INDUCTANCE

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and S4 and diodes D1 and D4 are conducting. Inductor currents iL r 1a > 0, iL r 1b > 0, iL r 2a < 0 and iL r 2b < 0. Mode 1 [t0 ≤ t < t1 ]: At t0 , switch S4 is turned off. Since iL r 1a > 0, iL r 1b > 0, iL r 2a < 0, and iL r 2b < 0, Cr 1 and Cr 4 are discharged and charged, respectively, via flying capacitor Cf in this mode. The rising slope of the drain-to-source voltage of S4 is limited by Cr 1 and Cr 4 . Thus, S4 is turned off under ZVS. Since Lo1 and Lo2 are large enough, the primary currents iL r 1a − iL r 2b are almost constant in this mode. The ZVS turnon condition of S1 is given as Cr Vin2 . (1) 2 This mode ends at t1 when vC r 4 = Vin /2 and vC r 1 = 0. The time interval in this mode is given as (Lr a + n2 Lo /2)[i2L r 1a (t0 ) + i2L r 2a (t0 )] ≥

nCr Vin Cr Vin ≈ iL r 1a (t0 ) − iL r 2a (t0 ) iL o1,m ax + iL o2,m ax (2) where iL o1,m ax and iL o2,m ax are the maximum value of inductor currents iL o1 and iL o2 , respectively. The delay time between S1 and S4 must be greater than Δt01 in order to turn on S1 under ZVS. Mode 2 [t1 ≤ t < t2 ]: At t1 , vC r 4 = Vin /2. Thus, the clamped diode Db is conducting and the capacitor voltage vC r 1 = 0. In this mode, the ac terminal voltages vab = vbc = Vin /2, va1b = Vin /2 and vbc1 = 0. Since the average capacitor voltages VC 1a = VC 2a = Vin /2 and VC 1b = VC 2b = Vin /4, the secondary voltages of T1a and T2a are equal to zero voltage. In the same manner, the secondary voltages of T1b and T2b are equal to Vin /(2n) and –Vin /(2n), respectively. Thus, the rectified voltages vrect1 = vrect2 = Vin /(2n) and the output inductor voltages vL o1 = vL o2 = Vin /(2n)–Vo < 0. The inductor currents iL o1 and iL o2 both decrease in this mode. At time t2 , S3 is turned off. Mode 3 [t2 ≤ t < t3 ]: At t2 , S3 is turned off. Since iL r 1a > 0, iL r 1b > 0, iL r 2a < 0, and iL r 2b < 0, Cr 2 and Cr 3 are discharged and charged, respectively. Thus, the rising slope of the drain-to-source voltage of S3 is limited by Cr 2 and Cr 3 so that S3 is turned off under ZVS. The ZVS turn-on condition of S2 is given as Δt01 = t1 −t0 =

Fig. 3.

Key waveforms of the proposed converter.

III. OPERATING PRINCIPLE Before the discussion of the proposed converter, the following assumptions are made to simplify the system analysis: 1) MOSFETs S1 − S4 , diodes D1 − D4 , and the clamped diodes Da –Db are ideal; 2) Cin1 and Cin2 are large enough to be considered as two voltage sources VC in 1 = VC in 2 = Vin /2; 3) Lo1 = Lo2 = Lo , Lr 1a = Lr 2a = Lr a , Lr 1b = Lr 2b = Lr b ; 4) turns ratio of T1a and T2a is n and turns ratio of T1b and T2b is n/2; 5) Cr 1 = Cr 2 = Cr 3 = Cr 4 = Cr , C1a = C2a = Ca , C1b = C2b = Cb and Ca , Cb Cr ; 6) C1a –C2b and Cf are large enough to be treated as five constant voltages VC 1a = VC 2a = VC f = Vin /2 and VC 1b = VC 2b = Vin /4; 7) Co is large enough to be considered as a constant output voltage; 8) the energy stored in the resonant inductances is greater than the energy stored in the resonant capacitances so that the ZVS turn-on of all switches can be achieved. Based on the on/off states of S1 − S4 , Da –Db , and D1 − D4 , the proposed converter has ten operation modes in a switching cycle. Fig. 3 shows the key waveforms of the proposed converter during one switching cycle. The equivalent circuits of these ten operation modes are shown in Fig. 4. Prior to t0 , MOSFETs S3

(Lr a + n2 Lo /2)[i2L r 1a (t2 ) + i2L r 2a (t2 )] + (Lr b + n2 Lo /8) Cr Vin2 . (3) 2 = Vin /2. The time interval in this

· [i2L r 1b (t2 ) + i2L r 2b (t2 )] ≥ At t3 , vC r 2 = 0 and vC r 3 mode is expressed as Δt23 = t3 −t2 = =

Cr Vin iL r 1a (t2 )+iL r 1b (t2 )−iL r 2a (t2 ) − iL r 2b (t2 )

nCr Vin nCr Vin ≈ . (4) 3[iL o1 (t2 ) + iL o2 (t2 )] 3(iL o1,m in + iL o2,m in )

The time delay td between S2 and S3 must be greater than Δt23 in order to turn on S2 under ZVS. Mode 4 [t3 ≤ t < t4 ]: At t3 , vC r 2 = 0. Since iL r 1a (t3 ) + iL r 1b (t3 ) − iL r 2a (t3 ) − iL r 2b (t3 ) > 0, the antiparallel diode of S2 is conducting. Thus, S2 can be turned on at this

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Fig. 4. Operation modes of the proposed converter during one switching cycle: (a) mode 1; (b) mode 2; (c) mode 3; (d) mode 4; (e) mode 5; (f) mode 6; (g) mode 7; (h) mode 8; (i) mode 9; and (j) mode 10.

LIN AND CHUNG: NEW PARALLEL ZVS CONVERTER WITH LESS ACTIVE SWITCHES AND SMALLER OUTPUT INDUCTANCE

moment to achieve ZVS. The ac terminal voltages vab = 0, vbc = Vin , va1b = 0, and vbc1 = Vin /2. In this mode, the secondary winding voltages vT 1a,s + vT 1b,s = vT 2a,s + vT 2b,s = 0 and D1 − D4 are all conducting. Thus, the inductor currents iL o1 and iL o2 are decreasing with the slope of –Vo /Lo . The primary inductor voltages vL r 1a = –vC 1a ≈ –Vin /2, vL r 1b = –vC 1b ≈ –Vin /4, vL r 2a = Vin − vC 2a ≈ Vin /2, and vL r 2b = Vin /2–vC 2b ≈Vin /4. The primary side currents iL r 1a − iL r 2b are expressed as iL r 1a (t) = iL r 1a (t3 ) −

Vin (t − t3 ) 2Lr a

iL r 1b (t) = iL r 1b (t3 ) −

Vin (t − t3 ) 4Lr b

iL r 2a (t) = iL r 2a (t3 ) +

Vin (t − t3 ) 2Lr a

iL r 2b (t) = iL r 2b (t3 ) +

Vin (t − t3 ). 4Lr b

(5)

diD 4 (t) nVin diD 1 (t) nVin = =− =− dt dt 4Lr a 16Lr b (6)

From (6), the relationship of Lr a and Lr b can be obtained as Lr a = 4Lr b . This mode ends at t4 when the diode currents iD 1 and iD 4 are decreased to zero. In this mode, the current variations on Lr 1a and Lr 2a are ΔiL r 1a = ΔiL r 2a ≈ Io /n and the current variations on Lr 1b and Lr 2b are ΔiL r 1b = ΔiL r 2b ≈ 2Io /n. The time interval in this mode is given as Δt34 = t4 − t3 ≈

2Lr a Io . nVin

(7)

In this mode, S1 and S2 are in the on-state and diodes D1 − D4 are conducting. Thus, the rectified voltages vrect1 = vrect2 = 0 and the inductor voltages vL o1 = vL o2 = -Vo . No power is transferred from input voltage source Vin to output load Ro . Thus, the duty loss in mode 4 is expressed as dloss,4 =

Δt34 2Lr a Io fs ≈ Ts nVin

zero voltage and Cr 4 is discharged from Vin /2 via capacitor Cf in this mode. The rising slope of the drain-to-source voltage of S1 is limited by Cr 1 and Cr 4 . Thus, S1 is turned off under ZVS. The ZVS turn-on condition of S4 is given as (Lr a + n2 Lo /2)[i2L r 1a (t5 ) + i2L r 2a (t5 )] ≥

Cr Vin2 . 2

(9)

This mode ends at time t6 when vC r 1 = Vin /2 and vC r 4 = 0. The time interval in this mode is expressed as nCr Vin Cr Vin ≈ . iL r 2a (t5 )−iL r 1a (t5 ) iL o1,m ax + iL o2,m ax (10) The time delay between S1 and S4 must be greater than Δt56 in order to turn on S4 under ZVS. Mode 7 [t6 ≤ t < t7 ]: At t6 , vC r 1 = Vin /2 and the clamped diode Da is conducting. Capacitor voltage vC r 4 = 0 due to vC f = Vin /2. The ac terminal voltages vab = vbc = Vin /2. Since the average capacitor voltages VC 1a = VC 2a = Vin /2, the primary and secondary winding voltages of T1a and T2a are all zero voltage. The secondary side voltages of T1b and T2b are Vin /(2n). Thus, the rectified voltages vrect1 = vrect2 = Vin /(2n). The output inductor voltages vL o1 = vL o2 = Vin /(2n)–Vo < 0 and iL o1 and iL o2 decrease in this mode. This mode ends at t7 when S2 is turned off. Mode 8 [t7 ≤ t < t8 ]: At time t7 , S2 is turned off. Since iL r 1a < 0, iL r 1b < 0, iL r 2a > 0, and iL r 2b > 0, Cr 2 and Cr 3 are charged and discharged, respectively. Thus, the rising slope of the drain-to-source voltage of S2 is limited by Cr 2 and Cr 3 so that S2 is turned off under ZVS. The ZVS turn-on condition of S3 is given as Δt56 = t6 −t5 =

The slopes of the diode currents iD 1 − iD 4 are given as

diD 3 (t) nVin diD 2 (t) nVin = = = . dt dt 4Lr a 16Lr b

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(8)

where Ts and fs are the switching period and switching frequency, respectively. Mode 5 [t4 ≤ t < t5 ]: At t4 , the diode currents iD 1 = iD 4 = 0. S1 and S2 are conducting in this mode and T1a − T2b are working as the forward type transformers. The ac-side voltages vab = 0, vbc = Vin , va1b = 0, and vbc1 = Vin /2. Since the average capacitor voltages VC 1a = VC 2a = Vin /2 and VC 1b = VC 2b = Vin /4, the rectified voltages vrect1 = vrect2 = Vin /n. The output inductor voltages vL o1 = vL o2 = Vin /n–Vo > 0 and iL o1 and iL o2 increase in this mode. Power is delivered from input voltage source Vin to output load Ro in this mode. The primary currents iL r 1a and iL r 1b decrease, and iL r 2a and iL r 2b increase in this time interval. Mode 6 [t5 ≤ t < t6 ]: At t5 , S1 is turned off. Since iL r 1a < 0, iL r 1b < 0, iL r 2a > 0, and iL r 2b > 0, Cr 1 is charged from

(Lr a + n2 Lo /2)[i2L r 1a (t7 ) + i2L r 2a (t7 )] + (Lr b + n2 Lo /8) × [i2L r 1b (t7 ) + i2L r 2b (t7 )] ≥ Cr Vin2 /2

(11)

This mode ends at t8 when vC r 2 = Vin /2 and vC r 3 = 0. The time interval in this mode is expressed as Δt78 = t8 −t7 = =

Cr Vin iL r 2a (t7 )+iL r 2b (t7 )−iL r 1a (t7 ) − iL r 1b (t7 )

nCr Vin nCr Vin ≈ . 3[iL o1 (t7 ) + iL o2 (t7 )] 3(iL o1,m in + iL o2,m in ) (12)

The delay time td between S2 and S3 must be greater than Δt78 in order to turn on S3 at ZVS. Mode 9 [t8 ≤ t < t9 ]: At time t8 , vC r 3 = 0. Since iL r 1a +iL r 1 b − iL r 2 a − iL r 2 b < 0, the antiparallel diode of S3 is conducting. Thus, switch S3 can be turned on at this moment to achieve ZVS. The ac terminal voltages vab = Vin , vbc = 0, va1b = Vin /2 and vbc1 = 0. Thus, the secondary winding voltages of T1a − T2b are all zero voltage and D1 − D4 are all conducting in this mode. Inductor currents iL o1 and iL o2 are decreasing with the slope of -Vo /Lo . The primary inductor voltages vL r 1a = Vin − vC 1a ≈ Vin /2, vL r 1b = Vin /2–vC 1b ≈Vin /4, vL r 2a = –vC 2a ≈ –Vin /2 and vL r 2b = −vC 2b ≈ –Vin /4. The primary currents can be expressed as

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iL r 1a (t) = iL r 1a (t8 ) +

Vin (t − t8 ) 2Lr a

iL r 1b (t) = iL r 1b (t8 ) +

Vin (t − t8 ) 4Lr b

iL r 2a (t) = iL r 2a (t8 ) −

Vin (t − t8 ) 2Lr a

iL r 2b (t) = iL r 2b (t8 ) −

Vin (t − t8 ). 4Lr b

Based on the volt–second balance on Lo1 and Lo2 , the output voltage can be obtained as Vin (0.5 + d − 2dloss,4 ) − Vf n Vin 4Lr a Io fs = − Vf 0.5 + d − n nVin

Vo =

(13)

The slopes of the diode currents iD 1 − iD 4 are given as diD 4 (t) nVin diD 1 (t) nVin = = = dt dt 4Lr a 16Lr b diD 3 (t) nVin diD 2 (t) nVin = =− =− . dt dt 4Lr a 16Lr b

(14)

This mode ends at t9 when the diode currents iD 2 and iD 3 are decreased to zero. The time interval in this mode is given as Δt89 = t9 − t8 ≈

2Lr a Io . nVin

(15)

In this mode, S3 and S4 are in the on-state and diodes D1 − D4 are conducting. The rectified voltages vrect1 = vrect2 = 0 in this mode. No power is transferred from input voltage source Vin to output load Ro . Thus, the duty loss in mode 9 is expressed as dloss,9 =

Δt89 2Lr a Io fs ≈ = dloss,4 . Ts nVin

The charge and discharge times of Cr 1 − Cr 4 in modes 1, 3, 6, and 8 are much less than the time intervals in modes 2, 4, 5, 7, 9, and 10. Thus, only modes 2, 4, 5, 7, 9, and 10 are discussed in this section. Since vC in 1 + vC in 2 = Vin and vC f = vC in 1 in mode 2 and vC f = vC in 2 in mode 7, the spite capacitor voltages can be derived as vC in 1 = vC in 2 = vC f = Vin /2. Based on the volt–second balance on (Lr 1a and T1a ), (Lr 1b and T1b ), (Lr 2a and T2 a) and (Lr 2b and T2b ), the average capacitor voltages VC 1a − VC 2b can be obtained as Vin , 2

VC 1b = VC 2b =

Io 2 (Vin /n − Vo − Vf ) 2Lr a Io fs + d− 2Lo fs nVin

iL o1,m ax = iL o2,m ax =

Io 2 (Vin /n − Vo − Vf ) 2Lr a Io fs − d− . (20) 2Lo fs nVin

iL o1,m in = iL o2,m in =

Since the average currents on capacitances Cr 1a − Cr 2b are zero, the average magnetizing currents of T1a − T2b are equal to zero. The magnetizing ripple currents can be obtained in modes 5 and 10 Vin (d − dloss,4 )Ts dVin Ts Lr a Io = − ΔiL m a ≈ 2Lm a 2Lm a nLm a ΔiL m b ≈

Vin (d − dloss,4 )Ts dVin Ts Lr a Io = − (21) 4Lm b 4Lm b 2nLm b

where Lm a and Lm b are the magnetizing inductances of T1a and T1b , respectively. The average and root-mean-square (rms) currents of rectifier diodes D1 − D4 are expressed as iD 1,av = iD 2,av = iD 3,av = iD 4,av ≈ Io /4

√ iD 1,rm s = iD 2,rm s = iD 3,rm s = iD 4,rm s ≈ Io /(2 2).

IV. CIRCUIT CHARACTERISTICS

VC 1a = VC 2a =

where Vf is the voltage drop on diode D1 − D4 , and d is the duty ratio of the ac-side voltages vab and vbc when S1 and S2 are both in the on-state or off-state. The output voltage Vo is a function of d, Vin , fs , Lr a , n, and Io . In steady state, the average output inductor currents are approximately balanced IL o1 = IL o2 = Io /2. The ripple currents of Lo1 and Lo2 are expressed as (Vin /n − Vo − Vf ) 2Lr a Io fs ΔiL o1 = ΔiL o2 = d− . Lo fs nVin (19) The maximum and minimum output inductor currents at steady state are expressed as

(16)

Mode 10 [t9 ≤ t < t0 + Ts ]: At time t9 , the diode currents iD 2 and iD 3 are decreased to zero. S3 and S4 are conducting in this mode and T1a − T2b are working as the forward type transformers. The ac-side voltages vab = Vin and vbc = 0. Since the average capacitor voltages VC 1a = VC 2a = Vin /2 and VC 1b = VC 2b = Vin /4, the rectified voltages vrect1 = vrect2 = Vin /n. The output inductor voltages vL o1 = vL o2 = Vin /n–Vo > 0 and iL o1 and iL o2 increase in this mode. The primary currents iL r 1a and iL 1b increase, and iL r 2a and iL r 2b decrease in this time interval. Power is delivered from input voltage source Vin to output load Ro in this mode. This mode ends at t0 + Ts when S4 is turned off. Then the circuit operations of the proposed converter during a switching period are completed.

Vin . 4

(17)

(18)

(22)

The voltage stresses of D1 − D4 can be obtained in modes 5 and 10 vD 1,stress = vD 2,stress = vD 3,stress = vD 4,stress ≈ 2Vin /n (23) If the ripple currents of S1 − S4 can be neglected, the rms currents of S1 − S4 approximate Io iS 1,rm s = iS 4,rm s ≈ √ , n 2

3Io iS 2,rm s = iS 3,rm s ≈ √ . n 2 (24) The voltage stress of S1 − S4 is equal to Vin /2. In mode 10, the inductor currents iL r 1a (t0 ) (or iL r 1a (Ts + t0 )) and iL r 2a (t0 )

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(or iL r 2a (Ts + t0 )) are expressed as dVin Ts iL o1,m ax Lr a Io Io = − + n 4Lm a 2nLm a 2n (Vo /n − Vo − Vf ) 2Lr a Io fs + d− 2nLo fs nVin

iL r 1a (t0 ) ≈ iL m a,m ax +

dVin Ts iL o1,m ax Lr a Io =− + n 4Lm a 2nLm a (Vo /n − Vo − Vf ) Io 2Lr a Io fs − − d− . 2n 2nLo fs nVin

iL r 2a (t0 ) ≈ −iL m a,m ax −

(25) From (1) and (25), the necessary resonant inductance Lr a to achieve ZVS turn-on of S1 and S4 is given as Lr a ≥

Cr Vin2 − n2 Lo /2. 2[i2L r 1a (t0 ) + i2L r 2a (t0 )]

(26)

In mode 2, the inductor currents iL r 1a (t2 ) − iL r 2b (t2 ) can be expressed as iL r 1a (t2 ) ≈

(Vo /n − Vo − Vf ) dVin Ts Lr a Io Io + − + 4Lm a 2nLm a 2n 2nLo fs 2Lr a Io fs (Vo + Vf − Vin /2n)Δt12 × d− − nVin nLo (Vo /n − Vo − Vf ) dVin Ts Lr a Io Io − + − 4Lm a 2nLm a 2n 2nLo fs 2Lr a Io fs (Vo + Vf − Vin /2n)Δt12 × d− + nVin nLo

iL r 2a (t2 ) ≈ −

iL r 1b (t2 ) ≈

(Vo /n − Vo − Vf ) dVin Ts Lr a Io Io + − + 8Lm b 4nLm b n nLo fs 2Lr a Io fs 2(Vo + Vf − Vin /2n)Δt12 × d− − nVin nLo (Vo /n − Vo − Vf ) dVin Ts Lr a Io Io − + − 8Lm b 4nLm b n nLo fs 2Lr a Io fs 2(Vo + Vf − Vin /2n)Δt12 × d− . + nVin nLo

Fig. 5. Measured waveforms of S 1 − S 4 at 100% load (a) V in = 750 V and (b) V in = 800 V.

4 or 9 at Vin = 750 V and Po = 1.5 kW is less than 5% dloss,4 =

iL r 2b (t2 ) ≈ −

2Lr a Io fs 2Lr a Po fs ≈ < 0.05. nVin 0.8Vin2

(29)

The maximum inductances Lr 1a − Lr 2a are obtained as: Lr 1a,m ax = Lr 2a,m ax = Lr a,m ax

dm in − ≈ 8.7 μH. ΔiL o1 fs nVin (33) We select Lo1 = Lo2 = 15 μH in the prototype. Based on (24), the rms currents and voltage stresses of S1 − S4 are given as Io iS 1,rm s = iS 4,rm s ≈ √ ≈ 16 A n 2 3Io iS 2,rm s = iS 3,rm s ≈ √ ≈ 4.7 A n 2

Fig. 8. Measured waveforms of gate voltage, drain voltage, and switch current of S 1 − S 4 at 25% load.

VS 1,stress = VS 2,stress = VS 3,stress = VS 4,stress =

Vin,m ax = 400 V. 2

(34)

The IRFP460 MOSFETs with VDS = 500 V, ID ,rm s = 20 A, RDS, o n = 0.27 Ω, and Coss = 480 pF at 25 V are used for

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Fig. 10. Measured waveforms of diode currents and output inductor current at full load (a) iD 1 , iD 2 , and iL o 1 (b) iD 3 , iD 4 , and iL o 2 .

Fig. 11. Measured results of output inductor currents iL o 1 , iL o 2 , and iL o 1 + iL o 2 at full load condition.

vD 1,stress = vD 2,stress = vD 3,stress = vD 4,stress ≈ 2Vin,m ax /n = 2 × 800/14 = 114 V.

Fig. 9. Measured waveforms of gate voltage, drain voltage, and switch current of S 1 − S 4 at full load.

switches S1 − S4 . From (22) and (23), the average currents and voltage stresses of D1 − D4 are given as iD 1,av = iD 2,av = iD 3,av = iD 4,av ≈ Io /4 = 1500/48/4 ≈ 8A

(35)

The KCU30A30 fast recovery diode with VRRM = 300 V and IF = 30 A are used as the rectifier diodes D1 − D4 . Fast recovery diodes 30ETH06 are adopted for the clamped diodes Da and Db . The selected dc blocking capacitances, flying capacitance, and output capacitance are C1a = C2a = C1b = C2b = Cf = 0.47μF and Co = 4000 μF. Experimental results based on the above circuit parameters are presented to verify the effectiveness of the proposed converter. Fig. 5 shows the measured waveforms of the PWM signals of S1 − S4 at 25% load and full load, respectively. Fig. 6 gives the measured waveforms of the ac-side voltages and

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primary side inductor currents at full load and 750 V input voltage case. Three voltage levels Vin , Vin /2, and 0 are generated on ac-side voltages vab and vbc . If vab = Vin and vbc = 0, inductor currents iL r 1a and iL 1b both increase, and iL r 2a and iL r 2b decrease. On the other hand, inductor currents iL r 1a and iL 1b both decrease and iL r 2a and iL r 2b increase when vbc = Vin and vab = 0. The measured capacitor voltages vC 1a − vC 2b and vC f at full load and 750 V input voltage are given in Fig. 7. The average capacitor voltages vC 1a , vC 2a , and vC f are equal to Vin /2 and the average voltages vC 1b and vC 2b are equal to Vin /4. The measured gate voltage, drain voltage, and switch current of switches S1 − S4 at 25% load and 750 V input voltage are shown in Fig. 8. In the same manner, the measured gate voltage, drain voltage, and switch current of S1 − S4 at full load are shown in Fig. 9. It is clear that S1 − S4 are all turned on under ZVS from 25% load. Fig. 10 shows the measured waveforms of diode currents iD 1 − iD 4 and output inductor currents at full load. Fig. 11 gives the test results of output inductor currents iL o1 , iL o2 and iL o1 + iL o2 at full load condition.

VI. CONCLUSION A new soft switching dc converter for high input voltage and high load current applications is presented to have the features of ZVS turn-on for all active switches from 25% load to full load, low voltage stress of power switches, and low current stress of rectifier diodes and magnetic components. Three-level diode clamped circuit is adopted to limit the voltage stress of power MOSFETs at one-half of input voltage. Flying capacitor is used to balance two input capacitor voltages. For high load current applications, two circuit cells with the same power switches are adopted and connected in parallel at low voltage side in order to achieve load current sharing and to reduce the current stress of transformer windings, the rectifier diodes, and the output inductors. Only four switches are used in the proposed converter instead of eight switches in the conventional parallel three-level PWM converter. Each circuit cell includes one half-bridge converter and one three-level converter. The transformer secondary windings of two converters are connected in series in order to reduce the output inductor voltage. Thus, the output inductor current ripple in the proposed circuit can be reduced compared with the current ripple in the conventional three-level PWM converter. Based on the resonant behavior at the transition interval, all MOSFETs can be turned on under ZVS at the designed load ranges. Thus, the switching losses of power MOSFETs are reduced. Since MOSFETs with low voltage stress are used in the proposed converter so that the conduction losses on MOSFETs are also reduced. Two center-tapped rectifiers are used at the secondary side to have only one diode conduction loss. The main contributions of the proposed converter are low output inductor current ripple, less switch counts, and low switching losses compared with the conventional parallel three-level dc/dc converter. The drawback of the proposed converter is high cost compared with the conventional three-level ZVS converter for medium power applications. However, the cost of the proposed converter is lower than the parallel three-level ZVS converter for

high-power applications. Finally, experiments based on a power scale-down prototype with 1.5 kW rated power are provided to verify the circuit performance.

REFERENCES [1] H. Akagi and R. Kitada, “Control and design of a modular multilevel cascade BTB system using bidirectional isolated DC/DC converters,” IEEE Trans. Power Electron., vol. 26, no. 9, pp. 2457–2464, Sep. 2011. [2] A. Nami, F. Zare, A. Ghosh, and F. Blaabjerg, “A hybrid cascade converter topology with series-connected symmetrical and asymmetrical diodeclamped H-bridge cells,” IEEE Trans. Power Electron, vol. 26, no. 1, pp. 51–65, Jan. 2011. [3] J. R. Pinheiro and I. Barbi, “The three-level ZVS-PWM DC-to-DC converter,” IEEE Trans. Power Electron., vol. 8, no. 4, pp. 486–492, Jul. 1993. [4] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Perez, “A survey on cascaded multilevel inverters,” IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2197–2206, Jul. 2010. [5] B. R. Lin and C. L. Huang, “Analysis and implementation of a novel softswitching pulse-width modulation converter,” IET Proc. Power Electron., vol. 2, no. 1, pp. 90–101, 2009. [6] A. K. Jain and V. T. Ranganathan, “Sensing for IGBT protection in NPC three level converters—Causes for spurious trippings and their elimination,” IEEE Trans. Power Electron., vol. 26, no. 1, pp. 298–307, Jan. 2011. [7] D. Montesinos-Miracle, M. Massot-Campos, J. Bergas-Jane, S. GalceranArellano, and A. Rufer, “Design and control of a modular multilevel DC/DC converter for regenerative applications,” IEEE Trans. Power Electron., vol. 28, no. 8, pp. 3970–3979, Aug. 2013. [8] W. Li, Y. He, X. He, Y. Sun, F. Wang, and L. Ma, “Series asymmetrical half-bridge converters with voltage autoblance for high input-voltage applications,” IEEE Trans. Power Electron., vol. 28, no. 8, pp. 3665–3674, Aug. 2013. [9] F. Canales, P. Barbosa, and F. C. Lee, “A zero-voltage and zero-current switching three-level DC/DC converter,” IEEE Trans. Power Electron., vol. 17, no. 6, pp. 898–904, May 2002. [10] B.-R. Lin and C.-H. Chao, “Soft-switching converter with two series halfbridge legs to reduce voltage stress of active switches,” IEEE Trans. Ind. Electron., vol. 60, no. 6, pp. 2214–2224, Jun. 2013. [11] J. P. Rodrigues, S. A. Mussa, I. Barbi, and A. J. Perin, “Three-level zerovoltage switching pulse-width modulation DC–DC boost converter with active clamping,” IET Proc. Power Electron., vol. 3, no. 3, pp. 345–354, 2010. [12] W. Chen and X. Ruan, “Zero-voltage-switching PWM hybrid full-bridge three-level converter with secondary-voltage clamping scheme,” IEEE Trans. Ind. Electron., vol. 55, no. 2, pp. 644–654, Feb. 2008. [13] X. Ruan, D. Xu, L. Zhou, B. Li, and Q. Chen, “Zero-voltage-switching PWM three-level converter with two clamping diodes,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 790–799, Aug. 2002. [14] K. Jin and X. Ruan, “Zero-voltage-switching multiresonant three-level converters,” IEEE Trans. Ind. Electron., vol. 54, no. 3, pp. 1705–1715, Mar. 2007. [15] F. Liu, J. Yan, and X. Ruan, “Zero-voltage and zero-current-switching PWM combined three-level DC/DC converter,” IEEE Trans. Ind. Electron., vol. 57, no. 5, pp. 1644–1654, 2010. [16] X. Xie, J. Zhang, Z. Chen, Z. Zhao, and Z. Qian, “Analysis and optimization of LLC resonant converter with a novel over-current protection circuit,” IEEE Trans. Power Electron., vol. 22, no. 2, pp. 435–443, Apr. 2007. [17] C.-H. Chien, Y.-H. Wang, and B.-R. Lin, “Analysis of a novel resonant converter with series connected transformers,” IET Proc. Power Electron., vol. 6, no. 3, pp. 611–623, 2013. [18] K. H. Yi and G. W. Moon, “Novel two-phase interleaved LLC seriesresonant converter using a phase of the resonant capacitor,” IEEE Trans. Ind. Electron., vol. 56, no. 5, pp. 1815–1819, May 2009. [19] B. R. Lin and J. Y. Dong, “ZVS resonant converter with parallel–series transformer connection,” IEEE Trans. Ind. Electron., vol. 58, no. 7, pp. 2972–2979, Jul. 2011. [20] Y. Gu, Z. Lu, L. Hang, Z. Qian, and G. Huang, “Three-level LLC series resonant DC/DC converter,” IEEE Trans. Power Electron., vol. 20, no. 4, pp. 781–789, Jul. 2005.

LIN AND CHUNG: NEW PARALLEL ZVS CONVERTER WITH LESS ACTIVE SWITCHES AND SMALLER OUTPUT INDUCTANCE

Bor-Ren Lin (S’91–M’93–SM’02) received the B.S. degree in electronic engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988, and the M.S. and Ph.D. degrees in electrical engineering from the University of Missouri-Columbia, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings—Power Electronics and the Journal of Power Electronics. He has authored or coauthored more than 200 published technical journal papers in the area of power electronics. His current research interests include power-factor correction, multilevel converters, active power filters, and soft-switching converters. Dr. Lin is an Associate Editor of the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS. He was the recipient of the Research Excellence Awards in 2004, 2005, 2007, and 2011 from the College of Engineering and the National Yunlin University of Science and Technology. He received the Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, 2007 Taiwan Power Electronics Conference, 2009 IEEE–Power Electronics and Drive Systems Conference, and the 2012 Taiwan Electric Power Engineering Conference.

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Shih-Kai Chung received the M.S. degrees in electrical engineering from National Yunlin University of Science and Technology, Yunlin, Taiwan, in 2013. He is currently a Power Supply Engineer with National Yunlin University of Science and Technology. His current research interests include soft switching converters, dc–dc converters, power factor correction techniques, and switching-mode power supplies.

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New Parallel ZVS Converter With Less Active Switches and Smaller Output Inductance Bor-Ren Lin, Senior Member, IEEE, and Shih-Kai Chung

Abstract—This paper presents a new three-level zero-voltage switching (ZVS) dc/dc converter for high input voltage applications. There are two ZVS circuits in the proposed converter to share load current. Thus, the size of the output chokes is reduced. These two circuits use the same power switches. Thus, the proposed converter has less switch counts compared with the conventional parallel three-level ZVS dc/dc converter. In the proposed converter, each circuit combines one half-bridge converter and one three-level converter. The transformer secondary windings of two converters are connected in series to reduce the size of output inductor. The voltage stress of each power switch is limited at one-half of input voltage due to three-level circuit topology. Based on the resonant behavior by the output capacitance of active switches and the leakage inductance (or external inductance) at the transition interval, power switches are turned on at ZVS within the desired load range. Experiments based on a 1.5 kW prototype are provided to demonstrate the performance of the proposed converter. Index Terms—DC/DC power conversion, zero-voltage switching (ZVS).

I. INTRODUCTION HREE-LEVEL dc/dc converters/inverters [1]–[5] have been proposed to use low voltage stress MOSFETs with high switching frequency instead of insulated gate bipolar transistors (IGBT) for switching mode power supplies (SMPSs) in medium power applications or use low voltage stress IGBT with low switching frequency for ac motor drives and active power filters. Three-phase SMPS systems are normally used for medium power applications such as modern cloud power units. In order to meet the power quality demand, three-phase power factor correctors with one, four or six active switches have been proposed for the past twenty years. Therefore, threephase line currents are controlled to be sinusoidal waveforms with nearly unity power factor. Thus, the reactive power and line current harmonics are eliminated. Since power factor correctors with boost type voltage conversion are widely adopted in three-phase ac/dc converters, the dc bus voltage after the three-phase power factor corrector may be higher than 750– 800 V. Thus, MOSFETs with 900 V voltage stress can be used in the second stage dc/dc converters such as phase-shift full-

T

Manuscript received January 13, 2013; revised March 20, 2013, May 12, 2013, and August 18, 2013; accepted August 26, 2013. Date of current version February 18, 2014. This work was supported by the National Science Council under Grant NSC 102-2221-E-224-022-MY3. Recommended for publication by Associate Editor F. L. Luo. The authors are with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin 64002, Taiwan (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2013.2280451

bridge converters, or MOSFETs with 500 V or 600 V voltage stress can be adopted in the three-level dc/dc converters. The series connection of MOSFETs scheme and the three-level dc/dc converters [1]–[3] have been proposed to overcome high voltage stress problem. However, the balance issue of the voltage across the series switches at the static and dynamic load conditions is not easy to overcome. The semiconductor switches in three-level dc/dc converters can be reduced at one-half of the input voltage. In order to realize the low size, light weight and high circuit efficiency SMPS, three-level converters with zerovoltage switching (ZVS) or zero-current switching (ZCS) have been proposed in [6]–[13]. Three-level converters with auxiliary circuits [14], [15] have been proposed to extend ZVS operation range. However, the design procedure of the auxiliary circuit is very complicated. Series resonant converters [16]–[20] with variable switching frequency have proposed to regulate output voltage with the advantages of high voltage gain and high conversion efficiency. However, the resonant converters have a wider range of switching frequency from light load to full load. Thus, the magnetic components are very difficult to be designed at the optimal condition. A new parallel ZVS converter is presented in this paper to reduce the switch counts and decrease the output ripple current. For high load current and high input voltage applications, the conventional parallel three-level converter with fixed frequency PWM is usually adopted. There are eight power switches in the conventional parallel three-level converter. In the proposed converter, there are two dc circuit cells with the same MOSFETs. Thus, there are only four active switches in the proposed converter. Two dc circuit cells are connected in parallel at the secondary side for high load current applications so that the current stresses of the transformer windings, rectifier diodes and output inductors are reduced. Three-level ZVS converter is adopted in the primary side for high input voltage applications, such as three-phase ac/dc converter with/without power factor correction (PFC) so that MOSFETs with low voltage stress can be used in three-phase SMPS power units. In each circuit cell, one half-bridge converter and one three-level converter are adopted at the high voltage side and the transformer secondary windings of two converters are connected in series at low voltage side so that the voltage across the output inductors is reduced and the output inductor ripple current is decreased compared with the output inductor ripple current in the conventional three-level converter. Based on the resonant behavior by resonant capacitance and resonant inductance at the transition interval, MOSFETs can be turned on at ZVS. Finally, experiments with a 1.5 kW prototype are provided to verify the effectiveness of the proposed converter.

0885-8993 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information.

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Fig. 2.

Fig. 1. Circuit configuration: (a) conventional three-level dc converter; (b) three-level hybrid converter with low output ripple current.

II. CIRCUIT CONFIGURATION Fig. 1(a) shows the conventional three-level dc converter. In order to reduce the voltage stress of active switches at Vin /2, two clamped diodes and one flying capacitor are adopted in the circuit. Due to the added flying capacitor, two spilt input capacitor voltages can be automatically balanced in a switching cycle. The rectified voltage vrect at the secondary side has two voltage levels Vin /(2n) and 0. In order to further decrease the ripple current of output inductor, it is a way to reduce the voltage across the output inductor. Thus, one more half-bridge converter can be added to the conventional three-level dc converter as shown in Fig. 1(b). The voltage stress of active switches is also equal to Vin /2. Cf 1 , Cf 2 , S3 , S4 , T2 , and Lr 2 work as an uncontrolled half-bridge converter. Since the secondary windings of T1 and T2 are connected in series, two voltage levels, Vin /(2n1 )+Vin /(4n2 ) and Vin /(4n2 ), are generated on the rectified voltage vrect . Thus, the lower ripple current of output inductor can be obtained due to lower voltage across the output inductor compared with the conventional three-level dc converter. For high load current applications, the parallel dc/dc converters were usually adopted in industry power converters. However, these solutions will increase the circuit components and also reduce the circuit reliability. Fig. 2 shows the circuit configuration of the proposed ZVS converter. The voltage stress of all switches in Fig. 2 is equal to Vin /2. The input dc bus voltage Vin is obtained from a three-phase ac/dc converter with PFC. The dc input voltage Vin is about 750–800 V for a three-phase 380 Vrm s /480 Vrm s ac/dc converter. Cin1 and Cin2 are equal and large enough to have the equal voltages VC in 1 = VC in 2 = Vin /2. S1 − S4 are power MOSFETs with Vin /2 voltage stress. Thus, MOSFETs with 500 V voltage rating can be used in the proposed converter. Cr 1 − Cr 4 are the output capacitances of S1 − S4 ,

Circuit configuration of the proposed converter.

respectively. The average voltage of flying capacitor is VC f = Vin /2. C1a − C2b are dc blocking capacitances. The average capacitor voltages VC 1a = VC 2a = Vin /2 and VC 1b = VC 2b = Vin /4. Lr 1a − Lr 2b are the resonant inductances. Lo1 and Lo2 are the output inductances. D1 − D4 are the rectifier diodes. T1a − T2b are the isolated transformers. Co and Ro denote the output capacitance and load resistance, respectively. The proposed converter has two dc/dc circuits sharing the same power switches S1 − S4 , flying capacitor Cf , and freewheeling diodes Da and Db . Each dc/dc circuit includes a three-level ZVS converter and a half-bridge converter. The transformer secondary sides of these two converters are connected in series to reduce the voltage ripple across the output inductor. Thus, the output inductance Lo1 and Lo2 can be reduced. The pulsewidth modulated (PWM) signals of S1 and S4 are complementary each other with a dead time to allow ZVS operation. Similarly, the PWM signals of S2 and S3 are also complementary each other. The components Cin1 , Cin2 , Da , Db , Cf , S1 − S4 , Cr 1 – Cr 4 , C1 a, Lr 1a , and T1a are the basic three-level PWM converter. Three voltage levels Vin , Vin /2, and 0 are generated on the terminal voltage vab . Since the average voltage of C1a is equal to Vin /2, three voltage levels Vin /2, 0 and –Vin /2 are generated on the primary side of T1a and inductor Lr 1a . The components Cf , S2 , S3 , Cr 2 , Cr 3 , C1b , Lr 1b , and T1b are an uncontrolled half-bridge converter with 50% duty cycle. Two voltage levels Vin /4 and –Vin /4 are generated on the primary side of T1b and inductor Lr 1b . In the same manner, three voltage levels Vin /2, 0 and –Vin /2 are generated on the primary side of T2a and inductor Lr 2a , and two voltage levels Vin /4 and –Vin /4 are generated on the primary side of T2b and inductor Lr 2b . The current rating of output inductors Lo1 and Lo2 is equal to Io /2. The center-tapped rectifiers are adopted at the secondary side to have only one diode conduction loss. Based on the resonant behavior by the output capacitance of MOSFETs and the resonant inductance (or leakage inductance of transformer), MOSFETs S1 − S4 can be turned on under ZVS. Compared with the conventional parallel three-level dc/dc converter with low output ripple current [see parallel connection of Fig. 1(b)], the proposed converter has less switch counts, clamped diodes and flying capacitor.

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and S4 and diodes D1 and D4 are conducting. Inductor currents iL r 1a > 0, iL r 1b > 0, iL r 2a < 0 and iL r 2b < 0. Mode 1 [t0 ≤ t < t1 ]: At t0 , switch S4 is turned off. Since iL r 1a > 0, iL r 1b > 0, iL r 2a < 0, and iL r 2b < 0, Cr 1 and Cr 4 are discharged and charged, respectively, via flying capacitor Cf in this mode. The rising slope of the drain-to-source voltage of S4 is limited by Cr 1 and Cr 4 . Thus, S4 is turned off under ZVS. Since Lo1 and Lo2 are large enough, the primary currents iL r 1a − iL r 2b are almost constant in this mode. The ZVS turnon condition of S1 is given as Cr Vin2 . (1) 2 This mode ends at t1 when vC r 4 = Vin /2 and vC r 1 = 0. The time interval in this mode is given as (Lr a + n2 Lo /2)[i2L r 1a (t0 ) + i2L r 2a (t0 )] ≥

nCr Vin Cr Vin ≈ iL r 1a (t0 ) − iL r 2a (t0 ) iL o1,m ax + iL o2,m ax (2) where iL o1,m ax and iL o2,m ax are the maximum value of inductor currents iL o1 and iL o2 , respectively. The delay time between S1 and S4 must be greater than Δt01 in order to turn on S1 under ZVS. Mode 2 [t1 ≤ t < t2 ]: At t1 , vC r 4 = Vin /2. Thus, the clamped diode Db is conducting and the capacitor voltage vC r 1 = 0. In this mode, the ac terminal voltages vab = vbc = Vin /2, va1b = Vin /2 and vbc1 = 0. Since the average capacitor voltages VC 1a = VC 2a = Vin /2 and VC 1b = VC 2b = Vin /4, the secondary voltages of T1a and T2a are equal to zero voltage. In the same manner, the secondary voltages of T1b and T2b are equal to Vin /(2n) and –Vin /(2n), respectively. Thus, the rectified voltages vrect1 = vrect2 = Vin /(2n) and the output inductor voltages vL o1 = vL o2 = Vin /(2n)–Vo < 0. The inductor currents iL o1 and iL o2 both decrease in this mode. At time t2 , S3 is turned off. Mode 3 [t2 ≤ t < t3 ]: At t2 , S3 is turned off. Since iL r 1a > 0, iL r 1b > 0, iL r 2a < 0, and iL r 2b < 0, Cr 2 and Cr 3 are discharged and charged, respectively. Thus, the rising slope of the drain-to-source voltage of S3 is limited by Cr 2 and Cr 3 so that S3 is turned off under ZVS. The ZVS turn-on condition of S2 is given as Δt01 = t1 −t0 =

Fig. 3.

Key waveforms of the proposed converter.

III. OPERATING PRINCIPLE Before the discussion of the proposed converter, the following assumptions are made to simplify the system analysis: 1) MOSFETs S1 − S4 , diodes D1 − D4 , and the clamped diodes Da –Db are ideal; 2) Cin1 and Cin2 are large enough to be considered as two voltage sources VC in 1 = VC in 2 = Vin /2; 3) Lo1 = Lo2 = Lo , Lr 1a = Lr 2a = Lr a , Lr 1b = Lr 2b = Lr b ; 4) turns ratio of T1a and T2a is n and turns ratio of T1b and T2b is n/2; 5) Cr 1 = Cr 2 = Cr 3 = Cr 4 = Cr , C1a = C2a = Ca , C1b = C2b = Cb and Ca , Cb Cr ; 6) C1a –C2b and Cf are large enough to be treated as five constant voltages VC 1a = VC 2a = VC f = Vin /2 and VC 1b = VC 2b = Vin /4; 7) Co is large enough to be considered as a constant output voltage; 8) the energy stored in the resonant inductances is greater than the energy stored in the resonant capacitances so that the ZVS turn-on of all switches can be achieved. Based on the on/off states of S1 − S4 , Da –Db , and D1 − D4 , the proposed converter has ten operation modes in a switching cycle. Fig. 3 shows the key waveforms of the proposed converter during one switching cycle. The equivalent circuits of these ten operation modes are shown in Fig. 4. Prior to t0 , MOSFETs S3

(Lr a + n2 Lo /2)[i2L r 1a (t2 ) + i2L r 2a (t2 )] + (Lr b + n2 Lo /8) Cr Vin2 . (3) 2 = Vin /2. The time interval in this

· [i2L r 1b (t2 ) + i2L r 2b (t2 )] ≥ At t3 , vC r 2 = 0 and vC r 3 mode is expressed as Δt23 = t3 −t2 = =

Cr Vin iL r 1a (t2 )+iL r 1b (t2 )−iL r 2a (t2 ) − iL r 2b (t2 )

nCr Vin nCr Vin ≈ . (4) 3[iL o1 (t2 ) + iL o2 (t2 )] 3(iL o1,m in + iL o2,m in )

The time delay td between S2 and S3 must be greater than Δt23 in order to turn on S2 under ZVS. Mode 4 [t3 ≤ t < t4 ]: At t3 , vC r 2 = 0. Since iL r 1a (t3 ) + iL r 1b (t3 ) − iL r 2a (t3 ) − iL r 2b (t3 ) > 0, the antiparallel diode of S2 is conducting. Thus, S2 can be turned on at this

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Fig. 4. Operation modes of the proposed converter during one switching cycle: (a) mode 1; (b) mode 2; (c) mode 3; (d) mode 4; (e) mode 5; (f) mode 6; (g) mode 7; (h) mode 8; (i) mode 9; and (j) mode 10.

LIN AND CHUNG: NEW PARALLEL ZVS CONVERTER WITH LESS ACTIVE SWITCHES AND SMALLER OUTPUT INDUCTANCE

moment to achieve ZVS. The ac terminal voltages vab = 0, vbc = Vin , va1b = 0, and vbc1 = Vin /2. In this mode, the secondary winding voltages vT 1a,s + vT 1b,s = vT 2a,s + vT 2b,s = 0 and D1 − D4 are all conducting. Thus, the inductor currents iL o1 and iL o2 are decreasing with the slope of –Vo /Lo . The primary inductor voltages vL r 1a = –vC 1a ≈ –Vin /2, vL r 1b = –vC 1b ≈ –Vin /4, vL r 2a = Vin − vC 2a ≈ Vin /2, and vL r 2b = Vin /2–vC 2b ≈Vin /4. The primary side currents iL r 1a − iL r 2b are expressed as iL r 1a (t) = iL r 1a (t3 ) −

Vin (t − t3 ) 2Lr a

iL r 1b (t) = iL r 1b (t3 ) −

Vin (t − t3 ) 4Lr b

iL r 2a (t) = iL r 2a (t3 ) +

Vin (t − t3 ) 2Lr a

iL r 2b (t) = iL r 2b (t3 ) +

Vin (t − t3 ). 4Lr b

(5)

diD 4 (t) nVin diD 1 (t) nVin = =− =− dt dt 4Lr a 16Lr b (6)

From (6), the relationship of Lr a and Lr b can be obtained as Lr a = 4Lr b . This mode ends at t4 when the diode currents iD 1 and iD 4 are decreased to zero. In this mode, the current variations on Lr 1a and Lr 2a are ΔiL r 1a = ΔiL r 2a ≈ Io /n and the current variations on Lr 1b and Lr 2b are ΔiL r 1b = ΔiL r 2b ≈ 2Io /n. The time interval in this mode is given as Δt34 = t4 − t3 ≈

2Lr a Io . nVin

(7)

In this mode, S1 and S2 are in the on-state and diodes D1 − D4 are conducting. Thus, the rectified voltages vrect1 = vrect2 = 0 and the inductor voltages vL o1 = vL o2 = -Vo . No power is transferred from input voltage source Vin to output load Ro . Thus, the duty loss in mode 4 is expressed as dloss,4 =

Δt34 2Lr a Io fs ≈ Ts nVin

zero voltage and Cr 4 is discharged from Vin /2 via capacitor Cf in this mode. The rising slope of the drain-to-source voltage of S1 is limited by Cr 1 and Cr 4 . Thus, S1 is turned off under ZVS. The ZVS turn-on condition of S4 is given as (Lr a + n2 Lo /2)[i2L r 1a (t5 ) + i2L r 2a (t5 )] ≥

Cr Vin2 . 2

(9)

This mode ends at time t6 when vC r 1 = Vin /2 and vC r 4 = 0. The time interval in this mode is expressed as nCr Vin Cr Vin ≈ . iL r 2a (t5 )−iL r 1a (t5 ) iL o1,m ax + iL o2,m ax (10) The time delay between S1 and S4 must be greater than Δt56 in order to turn on S4 under ZVS. Mode 7 [t6 ≤ t < t7 ]: At t6 , vC r 1 = Vin /2 and the clamped diode Da is conducting. Capacitor voltage vC r 4 = 0 due to vC f = Vin /2. The ac terminal voltages vab = vbc = Vin /2. Since the average capacitor voltages VC 1a = VC 2a = Vin /2, the primary and secondary winding voltages of T1a and T2a are all zero voltage. The secondary side voltages of T1b and T2b are Vin /(2n). Thus, the rectified voltages vrect1 = vrect2 = Vin /(2n). The output inductor voltages vL o1 = vL o2 = Vin /(2n)–Vo < 0 and iL o1 and iL o2 decrease in this mode. This mode ends at t7 when S2 is turned off. Mode 8 [t7 ≤ t < t8 ]: At time t7 , S2 is turned off. Since iL r 1a < 0, iL r 1b < 0, iL r 2a > 0, and iL r 2b > 0, Cr 2 and Cr 3 are charged and discharged, respectively. Thus, the rising slope of the drain-to-source voltage of S2 is limited by Cr 2 and Cr 3 so that S2 is turned off under ZVS. The ZVS turn-on condition of S3 is given as Δt56 = t6 −t5 =

The slopes of the diode currents iD 1 − iD 4 are given as

diD 3 (t) nVin diD 2 (t) nVin = = = . dt dt 4Lr a 16Lr b

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(8)

where Ts and fs are the switching period and switching frequency, respectively. Mode 5 [t4 ≤ t < t5 ]: At t4 , the diode currents iD 1 = iD 4 = 0. S1 and S2 are conducting in this mode and T1a − T2b are working as the forward type transformers. The ac-side voltages vab = 0, vbc = Vin , va1b = 0, and vbc1 = Vin /2. Since the average capacitor voltages VC 1a = VC 2a = Vin /2 and VC 1b = VC 2b = Vin /4, the rectified voltages vrect1 = vrect2 = Vin /n. The output inductor voltages vL o1 = vL o2 = Vin /n–Vo > 0 and iL o1 and iL o2 increase in this mode. Power is delivered from input voltage source Vin to output load Ro in this mode. The primary currents iL r 1a and iL r 1b decrease, and iL r 2a and iL r 2b increase in this time interval. Mode 6 [t5 ≤ t < t6 ]: At t5 , S1 is turned off. Since iL r 1a < 0, iL r 1b < 0, iL r 2a > 0, and iL r 2b > 0, Cr 1 is charged from

(Lr a + n2 Lo /2)[i2L r 1a (t7 ) + i2L r 2a (t7 )] + (Lr b + n2 Lo /8) × [i2L r 1b (t7 ) + i2L r 2b (t7 )] ≥ Cr Vin2 /2

(11)

This mode ends at t8 when vC r 2 = Vin /2 and vC r 3 = 0. The time interval in this mode is expressed as Δt78 = t8 −t7 = =

Cr Vin iL r 2a (t7 )+iL r 2b (t7 )−iL r 1a (t7 ) − iL r 1b (t7 )

nCr Vin nCr Vin ≈ . 3[iL o1 (t7 ) + iL o2 (t7 )] 3(iL o1,m in + iL o2,m in ) (12)

The delay time td between S2 and S3 must be greater than Δt78 in order to turn on S3 at ZVS. Mode 9 [t8 ≤ t < t9 ]: At time t8 , vC r 3 = 0. Since iL r 1a +iL r 1 b − iL r 2 a − iL r 2 b < 0, the antiparallel diode of S3 is conducting. Thus, switch S3 can be turned on at this moment to achieve ZVS. The ac terminal voltages vab = Vin , vbc = 0, va1b = Vin /2 and vbc1 = 0. Thus, the secondary winding voltages of T1a − T2b are all zero voltage and D1 − D4 are all conducting in this mode. Inductor currents iL o1 and iL o2 are decreasing with the slope of -Vo /Lo . The primary inductor voltages vL r 1a = Vin − vC 1a ≈ Vin /2, vL r 1b = Vin /2–vC 1b ≈Vin /4, vL r 2a = –vC 2a ≈ –Vin /2 and vL r 2b = −vC 2b ≈ –Vin /4. The primary currents can be expressed as

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 7, JULY 2014

iL r 1a (t) = iL r 1a (t8 ) +

Vin (t − t8 ) 2Lr a

iL r 1b (t) = iL r 1b (t8 ) +

Vin (t − t8 ) 4Lr b

iL r 2a (t) = iL r 2a (t8 ) −

Vin (t − t8 ) 2Lr a

iL r 2b (t) = iL r 2b (t8 ) −

Vin (t − t8 ). 4Lr b

Based on the volt–second balance on Lo1 and Lo2 , the output voltage can be obtained as Vin (0.5 + d − 2dloss,4 ) − Vf n Vin 4Lr a Io fs = − Vf 0.5 + d − n nVin

Vo =

(13)

The slopes of the diode currents iD 1 − iD 4 are given as diD 4 (t) nVin diD 1 (t) nVin = = = dt dt 4Lr a 16Lr b diD 3 (t) nVin diD 2 (t) nVin = =− =− . dt dt 4Lr a 16Lr b

(14)

This mode ends at t9 when the diode currents iD 2 and iD 3 are decreased to zero. The time interval in this mode is given as Δt89 = t9 − t8 ≈

2Lr a Io . nVin

(15)

In this mode, S3 and S4 are in the on-state and diodes D1 − D4 are conducting. The rectified voltages vrect1 = vrect2 = 0 in this mode. No power is transferred from input voltage source Vin to output load Ro . Thus, the duty loss in mode 9 is expressed as dloss,9 =

Δt89 2Lr a Io fs ≈ = dloss,4 . Ts nVin

The charge and discharge times of Cr 1 − Cr 4 in modes 1, 3, 6, and 8 are much less than the time intervals in modes 2, 4, 5, 7, 9, and 10. Thus, only modes 2, 4, 5, 7, 9, and 10 are discussed in this section. Since vC in 1 + vC in 2 = Vin and vC f = vC in 1 in mode 2 and vC f = vC in 2 in mode 7, the spite capacitor voltages can be derived as vC in 1 = vC in 2 = vC f = Vin /2. Based on the volt–second balance on (Lr 1a and T1a ), (Lr 1b and T1b ), (Lr 2a and T2 a) and (Lr 2b and T2b ), the average capacitor voltages VC 1a − VC 2b can be obtained as Vin , 2

VC 1b = VC 2b =

Io 2 (Vin /n − Vo − Vf ) 2Lr a Io fs + d− 2Lo fs nVin

iL o1,m ax = iL o2,m ax =

Io 2 (Vin /n − Vo − Vf ) 2Lr a Io fs − d− . (20) 2Lo fs nVin

iL o1,m in = iL o2,m in =

Since the average currents on capacitances Cr 1a − Cr 2b are zero, the average magnetizing currents of T1a − T2b are equal to zero. The magnetizing ripple currents can be obtained in modes 5 and 10 Vin (d − dloss,4 )Ts dVin Ts Lr a Io = − ΔiL m a ≈ 2Lm a 2Lm a nLm a ΔiL m b ≈

Vin (d − dloss,4 )Ts dVin Ts Lr a Io = − (21) 4Lm b 4Lm b 2nLm b

where Lm a and Lm b are the magnetizing inductances of T1a and T1b , respectively. The average and root-mean-square (rms) currents of rectifier diodes D1 − D4 are expressed as iD 1,av = iD 2,av = iD 3,av = iD 4,av ≈ Io /4

√ iD 1,rm s = iD 2,rm s = iD 3,rm s = iD 4,rm s ≈ Io /(2 2).

IV. CIRCUIT CHARACTERISTICS

VC 1a = VC 2a =

where Vf is the voltage drop on diode D1 − D4 , and d is the duty ratio of the ac-side voltages vab and vbc when S1 and S2 are both in the on-state or off-state. The output voltage Vo is a function of d, Vin , fs , Lr a , n, and Io . In steady state, the average output inductor currents are approximately balanced IL o1 = IL o2 = Io /2. The ripple currents of Lo1 and Lo2 are expressed as (Vin /n − Vo − Vf ) 2Lr a Io fs ΔiL o1 = ΔiL o2 = d− . Lo fs nVin (19) The maximum and minimum output inductor currents at steady state are expressed as

(16)

Mode 10 [t9 ≤ t < t0 + Ts ]: At time t9 , the diode currents iD 2 and iD 3 are decreased to zero. S3 and S4 are conducting in this mode and T1a − T2b are working as the forward type transformers. The ac-side voltages vab = Vin and vbc = 0. Since the average capacitor voltages VC 1a = VC 2a = Vin /2 and VC 1b = VC 2b = Vin /4, the rectified voltages vrect1 = vrect2 = Vin /n. The output inductor voltages vL o1 = vL o2 = Vin /n–Vo > 0 and iL o1 and iL o2 increase in this mode. The primary currents iL r 1a and iL 1b increase, and iL r 2a and iL r 2b decrease in this time interval. Power is delivered from input voltage source Vin to output load Ro in this mode. This mode ends at t0 + Ts when S4 is turned off. Then the circuit operations of the proposed converter during a switching period are completed.

Vin . 4

(17)

(18)

(22)

The voltage stresses of D1 − D4 can be obtained in modes 5 and 10 vD 1,stress = vD 2,stress = vD 3,stress = vD 4,stress ≈ 2Vin /n (23) If the ripple currents of S1 − S4 can be neglected, the rms currents of S1 − S4 approximate Io iS 1,rm s = iS 4,rm s ≈ √ , n 2

3Io iS 2,rm s = iS 3,rm s ≈ √ . n 2 (24) The voltage stress of S1 − S4 is equal to Vin /2. In mode 10, the inductor currents iL r 1a (t0 ) (or iL r 1a (Ts + t0 )) and iL r 2a (t0 )

LIN AND CHUNG: NEW PARALLEL ZVS CONVERTER WITH LESS ACTIVE SWITCHES AND SMALLER OUTPUT INDUCTANCE

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(or iL r 2a (Ts + t0 )) are expressed as dVin Ts iL o1,m ax Lr a Io Io = − + n 4Lm a 2nLm a 2n (Vo /n − Vo − Vf ) 2Lr a Io fs + d− 2nLo fs nVin

iL r 1a (t0 ) ≈ iL m a,m ax +

dVin Ts iL o1,m ax Lr a Io =− + n 4Lm a 2nLm a (Vo /n − Vo − Vf ) Io 2Lr a Io fs − − d− . 2n 2nLo fs nVin

iL r 2a (t0 ) ≈ −iL m a,m ax −

(25) From (1) and (25), the necessary resonant inductance Lr a to achieve ZVS turn-on of S1 and S4 is given as Lr a ≥

Cr Vin2 − n2 Lo /2. 2[i2L r 1a (t0 ) + i2L r 2a (t0 )]

(26)

In mode 2, the inductor currents iL r 1a (t2 ) − iL r 2b (t2 ) can be expressed as iL r 1a (t2 ) ≈

(Vo /n − Vo − Vf ) dVin Ts Lr a Io Io + − + 4Lm a 2nLm a 2n 2nLo fs 2Lr a Io fs (Vo + Vf − Vin /2n)Δt12 × d− − nVin nLo (Vo /n − Vo − Vf ) dVin Ts Lr a Io Io − + − 4Lm a 2nLm a 2n 2nLo fs 2Lr a Io fs (Vo + Vf − Vin /2n)Δt12 × d− + nVin nLo

iL r 2a (t2 ) ≈ −

iL r 1b (t2 ) ≈

(Vo /n − Vo − Vf ) dVin Ts Lr a Io Io + − + 8Lm b 4nLm b n nLo fs 2Lr a Io fs 2(Vo + Vf − Vin /2n)Δt12 × d− − nVin nLo (Vo /n − Vo − Vf ) dVin Ts Lr a Io Io − + − 8Lm b 4nLm b n nLo fs 2Lr a Io fs 2(Vo + Vf − Vin /2n)Δt12 × d− . + nVin nLo

Fig. 5. Measured waveforms of S 1 − S 4 at 100% load (a) V in = 750 V and (b) V in = 800 V.

4 or 9 at Vin = 750 V and Po = 1.5 kW is less than 5% dloss,4 =

iL r 2b (t2 ) ≈ −

2Lr a Io fs 2Lr a Po fs ≈ < 0.05. nVin 0.8Vin2

(29)

The maximum inductances Lr 1a − Lr 2a are obtained as: Lr 1a,m ax = Lr 2a,m ax = Lr a,m ax

dm in − ≈ 8.7 μH. ΔiL o1 fs nVin (33) We select Lo1 = Lo2 = 15 μH in the prototype. Based on (24), the rms currents and voltage stresses of S1 − S4 are given as Io iS 1,rm s = iS 4,rm s ≈ √ ≈ 16 A n 2 3Io iS 2,rm s = iS 3,rm s ≈ √ ≈ 4.7 A n 2

Fig. 8. Measured waveforms of gate voltage, drain voltage, and switch current of S 1 − S 4 at 25% load.

VS 1,stress = VS 2,stress = VS 3,stress = VS 4,stress =

Vin,m ax = 400 V. 2

(34)

The IRFP460 MOSFETs with VDS = 500 V, ID ,rm s = 20 A, RDS, o n = 0.27 Ω, and Coss = 480 pF at 25 V are used for

LIN AND CHUNG: NEW PARALLEL ZVS CONVERTER WITH LESS ACTIVE SWITCHES AND SMALLER OUTPUT INDUCTANCE

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Fig. 10. Measured waveforms of diode currents and output inductor current at full load (a) iD 1 , iD 2 , and iL o 1 (b) iD 3 , iD 4 , and iL o 2 .

Fig. 11. Measured results of output inductor currents iL o 1 , iL o 2 , and iL o 1 + iL o 2 at full load condition.

vD 1,stress = vD 2,stress = vD 3,stress = vD 4,stress ≈ 2Vin,m ax /n = 2 × 800/14 = 114 V.

Fig. 9. Measured waveforms of gate voltage, drain voltage, and switch current of S 1 − S 4 at full load.

switches S1 − S4 . From (22) and (23), the average currents and voltage stresses of D1 − D4 are given as iD 1,av = iD 2,av = iD 3,av = iD 4,av ≈ Io /4 = 1500/48/4 ≈ 8A

(35)

The KCU30A30 fast recovery diode with VRRM = 300 V and IF = 30 A are used as the rectifier diodes D1 − D4 . Fast recovery diodes 30ETH06 are adopted for the clamped diodes Da and Db . The selected dc blocking capacitances, flying capacitance, and output capacitance are C1a = C2a = C1b = C2b = Cf = 0.47μF and Co = 4000 μF. Experimental results based on the above circuit parameters are presented to verify the effectiveness of the proposed converter. Fig. 5 shows the measured waveforms of the PWM signals of S1 − S4 at 25% load and full load, respectively. Fig. 6 gives the measured waveforms of the ac-side voltages and

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primary side inductor currents at full load and 750 V input voltage case. Three voltage levels Vin , Vin /2, and 0 are generated on ac-side voltages vab and vbc . If vab = Vin and vbc = 0, inductor currents iL r 1a and iL 1b both increase, and iL r 2a and iL r 2b decrease. On the other hand, inductor currents iL r 1a and iL 1b both decrease and iL r 2a and iL r 2b increase when vbc = Vin and vab = 0. The measured capacitor voltages vC 1a − vC 2b and vC f at full load and 750 V input voltage are given in Fig. 7. The average capacitor voltages vC 1a , vC 2a , and vC f are equal to Vin /2 and the average voltages vC 1b and vC 2b are equal to Vin /4. The measured gate voltage, drain voltage, and switch current of switches S1 − S4 at 25% load and 750 V input voltage are shown in Fig. 8. In the same manner, the measured gate voltage, drain voltage, and switch current of S1 − S4 at full load are shown in Fig. 9. It is clear that S1 − S4 are all turned on under ZVS from 25% load. Fig. 10 shows the measured waveforms of diode currents iD 1 − iD 4 and output inductor currents at full load. Fig. 11 gives the test results of output inductor currents iL o1 , iL o2 and iL o1 + iL o2 at full load condition.

VI. CONCLUSION A new soft switching dc converter for high input voltage and high load current applications is presented to have the features of ZVS turn-on for all active switches from 25% load to full load, low voltage stress of power switches, and low current stress of rectifier diodes and magnetic components. Three-level diode clamped circuit is adopted to limit the voltage stress of power MOSFETs at one-half of input voltage. Flying capacitor is used to balance two input capacitor voltages. For high load current applications, two circuit cells with the same power switches are adopted and connected in parallel at low voltage side in order to achieve load current sharing and to reduce the current stress of transformer windings, the rectifier diodes, and the output inductors. Only four switches are used in the proposed converter instead of eight switches in the conventional parallel three-level PWM converter. Each circuit cell includes one half-bridge converter and one three-level converter. The transformer secondary windings of two converters are connected in series in order to reduce the output inductor voltage. Thus, the output inductor current ripple in the proposed circuit can be reduced compared with the current ripple in the conventional three-level PWM converter. Based on the resonant behavior at the transition interval, all MOSFETs can be turned on under ZVS at the designed load ranges. Thus, the switching losses of power MOSFETs are reduced. Since MOSFETs with low voltage stress are used in the proposed converter so that the conduction losses on MOSFETs are also reduced. Two center-tapped rectifiers are used at the secondary side to have only one diode conduction loss. The main contributions of the proposed converter are low output inductor current ripple, less switch counts, and low switching losses compared with the conventional parallel three-level dc/dc converter. The drawback of the proposed converter is high cost compared with the conventional three-level ZVS converter for medium power applications. However, the cost of the proposed converter is lower than the parallel three-level ZVS converter for

high-power applications. Finally, experiments based on a power scale-down prototype with 1.5 kW rated power are provided to verify the circuit performance.

REFERENCES [1] H. Akagi and R. Kitada, “Control and design of a modular multilevel cascade BTB system using bidirectional isolated DC/DC converters,” IEEE Trans. Power Electron., vol. 26, no. 9, pp. 2457–2464, Sep. 2011. [2] A. Nami, F. Zare, A. Ghosh, and F. Blaabjerg, “A hybrid cascade converter topology with series-connected symmetrical and asymmetrical diodeclamped H-bridge cells,” IEEE Trans. Power Electron, vol. 26, no. 1, pp. 51–65, Jan. 2011. [3] J. R. Pinheiro and I. Barbi, “The three-level ZVS-PWM DC-to-DC converter,” IEEE Trans. Power Electron., vol. 8, no. 4, pp. 486–492, Jul. 1993. [4] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Perez, “A survey on cascaded multilevel inverters,” IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2197–2206, Jul. 2010. [5] B. R. Lin and C. L. Huang, “Analysis and implementation of a novel softswitching pulse-width modulation converter,” IET Proc. Power Electron., vol. 2, no. 1, pp. 90–101, 2009. [6] A. K. Jain and V. T. Ranganathan, “Sensing for IGBT protection in NPC three level converters—Causes for spurious trippings and their elimination,” IEEE Trans. Power Electron., vol. 26, no. 1, pp. 298–307, Jan. 2011. [7] D. Montesinos-Miracle, M. Massot-Campos, J. Bergas-Jane, S. GalceranArellano, and A. Rufer, “Design and control of a modular multilevel DC/DC converter for regenerative applications,” IEEE Trans. Power Electron., vol. 28, no. 8, pp. 3970–3979, Aug. 2013. [8] W. Li, Y. He, X. He, Y. Sun, F. Wang, and L. Ma, “Series asymmetrical half-bridge converters with voltage autoblance for high input-voltage applications,” IEEE Trans. Power Electron., vol. 28, no. 8, pp. 3665–3674, Aug. 2013. [9] F. Canales, P. Barbosa, and F. C. Lee, “A zero-voltage and zero-current switching three-level DC/DC converter,” IEEE Trans. Power Electron., vol. 17, no. 6, pp. 898–904, May 2002. [10] B.-R. Lin and C.-H. Chao, “Soft-switching converter with two series halfbridge legs to reduce voltage stress of active switches,” IEEE Trans. Ind. Electron., vol. 60, no. 6, pp. 2214–2224, Jun. 2013. [11] J. P. Rodrigues, S. A. Mussa, I. Barbi, and A. J. Perin, “Three-level zerovoltage switching pulse-width modulation DC–DC boost converter with active clamping,” IET Proc. Power Electron., vol. 3, no. 3, pp. 345–354, 2010. [12] W. Chen and X. Ruan, “Zero-voltage-switching PWM hybrid full-bridge three-level converter with secondary-voltage clamping scheme,” IEEE Trans. Ind. Electron., vol. 55, no. 2, pp. 644–654, Feb. 2008. [13] X. Ruan, D. Xu, L. Zhou, B. Li, and Q. Chen, “Zero-voltage-switching PWM three-level converter with two clamping diodes,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 790–799, Aug. 2002. [14] K. Jin and X. Ruan, “Zero-voltage-switching multiresonant three-level converters,” IEEE Trans. Ind. Electron., vol. 54, no. 3, pp. 1705–1715, Mar. 2007. [15] F. Liu, J. Yan, and X. Ruan, “Zero-voltage and zero-current-switching PWM combined three-level DC/DC converter,” IEEE Trans. Ind. Electron., vol. 57, no. 5, pp. 1644–1654, 2010. [16] X. Xie, J. Zhang, Z. Chen, Z. Zhao, and Z. Qian, “Analysis and optimization of LLC resonant converter with a novel over-current protection circuit,” IEEE Trans. Power Electron., vol. 22, no. 2, pp. 435–443, Apr. 2007. [17] C.-H. Chien, Y.-H. Wang, and B.-R. Lin, “Analysis of a novel resonant converter with series connected transformers,” IET Proc. Power Electron., vol. 6, no. 3, pp. 611–623, 2013. [18] K. H. Yi and G. W. Moon, “Novel two-phase interleaved LLC seriesresonant converter using a phase of the resonant capacitor,” IEEE Trans. Ind. Electron., vol. 56, no. 5, pp. 1815–1819, May 2009. [19] B. R. Lin and J. Y. Dong, “ZVS resonant converter with parallel–series transformer connection,” IEEE Trans. Ind. Electron., vol. 58, no. 7, pp. 2972–2979, Jul. 2011. [20] Y. Gu, Z. Lu, L. Hang, Z. Qian, and G. Huang, “Three-level LLC series resonant DC/DC converter,” IEEE Trans. Power Electron., vol. 20, no. 4, pp. 781–789, Jul. 2005.

LIN AND CHUNG: NEW PARALLEL ZVS CONVERTER WITH LESS ACTIVE SWITCHES AND SMALLER OUTPUT INDUCTANCE

Bor-Ren Lin (S’91–M’93–SM’02) received the B.S. degree in electronic engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988, and the M.S. and Ph.D. degrees in electrical engineering from the University of Missouri-Columbia, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings—Power Electronics and the Journal of Power Electronics. He has authored or coauthored more than 200 published technical journal papers in the area of power electronics. His current research interests include power-factor correction, multilevel converters, active power filters, and soft-switching converters. Dr. Lin is an Associate Editor of the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS. He was the recipient of the Research Excellence Awards in 2004, 2005, 2007, and 2011 from the College of Engineering and the National Yunlin University of Science and Technology. He received the Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, 2007 Taiwan Power Electronics Conference, 2009 IEEE–Power Electronics and Drive Systems Conference, and the 2012 Taiwan Electric Power Engineering Conference.

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Shih-Kai Chung received the M.S. degrees in electrical engineering from National Yunlin University of Science and Technology, Yunlin, Taiwan, in 2013. He is currently a Power Supply Engineer with National Yunlin University of Science and Technology. His current research interests include soft switching converters, dc–dc converters, power factor correction techniques, and switching-mode power supplies.