Abstract- Recent single-stage power factor correction (PFC). AClDC converters usually present a high storage capacitor voltage stress and voltage variation.
New Power Factor Correction AC/DC Converter with Reduced Storage Capacitor
Voltage A. LAzaro, A. Barrado, J. Pleite, E. Olias. Universidad Carlos Ill de Madrid Departamento de Tecnologia Electronica Grupo de Sistemas Electronicos de Potencia Avda. Universidad, 30; 2891 1, Leganes, Madrid, SPAIN Tel.: 34-1-6249428; FAX: 34-1-6249430 E-mail: alazaro@,in.g.uc3m.es Abstract- Recent single-stage power factor correction (PFC) AClDC converters usually present a high storage capacitor voltage stress and voltage variation. The Series Inductance Interval (SII) PFC converters allow obtaining a bulk capacitor voltage lower than the peak value of the line voltage and even lower than output voltage. In this paper the novel single-stage SII-B-2D PFC converter is presented. This topology combines as three main advantages a low value and not much variable storage capacitor voltage, input current harmonics under EN61000-3-2 Class D limits, and an advantageous component count.
I. INTRODUCTION The potential advantages in low power applications of single-stage power factor correction (PFC) AC/DC converters over the classical two stages approach are a lower cost and complexity. However, a reflection about the actual capabilities of present single-stage converters must be done. If universal line voltage operation and fast output voltage regulation are assumed, four are the aspects to measure the performance of the different PFC solutions. These are the following: A . Input current. The input current of a two stages approach is potentially sinusoidal. Harmonic regulations allow a harmonic content in line current, however, the compliance of the Class D limits would be the added value of single-stage PFC solutions. The future amendment 14 to EN61000-3-2 (it will be mandatory in January 2004) will force power supplies of “high impact products” as computers, PC monitors and television sets to comply with Class D limits. B. Energy storage. Because input energy is pulsating, in any power factor correction (PFC) AC/DC converter, an storage element is necessary to provide constant power to the load. If the wide voltage range of the universal input is transmitted to the storage capacitor voltage, the storage capacitor requires both, a large capacitance value and high voltage rating (>400V) to meet the hold-up time requirement. The two stages approach uses the control loop of the PFC stage to provide a storage capacitor voltage independent of both, the load power and the input AC voltage. In single-stage PFC converters, according to the storage problem, one interesting group of solutions [2-41 obtains a storage capacitor voltage clamped to the peak value of input voltage. However still a variation about 3 to 1 is produced and the rated voltage of the needed capacitors is 400V (the same value than in a Boost PFC front end of a
0-7803-7474-6/02/$17.00 02002 IEEE
two stage approach). In the simple solution proposed in [5], voltage values on storage capacitor below the peak of the input voltage are obtained (e.g. 100 VDc on storage capacitor for a line voltage of 120 VRMS).Although additional information about the variation of this voltage is not given, the obtained results are quite interesting. The reason is that storing energy at low voltage can result advantageous in order to minimize size and cost of the total storage capacitance necessary to satisfy the holdup time requirement. On the one hand, although more micro Farads must be used at low voltage to store the same quantity of energy, low voltage capacitors presents a lower size. On the other hand, a bigger number of capacitance values as well as a bigger number of rated voltage values are available in commercial low voltage series ( 4 00 VDc). Therefore, low voltage capacitors result better exploited, so, the size can be reduced C. Simplicity and component count. The raison d’&treof single-stage PFC ACDC converters has been to reduce the complexity and cost of the two stages approach in low power applications. According to this aspect, a solution hold a better position in the ranking if: 0 Only a simple feedback loop is needed to obtain a well regulated output voltage. Complex transformers: are not required, due to the high manufacturing cost. Some solutions can also be less attractive if the magnetic components are bigger and complex than those of the equivalent two stage approach. No extra components are added to the two stages approach and besides some of the converter components present a lawer sizes and cost. In the “current shaper” group of solutions [6-91, just a few components are added to a conventional DC/DC converter, therefore, from the point of view of simplicity, these converters can be considered as an advantageous solution.
D.Energy processing and efficiency. At first, the poorest performance falls on the two stages approach because the total power is processed twice as well as the discontinuous conduction mode (DCM) for the higher rms currents. In low power applications, a energy processing lower than two, allows obtaining an efficiency close to the two stages approach even in DCM operation. However, when the power value is increased the way in
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which the power is processed [lo] gains a higher weight than the single processing ratio. Then the two stage approach obtains the best results. If a revision of the prior art of low power PFC converters is done ([ 11-13] are very useful for this aim), it can be conclude that there is not a topology which optimizes the four PFC requirements at the same time. At best, the more interesting solutions achieve good results in two or three aspects and the rest of them do not force the solution to be rejected. Therefore, the concrete application would define which is the best solution. In this context, a new family of PFC converters has been recently proposed in [14]. These converters presents an overall good performance, because the storage capacitor voltage is held below the output voltage, therefore below the peak value of the line voltage, and its input line current comply with EN61000-3-2 Class D limits regardless of the load condition. The component count and simplicity are also advantageous and the efficiency values are competitive. In this paper a new topology of the Series Inductance Interval (SII) family of PFC converters is analyzed. PROPOSED AC/DC CONVERTER The proposed converter is shown in Fig.1. The main features and advantages can be summarized as follows: In this converter the magnetizing inductance of the transformer T I (LII if it is viewed at the primary winding and L12 if it is referred to the secondary winding) and the inductance L2 operate in discontinuous conduction mode (DCM).
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which components have a low voltage rating. In order to obtain a tightly regulated output voltage, a single control loop generates the duty cycle which is applied on both MOSFET. ENERGY PROCESSING All the converters of the family SI1 can be classified into I-IIIB type if the classification proposed in [16] is used. This method proposes a block diagram very useful to explain the internal energy flow of the SI1 converters. See
Fig. 2. Block diagram and energyflow in the SII-B-2D converter.
The inner Flyback converter placed in the position 2 takes the power from the line (branch 1 in Fig. 2.a). A portion of this energy (branch 0 in Fig. 2.a. and trace 0 in Fig. 2.b and 3.d) is directly delivered to the output through the series connection of DSI+,"x and DS1-2, so, this energy is processed once. "2
t I
t I
Control
m
Fig. I . Power stage and control loop of the Sll-B-2D converter.
The capacitor C1 provides the energy storage and it holds a voltage always lower than output voltage. Since the converter operates in DCM, the voltage on storage capacitor does not varies with the load power (see [15] for a theoretical explanation), moreover the variation of the storage capacitor voltage under universal input is lower than the variation of the line voltage. The input current complies with the EN61000-3-2 Class D limits regardless of the load power because of the DCM operation. The margin of compliance of the Class D limits as well as the power factor and the ratio of single processing energy can be selected by design. The DCM operation of the converter penalizes the conduction losses in the switches, however, the effect of this aspect on the overall efficiency is reduced because up to a 70% of the output power is processed only once. The component count is also favorable because the same number of power components than in a Boost-Flyback two stages approach is used. Moreover, the SII-B-2D converter presents a branch that transfers a low power level and
32%
Fig. 3. Line frequency theoretical waveforms.
3 54
The other portion of the input energy is stored in the (branch 0 in capacitor CI also through the diode DSI-AIJX Fig. 2.a). The components k,S2 and DSl-2 can be seen as a Boost converter (this is the reason for the name SII-B) which holds the position 1 of the block diagram. Along the whole line half-cycle, and complementarily to the single processing energy, the Boost converter feeds the output via DSI-2(branch 0in Fig. 2.a and trace 0in Fig. 2.b and Fig. 3 . 4 with the energy stored in capacitor CI. This energy is processed twice and its value equals the output power when input voltage reaches zero Volts. In Fig. 3.a it is shown how the duty cycle must vary with the line angle to keep the output voltage constant. The output voltage presents a fast dynamic response since the addition of the average currents through Dsl and DS2 is constant along the whole line half-cycle, see Fig. 3.d. The regulation EN61000-3-2 allows some distortion in the line current (in Fig. 3.b, a line current which complies with class D limits is shown). As a consequence of the input current distortion, a higher portion of single processing energy than in the case of sinusoidal line current can be obtained. In Fig. 3.c the evolution of the input power with the line angle is represented (bold black line). It can be seen, how the single processing power (area below the Po level) is wider than the 68% corresponding to sinusoidal line current (dashed line). Therefore, the double processing power (line-filled area in Fig. 3.c and Fig.3.d) can be lower than the 32%, so, the inner converter 1 have to transfer a low power level, and the low overall efficiency due to DCM operation can be improved. SWITCHING PROCESS The converter has two operation modes depending on the instantaneous magnitude of the input line voltage as it is illustrated in Fig. 4.The principal switching mode is Mode 2, therefore its corresponding switching process will be described in more detail.
1 ;,
0’
lo’ ,
ti i
‘20
Model
of this stage is d l . Stage 3: C1 is recharged with the L12 current. Along stage 2 the L2 current has been decreasing because the output voltage minus the storage capacitor voltage has been applied on it. When this current reaches the zero value, stage 2 finish and it begins to flow in the opposite sense. Therefore the current is flowing into CI and it is recharged (see Fig. 6.b). When the value of the current through C1is equal to the reset current of LI2,DSI-2switches off and the stage ends. The duration of the third stage is d2. Normalized duration
Stage 3
d
dl
4 4 4
Fig. 5. Mode 2 switchingfrequency theoretical waveforms. Equivalent circuit of each stage of the switching cycle.
Stage 4: “The Series Inductance Interval”. Once DS1-2 has switched off, LI2and L2 result connected in series and reset together. This stage is common to all the SI1 converters and gives them its name. Stages 3 and 4 allow the recharge of CI as it can be seen in Fig. 6.b. The normalized duration of the series inductance interval is d3. After this stage, as in any converter working in DCM, a dead time is produced. The duration is d4.
4
b)
Fig. 4. Switching modes along the line cycle.
A . Mode 2 switchingprocess. The main switching frequency waveforms together with the equivalent circuit of each stage are represented in Fig. 5. The switching process can be summarized as follows: Stage I : Si and Sz are On. L2 is magnetized with the voltage on storage capacitor and LII is magnetized with the input voltage. The duration of this stage normalized with the switching period is d. Stage 2: CI delivers energy through DSI-2. LZ resets through DSI-2and LI2via DSI-*”x and DSI-2connected in series. Therefore, each switching cycle, single processing energy and double processing energy flows through DS as it can be also seen in Fig.6.a. The normalized duration
Fig. 6.a) Single & Double energy processing and current through DsI.2. b) Energy delivered toCl and current through Dsl.Aux.
B. Mode 1 . For low values of the input voltage, L12 resets before than Lz. Therefore, L2 never inverts its current and C1 is not recharged. However, in this switching mode, output is also feed from the input and from the storage capacitor. The boundary between the operation modes 1 and 2 is reached when the reset time of L12 and L2 become equal, its
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parameter has no influence neither the input current waveform nor the storage capacitor voltage. This parameter has to be designed low enough to assure the DCM operation for full load and the lower input voltage, 84 VRMS.
value is given by (1).
where nl is the turns ratio of T I ( I n l ) , VG is the peak value of the line voltage, Vo is the output voltage and Vcl is the storage capacitor voltage. DESIGN GUIDELINES A . Design parameters. Three are the degrees of freedom to design the converter SII-B-2D, these are the turns ratio of T I and the value of the inductances LI2 and L2. However, normalizing the values of the inductances L I Zand L2 has been considered more useful to describe the design guidelines. The normalized design parameters are the following. 0 T I turns ratio. n, 0
=d?
(2)
Dimensionless load parameter.
-3
0%
3
where & is the load resistor and Ts is the switching
b)
period.
1
03 : :O
;
01s
Inductance ratio.
LL
01
0 05
,=L,,
(4)
0 3
L2
Since the equation which connects the storage capacitor voltage with the other circuit parameters is transcendental, mathematical software such as MathCAD@must be used and only numerical solutions can be obtained for each design. The evaluation repeatedly of the MathCAD@developed calculus program allows describing the effect of each dimensionless design parameter on the performance of the converter. Some of this information is represented in Fig.7 and 8. The ratio of the single processing power, Kp, has a close relation with the efficiency and also talks about the size of the inner converter 1. Therefore its use has been preferred to describe the performance of the design better than the use of theoretical efficiency models. Also the storage capacitor voltage and input current harmonic content have been taken into account. B. Design process.
In Fig. 7 it can be seen the input current wave shape for designs with a different single processing ratio, Kp. In order to get the highest efficiency, the best design corresponds to the highest value of Kp, while Class D limits are complained. The harmonic content of the input current for each KPvalue as well as the Class D limits are represented In Fig. 7.b. The influence of each design parameter is represented in Fig. 8 and can be summarized as follows: T I turns ratio. KP decreases slightly with nl, see Fig.8.c. However, the storage capacitor voltage depends strongly of nl as it can bee seen in Fig.8.a and 8.b. The higher nl is, the higher the storage capacitor voltage is obtained. 0 Dimensionless load parameter. The converter operates in DCM, therefore the dimensionless load
3
7
9
11
13
I3
Hamonk numb.r
Fig. 7. lnfruence of inductance ratio, a, on single processing ratio, K p , and an the input current waveform and harmonic content.
Inductance ratio. As it can be seen in Fig. 7 and Fig.8.q the input current waveform and KP depend strongly on the inductance ratio. A better input current waveform an therefore a wider margin with respect to the regulation limits are obtained for higher values of a. However high values of a implies low values of KP and therefore worse efficiencies. C.Preferred Design The storage capacitor is determined by its voltage value at high and low line. Storage capacitor voltage at low line, VC1(84VRMs). This value defines the needed capacitance to meet the hold-up time requirement and is given by (9, (storage capacitor discharge with a constant power load). (5) were HUT is the hold-up time, and Po is the output power. Storage capacitor voltage at high line, V c l ( 2 6 7 V ~ ~This ~ ) . value define the voltage rating of the storage capacitor. In order to obtain the lower storage capacitor size the design must get : A value of Vcl(84VRMS) as high as possible. This way a lower value of capacitance is needed. A value of VC1(267VRMS) as close as possible to the upper commercial rated value.
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specifications are listed below: 0 Output power: 1OOW. Output voltage: 56 VDc. AC line voltage: 187-265 VRMS,"European range".
Storage wpacila voltage l a 84 VRMsline wltaga
Table 3: Selected design parameters for the prototype. *
0
e
a
10
8
?I
nl=l
Inductance ratio a
storage Capacrtw voltage fw 267 v,
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s
.
.
.
l
lhne voltage
o
I
...,E
a=4 L~8.63pH
A . EN61 000-3-2 Compliance. The measured line current of the SII-B-2D converter is shown in Fig 9.a. According to the design parameters of Table 3, the converter presents a Kp value around 0.65 and the input current waveform complies with the Class D limits with a wide enough margin, as it can be seen in Fig 9.b.
I
lnductanoe rat80 a
Single proceosmg ratlo
K=O. 15
L12=47pH
6
1
1 4 35
3
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2
0
8
10
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t 25 -2 1.:
(2
inductancerat0 a
I
Fig. 8. Influence ofdesign parameters n, and
05
0
An example of good-performance design is shown in Table 1. In this design, a has been chosen lower enough to obtain a K p about the 70% and high enough to comply Class D limits. The value of nl has been selected to obtain a storage capacitor voltage at high line (267 VRMS)lower than the commercial rated voltage of 35V and a value of 18.8 V at low line (84 VRMS) in order to reduce the needed capacitance. Table 1 : Selected values for design parameters. nl=l.l
Kp=70a/o
K=0.064
a=2.5
L12=20p H
L2=8pH
V c 1 ( 8 4 V ~ s ) =18.8V Vc1(267Vms)
34V
The comparison of the size of the storage capacitor in the proposed solution and the corresponding one to a single-stage converter which storage capacitor voltage were clamped to the peak value of line voltage (clamped Vcl converters) is shown in Table 2. The needed capacitance has been obtained using (5) and miniature size series of commercial capacitor have been selected for the analysis. It can be seen in Table 2 how under universal input, the proposed SII-B-2D converter and its design obtains a lower size than the clamped VCl converters.
3
1-
7
5
9
11
13
15
H a m o n k Number
4
b)
Fig. 9. a) V ~ C rectified Z line voltage (100 V/div). iuNE, line current (0.5 A/div). Error amplifier output (duty cycle) (0.5 V/div, AC coupling). Time base 5 ms. b)Hannonic content and Class D limits.
B. Storage capacitor voltage. The measured variation of the storage capacitor voltage as a function of the load power and the input AC voltage has been represented in Fig. 10.a. The storage capacitor voltage is held around 28 VDc for 187 V and 34 VDc for 257 V AC line voltage, just a variation of 1.2 times. The measured variation with load power has been lower than a 2%. This low variation is due to the DCM operation of the converter. The low variation of the storage capacitor voltage, together with the use of 35V capacitors allows obtaining a size of the storage capacitor similar to the corresponding to a clamped Vcl converter for the European range. The needed capacitor size are exposed in Table 4 and the measured hold-up time is shown in Fig. 10.b. Under universal line voltage operation, the SII-B-2D converter takes advantage over the clamped VC, converters.
Table 2: Storage capacitor voltage size for a clamped Vcl converter and the proposed SII-B-2D converter. Hold-up time = I O ms and P0=100 W.
Clamped
ca acitance 142pF/400V
ca acitor 3x 47pF/400V
converter SII-B-2D
5.66mFl35V
2x 3300pF/35V
Volume (mm')
I6 x 31.5
19000
16 x 35.5
14275 Load Power (W)
a)
EXPERIMENTAL RESULTS A SII-B-2D converter for European input range has been developed to obtain the experimental results. The proposed design values are listed in Table 3, the other converter
b)
Fig. IO. a) Storage capacitor voltage variation. b) Hold up time measuremen I.
Under universal input conditions, the variation of the storage capacitor voltage is lower in the SII-B-2D
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80% for European input voltage range. The energy processing (lower than twice, Kp=70%) allows overcoming the potential low efficiency of the DCM operation which is responsible of the good performance of the converter. Finally, it can be seen, how the proposed converter present a good performance in the four features described in the introduction paragraph.
converter just 1.8 times (18.8V to 84V, see Table 1) against the 3 times of the clamped converters. For these converters, the storage capacitor voltage varies from 85.42 to 265.42. Table 4: Storage capacitor size in clamped VCIconverters and the prototype for European range. HUT = 10 ms and PO=100 W. Volume
V. REFERENCES IEC 1000-3-2:1995 + A.1:1997 + A.2:1998, EMC Part 3-2: “LimitsLimits for harmonic current emissions (equipment input current < 16 A per phase)”. 0. Garcia, J.A. Cobos, R. Prieto, P. Alou, J. Uceda. “Simple ACDC Converters to Meet IEC 1000-3-2”. IEEE APEC ’00. Pp. 487-493. N. Vazquez, C. Hernandez, R. Cano, J. Antonio, E. Rodriguez, J. Arau, “An efficient Single-Switch Voltage Regulator”, IEEE PESC ’00.Pp. 81 I816. Q. Zhao, J. Qian, F.C. Lee, “Single-stage Parallel Power Factor Correction ACDC Converters with Inherent Load Current Feedback”. IEEE APEC ’02. J.J. Spangler “A Power Factor Corrected, MOSFET, Multiple Output, Flyback Switching Supply”, PCI Proceedings, 1985. J. Sebastian, M.M. Hernando, P. Villegas, J. D i u , A. Fontan, ‘‘Input Current Shaper Based on the Series Connection of a Voltage Source and a Loss Free Resistor”, IEEE Applied Power Electronics conference (APEC) 1998. Pp. 461-467. L. Huber and h1.M. Jovanovic. “Single-stage, Single Switch, Isolated Power Supply Technique with Input Current Shaping and Fast Output.. Voltage Regulation for Universal Input-Voltage-Range Applications”. IEEE APEC ’97. Pp. 272-280. M Daniele, P. Jain, G. Joos. “A Single Stage Single Switch Power Factor Corrected ACIDC Converter”. IEEE INTELEC ’96. Pp. 216-222. F. Tsai, P. Markowski and E. Whitcomb, “Off-line Flyback Converter with input Harmonic Correction”. IEEE INTELEC ’96. Pp. 120-1.24. J. Zhang, M.M. Jovanovic, F.C. Lee, “Comparison between CCM Single.. Stage and Two-Stage Boost PFC Converters”, lEEE APEC ’99. Pp. 335341. 0. Garcia, J.A. Cobos, R. Prieto, P. Alou, J. Uceda, “Power Factor Correction: A Survey” IEEE PESC ‘01. Pp. 8 -13. C. Qiao, K.M. Smedley, “A Topology Survey of Single-Stage Power Factor Corrector with a Boost Type Input-Current-Shaper”. IEEE Transactions on Power Electronics, Vol.16, No.3, May 2001. Pp. 360-368. R. Redl, “Low Cost Line Harmonics Reduction”, IEEE APEC ‘95 Professional Seminar. A. Lazaro, A. Barrado, J. Pleite, R. Vazquez, E. Olias, “New Family of Single-Stage PFC Converters with Series Inductance Interval”. IEEI: PESC ’02. To be published in PESC 2002 R. Redl, L. Balogh, “Design Considerations for Single-Stage Power Factor Corrected Power Supplies with Fast Regulation of the Output Voltage”. IEEE APEC ’95. Pp. 454-458.
converter
C. Efficiency and dynamic response. The efficiency of the proposed converter is shown in Fig. 11.a. An the transient response in Fig. 11.b. I ” ’
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100
120
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1.3
Load Power (W)
a)
b)
Fig.[ I . a) Eficiency measured in the proto(ype. b) Dynnmical response. VRECT, rectified line voltage (100 v/div). iLlNE, line current (0.5 A/div). Duty cycle (0.5 V/div. AC coupling). IO, output current ( I Aldiv).
The use of Coolmos technology for the switch SI as well as the value of Kp allow obtaining this competitive efficiency values. Fig.,l 1.b shows the line current under a load step of 55% of amplitude. To obtain the shown fast dynamic of the converter, a single control loop (based on a low cost IC controller) has been used. Furthermore the same duty cycle is applied to both MOSFET. CONCLUSIONS In this paper, a new SI1 single-stage AC/DC PFC converter has been presented together with the main design guidelines and experimental results. The main advantages are the following: EN61000-3-2 Class D compliance. The prototype has obtained an experimental voltage value around 29 VDC on storage capacitor, for an output voltage of 56 VDC. The reduced variation with line voltage (
