New "Real" Bridgeless High Efficiency AC-DC Converter - IEEE Xplore

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Oct 14, 2010 - Abstract— In this paper, a new bridgeless single-phase ac–dc converter with a natural power factor correction (PFC) is proposed. Compared ...

New “Real” Bridgeless High Efficiency AC-DC Converter Abbas A. Fardoun1, Esam H. Ismail2, Mustafa A. Al-Saffar2, and Ahmad J. Sabzali2 1

2

Electrical Engineering Department University of United Arab Emirates P.O. Box 17555, Al-Ain, UAE

Electrical Engineering Department College of Technological Studies P.O. Box 35007, Al-Shaab, Kuwait 36051

Email: [email protected], [email protected], [email protected], [email protected] Abstract— In this paper, a new bridgeless single-phase ac–dc converter with a natural power factor correction (PFC) is proposed. Compared with existing single-phase bridgeless topologies, the proposed topology has the merits of less component counts. Other advantages include: simple structure, soft switching, common ground, electrical isolation, and simple control circuitry. The absence of an input diode bridge and the presence of only one diode in the current path during each stage of the switching cycle result in higher power density and less conduction losses; hence, improved thermal management compared to existing PFC rectifiers is obtained. The proposed topology is designed to work in resonant mode to achieve an automatic PFC close to unity in a simple and effective manner. Principle of operation and the feasibility of the proposed converter are provided. The measured efficiency of the proposed converter at low line (85-Vrms) line voltage is near 95%. Detailed experimental and simulation results are presented.

I.

5) input–output galvanic isolation cannot be easily implemented, and 6) due to floating ground, some topologies require additional diodes and/or capacitors to minimize EMI. In order to overcome most of these problems, a new bridgeless PFC circuit based on the modified Cuk is introduced in this paper. Compared with existing single-phase bridgeless topologies, the proposed topology has simple structure, low component count, galvanic isolation capability, a single control signal, and non-floating output. Hence, the proposed converter is cost effective, especially for low power applications. The converter components are fully utilized during the positive and negative ac-line cycle. Compared to the conventional bridgeless boost converter, the proposed converter offers a higher power factor and higher efficiency especially at low ac-line voltage condition (85 Vrms). II.

INTRODUCTION

Power supplies with active power factor correction (PFC) techniques are becoming necessary for many types of electronic equipment especially in the telecommunication and computer industries to meet harmonic regulations and standards, such as the IEC 61000-3-2. Also, higher power density and lower system cost are always very desirable features, especially for low power supplies. In addition, new energy saving initiatives (e.g., 80 PLUS) are forcing designers to search for new topologies to further reduce losses while keeping low input current harmonics and PFC capability. In response to these concerns, considerable research efforts have been directed toward the development of efficient bridgeless PFC circuit topologies [1]–[13]. A bridgeless PFC circuit allows the current to flow through a minimum number of switching devices compared to the conventional PFC circuit. Accordingly, the converter conduction losses can be significantly reduced, and higher efficiency and lower cost can be obtained. However, most of the previous proposed bridgeless PFC converters have at least one of the following drawbacks: 1) high components count, 2) components are not fully utilized over whole ac-line cycle, 3) complex control, 4) dc output voltage is always higher than the peak input voltage,

In this section, the topology derivation of the proposed converter is presented. Fig. 1a and Fig. 2b show a modified Cuk converter also known as a “Self-lift Cuk” converter. These converters were first reported in [14] as a new step-up converter topology while detailed analysis for the converter of Fig. 1a is reported in [15]-[17]. Referring to Fig. 1a, the converter can be manipulated to produce a positive output voltage from a negative input voltage as shown in Fig. 1b. Similarly, for the converter of Fig. 2a, it is possible to produce a negative output voltage from a negative input voltage as shown in Fig. 2b. Note that the converter of Fig. 1b and 2a have similar output characteristics and they are identical except for their input voltage polarity and switch drain-tosource connection. Therefore, it is possible to combine the two converters of Fig. 1b and 2a into a single bridgeless ac-dc PFC converter containing a bi-directional switch and an alternating input voltage source as shown in Fig. 3a. Likewise, the converter of Fig. 1a and 2b can be combined into a single bridgeless ac-dc PFC converter which offers an inverted output voltage polarity as shown in Fig. 3b. Unlike the conventional bridgeless PFC converters, all components in the proposed converter of Fig. 3 are fully utilized as there are no idle components during both the positive and negative ac-line

This work was supported in part by the United Arab Emirates University Research Affairs under Research Grant Contract # Seed-EE-2011.

978-1-4577-1216-6/12/$26.00 ©2012 IEEE

TOPOLOGY DERIVATION

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cycle. Also, no additional diodes or capacitors are added to the topology to filter out common mode noise since the output is not floating. It should be mentioned here that a similar converter to the proposed converter of Fig. 3a was recently reported in [18][19]. However, the converter in [18]-[19] utilizes an extra resonant inductor in series with capacitor C1; hence, its circuit operation is completely different than the proposed converter of Fig. 3a. Moreover, compared to the converter in [18], it is expected that the proposed converter of Fig. 3 offers a higher overall efficiency as it utilizes one less inductor. III.

PRINCIPLE OF OPERATION AND ANALYSIS

A. Principle of Operation The proposed converters of Fig. 3 are designed to operate in discontinuous-conduction-mode (DCM) during the switch turn-on interval and in resonant mode during the switch turnoff intervals. As a result, the switch current stress is similar to the conventional DCM PFC converter while the switch voltage stress is higher. Moreover, the two power switches Q1 and Q2 can be driven by the same control signal, which significantly simplifies the control circuitry. Referring to Fig. 3a, the switching conduction sequences are as follows: 1) during positive ac-line cycle, Q1-DQ2, D2, D1, X (all switches are off), and 2) during negative ac-line cycle, Q2-DQ1, D1, D2, X. On the other hand, the switching conduction sequences for the converter of Fig. 3b are as follows: 1) during positive acline cycle, Q1-DQ2, D1, D2, X, and 2) during negative ac-line cycle, Q2-DQ1, D2, D1, X. Thus, during each switching period Ts, the current path goes through only two or one semiconductor devices instead of three. As a result, the total conduction losses of the semiconductor devices will be considerably lower compared to the conventional bridgeless PFC converters. Furthermore, to avoid repetition, only the converter in Fig. 3a will be analyzed; however, a similar approach can be developed for the proposed converter in Fig. 3b. Also, due to the symmetry of the circuit, it is sufficient to analyze the circuit during the positive half-period of the acinput voltage.

Figure 1. Modified Cuk converter with: (a) Negative output polarity. (b) Positive output polarity.

Figure 2. Enhanced modified Cuk converter with: (a) Positive output. (b) Negative output.

To simplify the analysis, it is assumed that the converter of Fig. 3a is operating at steady-state condition. In addition, the following assumptions are made: input voltage is pure sinusoidal, ideal lossless components, the switching frequency (fs) is much higher than the ac line frequency (fl), and the output capacitor Co is large enough such that the output voltage can be considered constant over the whole line period. Based on these assumptions, the circuit operations in one switching period Ts in a positive ac-line cycle can be divided into four distinct topological stages. The four equivalent circuits of each topological stage and the key waveforms during one switching period are shown in Figs. 4 and 5, respectively. In order to perform the analysis and derive equations independent of any particular parameter, all equations derived in this paper are normalized using the following base quantities:

Figure 3. Proposed bridgeless ac-dc PFC converter with: (a) Positive output polarity. (b) Negative output polarity.

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where vac the input ac voltage, vC1 is the voltage across the capacitor element C1, iL1 is the current through the inductor element L1, and iQ-pk is the peak switch Q1. For a loss free converter, the output and the input power are equal. Based on the above definitions, a brief analysis of each topological stage, along with the important circuit equations is presented next. Stage 1[t0, t1], (Fig. 4a): This stage starts when the switch Q1 is turned-on. The body Diode of Q2 is forward biased by the inductor current iL1. Diode D1 is reverse biased by the voltage across C1, while D2 is reverse biased by the voltages vC1 + Vo. In this stage, the current through inductor L1 increases linearly with the input voltage, while the voltage across capacitor C1 remains constant at voltage vx. The normalized circuit equations are given by

Figure 4. Topological stages for the converter of Fig. 3a during one switching period Ts.



jL1 (t  t 0 )  m ac r (t  t 0 ) 

(6)



mC1 (t  t 0 )   m x 

(7)



jQ  pk  mac  

(8)

where mx = vx/Vo and  in the normalized length of this stage and it is given by 

   r (t 1  t 0 ) 

(9)

Stage 2[t1, t2] (Fig. 4b): This stage starts when switch Q1 is turned-off and diode D2 is turned-on simultaneously providing a path for the inductor currents iL1. As a result, diode D1 remains reverse biased during this interval. The series tank consisting of L1 and C1 are excited by the input voltage vac through diode D2 as shown in Fig. 4b. The stage ends when the resonant current iL1 reaches zero and diode D2 turns off with zero current. During this stage, capacitor C1 is charged until it reaches a peak value as shown in Fig. 5. The normalized resonant iL1(t) and vC1(t) can be respectively described as Figure 5. Topological Theoretical waveforms for the converter of Fig. 3a.

 

Base voltage  Output voltage, Vo  Base impedance  Zo 

 

Base current  Base frequency, f r 

L1  C1

Vo  Zo

r 1   2  2 L1 C1



(1)

mC1 (t  t1 )  (mac  1)  jQ  pk sin r (t  t1 )  A cos r (t  t1 )  (11)

(2)

Where A = mac + mx -1. The normalized length of this stage can be calculated as following

(3)



(4)

Stage 3[t2, t3] (Fig. 4c): during this stage diode D1 is forward biased to provide a path during the negative cycle of the resonating inductor current iL1. This stage ends when the inductor current reaches zero. Thus, during this stage diode D1 is switched on and off under zero current conditions. Assuming constant input voltage over a switching period, the capacitor is discharged until it reaches a voltage vx (Fig. 5). The normalized resonant iL1(t) and vC1(t) can be respectively described as

The normalized values of the input and output quantities are described as mac 

 jL1

vac v , mC1  C1 Vo Vo

i  L1 Zo , Vo

jQ  pk 

iQ  pk Vo



jL1 (t  t1 )  A sin r (t  t1 )  jQ  pk cos r (t  t1 )  (10)

(5)



Zo

319

 4 j Q  pk   r  t 2  t1   sin 1   4  j Q2  pk 

   

jL1 (t  t 2 )   (mac  m x ) sin r (t  t 2 ) 

(12)

(13)



mC1 (t  t 2 )  mac  (m ac  m x ) cos r (t  t 2 )  (14)

The normalized length of this stage can be calculated as following 

  r  t 3  t 2    

(15)

Stage 4[t3, t4) (Fig. 4d): during this stage all switches are in their off-state. The inductor current is zero while the capacitor voltage remains constant (vC1 = vx). It shall be noted that for this converter to operate as specified, the length of this stage must be greater than or equal to zero. Based on the analysis above, the complete normalized state-plane trajectory of the proposed converter could be constructed in the (mC1, jL1) state-plane. Fig. 6 shows the stateplane diagram in a switching period with (mC1, jL1) as state variables. Referring to Fig. 6, the direction of the arrows shows the variations of the normalized current and voltage during the switching period. The circled numbers reflect the stage number. The value of the normalized capacitor voltage mx can be found from Fig. 6 as: 

mx 

j Q2  pk 4

 mac 

(16)

B. Voltage Conversion Ratio M The voltage conversion ratio M=Vo/Vm in terms of circuit parameters can be obtained by applying the input-output power balance principle to the circuit of Fig. 3a. The average input power during one half-cycle (TL/2) of the ac-line voltage is, 2  Pin (t) TL / 2  TL

TL / 2



vac iL1 dt

(17)

vac  Re

(18)

The variable Re represents the emulated input resistance of the converter and it is derived as, 

Re 

2 L1 d12 Ts



(19)

where d1 is the switch Q1 duty-cycle. Evaluating (17) and applying the power balance between the input-output ports, the desired voltage conversion ratio M can be derived as, 

V d M o  1  Vm 2k

RL  2 Re

2 L1  K R L Ts

   

2  F

(22)

where F = fs/fr is the normalized switching frequency. The condition in (22) can be fulfilled if diodes D1 and D2 remains reverse biased during the fourth stage. Hence, the following condition must be also satisfied 

0  m D1  1 

(23)

where mD1 is the normalized voltage across diode D1. Since the inductor voltage is zero during the fourth stage and the normalized capacitor voltage (mC1) is equal to –mx, the normalized voltage across D1 can be expressed by the following bounds 

0  m ac  m x  1 

(24)

Substituting (16) in (24) gives, 

(20)

where Vm is the peak of the input ac-line voltage and the dimensionless conduction parameter K is defined by 

C. Boundaries Between CCM and DCM To ensure DCM operation, the length of the fourth stage must be greater than zero. Therefore, the following condition must be satisfied 

period Ts and it is given by iL1 

Note that (20) shows that the gain is directly proportional to the duty cycle, which simplifies the control of the proposed topology. Moreover, for a given operating point (M, RL), the emulated input resistance Re in (19) is constant when both d1 and Ts are kept constant. Thus, the converter presents a linear resistive load to the ac power line, which is the perfect condition for a unity power factor operation. In other words, similar to conventional PFC rectifiers, (18) shows that the input port of the proposed rectifier obeys Ohm’s law. Thus, the input current is sinusoidal and in phase with the input voltage. Hence, the power stage circuit of the converter of Fig. 3a can be represented by its large signal averaged model shown in Fig. 7. This model can be implemented in a simulation program to predict the steady state and large signal dynamic characteristics of the real circuit. Furthermore, the averaged model can greatly reduce the long computation time when it is implemented in simulation software.

0

where iL1 is the average input current over one switching



Figure 6. Normalized state-plane trajectories for the converter of Fig. 3a.

0  j Q  pk  2 

(25)

From (2), the maximum value of the peak switch current occurs when vac = Vm, and it is given by

(21)

320



J Q  pk 

  M

(26)

TABLE I. COMPONENT STRESSES FOR THE PROPOSED CONVERTER Peak voltage across switches Q1 and Q2

M2  M  M2

Peak voltage across diodes D1 and D2 Figure 7.

Large signal model of the proposed converter of Fig. 3a.

Substituting (20) and (26) into (25), the following condition for DCM is obtained: 2



K

1F    K crit  2

(27)

IV.

1

Tank capacitor C1 peak voltage during positive half line cycle

4M   2 4M 2

Tank capacitor C1 peak voltage during negative half line cycle

M2  M  M2

2 4

RL 2 M Re

Switches Q1 and Q2 rms current

D. Components Stresses Table I shows the semiconductors normalized peak voltage and current stresses for the proposed converter of Fig. 3a. Table I also shows the capacitors rms current stress. Voltages and currents are normalized with respect to the output voltage Vo and output load current Io, respectively. These equations are provided for design purposes.

2 4

Diodes D1 and D2 average current

1

TABLE II. COMPONENTS USED IN SIMULATION AND EXPERIMENTAL PROTOTYPE

SIMULATION AND EXPERIMENTAL RESULTS

A. Design Procedure In this section, a procedure for the converter design is presented for a given operating point. The highest values for  and  occur at peak input voltage. Worst case values must be taken into account to ensure that (22) is satisfied. It shall be noted that due to the resonant non-linear nature of the converter, an iterative design procedure is involved as follows:

a. Assume a natural frequency fr greater than fs (e.g., fr=1.1 fs) to gaurantee satisfaction of (22).

Tank inductor L1

100 H

Tank capacitor C1

65 nF

Filter inductor LF

1 mH

Filter capacitor CF

1 F

Output filter capacitors Co

470 F

Active switches Q1 and Q2

STY60NM60: 600 V, 60 A with RDS-ON = 50 m

Diodes D1 and D2

STTH5L06: 600 V, 5 A, with VF = 1.05 V

b. Find Kcrit from (27). c. Find L1 from (21) for a given K (e.g., K = 0.9 Kcrit). d. Calculate resonant capacitance C1. e. Calculate duty cycle d1 from (20). f. Calculate  and  from (9) and (12). g. Check for satisfaction of (22) and (27). h. Reiterate such that K is as close as possible to Kcrit without violating constraint of Equation(27) B. Simulation and Experimental results The converter of Fig. 3a has been simulated using PSPICE for the following input and output data specifications: vac = 85 Vrms, Vo = 240 V, Pout = 115 W, and fs = 50 kHz. The design procedure of Section IV.A has been followed to come up with the design components values. The values of the resonant tank have been rounded to the closet discrete off the shelf components. Moreover, an equivalent series resistor (ESR) of 30 m is placed in series with all the inductors and capacitors. Furthermore, PSPICE actual semiconductor models have been used to simulate the switches. Table II shows the details of the components used in the simulation for the above operating point. The switch duty-cycle (d1) is calculated at 40%.

A small high-frequency input filter (LF = 1 mH, and CF = 1 μF) is inserted to filter the pulsating high frequency inductor L1 ripple current. Fig. 8 shows the simulated voltage and current waveforms at full load condition. It can be observed from Fig. 8a that the input line current is in phase with the input voltage. Fig. 8b shows the unfiltered input current through tank inductor (iL1) and tank capacitor voltage (vC1) over the whole line period. It can be noticed that the capacitor voltage during the negative half line cycle is different from that during the positive half cycle. The asymmetry of vC1 is expected since the switching sequence during the positive acline cycle is different from the switching sequences during the negative ac-line cycle. Fig. 8c shows the tank inductor current and capacitor voltage waveforms over several switching cycles. The performance of the proposed converter of Fig. 3a has been verified by a laboratory prototype for the same operating point as the simulation and using the same components of Table II. The experimental waveforms of the converter at full load are depicted in Fig. 9. The output voltage, the input voltage, and the filtered line current (iac) waveforms are shown in Fig. 9a. The measured THD in filtered input current is about 5.7%.

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Fig. 9b depicts the unfiltered line current (iL1) and the voltage across the capacitor C1. The waveforms of iL1 and vC1 during a few switching periods at peak input voltage are depicted in Fig. 9c, which correctly demonstrates the operating mode and matches the simulated results. The measured efficiency at full-load is about 94.3% which can be further improved by improving the prototype layout and utilizing optimized components. It shall be mentioned that the measured efficiency includes losses in the input filter. V.

CONCLUSION

A new AC-DC converter and its topology derivation have been presented. The components of the proposed topology are fully utilized over the whole line cycle, hence higher efficiency and higher power density converter is attained. Analysis, component stresses and design constraints of the converter have been presented. State-plane diagram has been constructed which has been successfully used to analyze the proposed converter. An efficiency of 94.3% and a THD of 5% were obtained at a prototype level. An even higher efficiency can be expected with a professional set up. Experimental and simulated waveforms of the converter are also presented. REFERENCES

Figure 8. Simulated waveforms for the converter of Fig. 3a. [1]

Figure 9. Measured waveforms for the converter of Fig. 3a. (vac = 85 Vrms, Vo = 240 V, Po = 115 W)

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