Next Generation Field-Effect Transistors Based on 2D Black Phosphorus Crystal (Invited Paper) Kah-Wee Ang*, Zhi-Peng Ling, and Juntao Zhu Silicon Nano Device Lab, Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, Singapore 117582 * e-mail:
[email protected]
Abstract—Two-dimensional (2D) crystals emerge as a new class of semiconducting material which may potentially revolutionize future electronic devices. Unlike graphene, black phosphorus (BP) is a semiconductor which has a predicted direct bandgap that can be tuned from 0.3 eV in its bulk form to 2.0 eV when reduces to a monolayer thinness. The presence of a bandgap in BP makes it advantageous over graphene in facilitating good transistor switching action. Here, field-effect transistors based on multi-layer BP and high-k gate dielectric (HfO2) are demonstrated using CMOS-compatible processes. Respectable transistor characteristics are achieved including a room temperature hole mobility of ~413 cm2/Vs and a subthreshold slope of ~200 mV/dec. Good ohmic contacts with a low Schottky barrier height of ~130 meV is realized using nickel (Ni), which can be further reduced to ~20 meV through thermal annealing. The potential of achieving low contact resistance coupled with enhanced carrier transport properties makes BP a promising channel material for next generation nanoelectronic device applications. Keywords—Black phosphorus, 2D materials; Field-effect transistors.
I.
I NTRODUCTION
For over four decades, silicon (Si) has been used as the material to realize integrated circuit chip which is now ubiquitously used in almost all electronic products. Today, the physical dimension of transistor is quickly approaching its fundamental scaling limit and further transistor miniaturization is expected to encounter unprecedented challenges. The semiconductor industry therefore urgently needs new innovation in materials and devices to address key challenges as outlined in the International Technology Roadmap for Semiconductor. A primary research challenge lies with reducing the power consumption of chips by making the fundamental transistor building block more power efficient. Lowering the supply voltage would reduce power consumption but such approach usually compromises transistor speed performance. While alternative channel materials such as III-V compound semiconductor have higher carrier mobility, incorporating these channel materials in transistor is very challenging. Replacing silicon with a more superior channel material such as 2D layered crystals is a revolutionary change. Although preliminary works have been reported [1]-[20], the performance of such 2D transistors is still far from satisfactory. More works are also needed to address the lacks of a scalable and manufacturable approach to deposit large area 2D materials on silicon platform.
2D Transition Metal Dichalcogenides MoS2
WSe2
0
0.5
1.0
WS2
1.5
2.0
Bandgap (eV)
Figure 1. Bandgap energies of various 2D layered materials, which can be modified by tuning film thickness, strain, and/or perpendicular electrical field.
Although the widely explored pristine graphene shows an extremely high carrier mobility, the lacks of a bandgap makes it less favorable for transistor switching. Two-dimensional materials such as transition metal dichalcogenides (TMD) which are atomically thin and have tunable bandgap properties provide an option to build ultimately scaled channel (Fig. 1). Excellent gate control can be achieved, which addresses the issue of short channel effects in aggressively scaled transistors. This leads to an effective power consumption reduction. However, majority of the reported TMD transistors, such as molybdenum disulfide (MoS2) have a much lower carrier mobility performance over graphene or traditional semiconductors. The quest for a new material that bridges the gap between graphene and TMD is therefore needed. The rediscovery of black phosphorus (BP) offers attractive electronic properties including room temperature field-effect mobility of ~1000 cm2/Vs. BP is semiconducting in nature and has a layered crystal structure with puckered honeycomb coordination. Apart from its in-plane effective mass asymmetry and tunable bandgap, BP is also the most stable and least reactive phosphorus allotrope under standard processing conditions. When coupled with the ability to achieve low contact resistance, BP emerges as an attractive channel material for high performance FETs. In this paper, the development of next generation field-effect transistors based on 2D black phosphorus crystal and its associated metal-contacts will be presented. Important performance metrics in BP FETs such as carrier mobility, subthreshold slope and contact Schottky barrier height will be benchmarked against other TMD FETs.
The authors acknowledge funding support from the NUS Start-Up Grants (R-263-000-B21-133 and R-263-000-B21-731).
978-1-4799-8058-1/15/$31.00 ©2015 IEEE.
MoSe2
Graphene Black Phosphorus
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(a) HfO2
III.
(b)
A. Ohmic Contact Formation on BP using Nickel Fig. 3 shows the I-V curves for both the ohmic and Schottky contacts, in which a higher normalized current was clearly evident for the ohmic contact. To gain an insight into their Schottky barrier heights, temperature dependent I-V measurements were conducted and analyzed using the thermionic emission equation [22] which can be expressed as
BP
Ni
MULTI-LAYER BP TRANSISTOR CHARACTERISTICS
Ni
P+ Si
ܵܦܫൌ ݔ݁ ʹ ܶ כܣܣെ A2g
320
Intensity (a.u)
300
A1g
280
Si
B2g
260 240
Thin BP
220
Thick BP
200 180 160
SiO2/Si substrate only
140 300
350
400
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500
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Raman shift (cm-1)
600
Figure 2. (a) Fabrication process flow of the back-gated black phosphorus transistors starts with a highly doped p-type Si wafer. A 15 nm HfO2 high-k dielectric is deposited by the ALD approach, followed by the exfoliation of the black phosphorus layers with 10 nm thickness. EBL patterning and deposition of the Ni metal electrodes are performed followed by the deposition of a 30 nm SiO2 to protect the BP channel from ambient oxidation. (b) The top-view optical image of the back-gated BP transistor. (c) A typical Raman spectra scan of the black phosphorus crystal. (d) Thinner BP flake shows a left-shift of B2g and A2g peaks as compared to thicker BP flake.
30μ
Schottky Ohmic 20μ
BP TRANSISTOR FABRICATION FLOW
Fig. 2 shows the fabrication process flow for realizing the back-gated black phosphorus (BP) transistor. First, using a highly doped blanket p-type Si wafer, the native oxide is removed using a 2% concentration dilute HF dip prior to the deposition of a 15 nm hafnium-dioxide (HfO2) dielectric by atomic layer deposition (ALD) process (CambridgeNanoTech, Savannah Systems). This is followed by the exfoliation of the black phosphorus crystal (from HQGraphene) using the all-dry viscoelastic stamping technique [21]. Using a two-step exfoliation/transfer steps from tape to the viscoelastic material (Gelfilm from Gelpak) and finally onto the target substrate, the uniformity of the layered BP flakes can be significantly improved and the tape residue is kept to a minimum. A cleaning in acetone followed by isopropyl alcohol is then performed before the electron beam lithography (EBL) patterning of the source/drain contacts. Nickel metal electrodes deposition with a thickness of 100 nm is done by electron-beam evaporation (Oerlikon, Univex 450B). The remaining photoresist is then removed by the acetone lift-off process. Given that the black phosphorus material is prone to oxidation when exposed to the ambient, an additional EBL step is performed to protect the top surface of the BP channel using a 30 nm SiO2 deposited by electron-beam evaporation. Selected samples are further subjected to a rapid thermal annealing (RTA) process to study the influence of annealing conditions on the contact Schottky barrier heights.
ΦB = 0.13 eV
ΦB = 0.38 eV
25μ
400 K
15μ 10μ 5μ 0
150 K
-5μ -0.50
-0.25
0.00
0.25
0.50
Voltage (V) Figure 3. Temperature dependent I-V measurements for both the ohmic and Schottky contacts without applying gate bias.
T (K) 400
-22
300
250
200
150
175
VDS=0.1 V
2 -2 In [IDS/T ] (AK )
II.
(1)
where A is the contact area, A* is the Richardson constant, T is the temperature, q is the electron charge, kB is the Boltzmann constant, B is the Schottky barrier height, VDS is the applied channel bias, and n is the ideality factor. By plotting the Arrhenius plot of ln(IDS/T2) vs 1/T for different channel bias VDS, and getting the bias dependent slope S(VDS) at the linear region, the extraction of Schottky barrier height can be obtained by extrapolation to zero applied channel bias. Fig. 4 illustrates the above approach where a Schottky barrier height of ~130 meV was extracted. Additionally, Fig. 3 shows that at temperatures lower than ~150K, there is current saturation in the channel even with increasing bias, indicating that the tunneling component in the electrical transport plays a less dominant role as compared to the thermionic emission component evident at higher temperatures.
Current (A)
(d)
(c)
ݍ ܸܵܦ ൬ߔ െ ൰൨ ݇ܤ ܶ ܤ ݊
VDS=0.2 V
-23
VDS=0.3 V -24
VDS=0.4 V VDS=0.5 V
-25 -26
S(VDS) -27
2
3
4
5
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1000/T (K-1) Figure 4. Arrhenius plot of ln(IDS/T2) vs 1/T for increasing channel bias VDS from 0.1 V to 0.5 V, and zero back-gate bias. The slope is taken at the linear part of curve, and subsequently plotted as a function of applied VDS bias, and extrapolated to zero to obtain the Schottky barrier height.
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0.131
0.10 100 οC anneal 0.05
0.053
0.00
Ni
200 οC anneal
[3]
0.019
0.025
Ni
Ni
Co
Co/TiO2
MoSe2 FETs WSe2 FETs
[20]
0.1
μFE (cm /Vs)
Lch = 5μm
0.5
SS~216mV/dec 1.0
1.5
2.0
2
Lch = 21μm
2.5
IDS (A)
10
[10]
Width=8 μm
VBG -VT = -1.0 V
[8]
[6]
[11]
[19]
[17]
[7]
[20] [2]
[5] [18]
[1]
[16]
[12]
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BP FET on HfO2 MoSe2 FETs
1
BP FET on SiO2
BP FET on Al2O3
MoS2 FETs
WSe2 FETs
10
100
Channel Length (μm) Figure 9. A benchmark of hole mobility shows the achievement of enhanced carrier transport in BP transistors over TMD-based FETs.
35
Decreasing L ch
30
[9]
BP FET on HfO2 (this work)
VBG -VT = -0.5 V
40
[19]
1
100
10
45
[16]
This work
Figure 6. Transfer characteristics IDS-VBG (logarithmic scale) for VDS=-0.1V, and varying channel length for the BP field-effect transistors.
-1
[11]
Width=8μm
VBG (V)
Drain Current (μA μm )
[14]
1000
Lch=3 μm
This work
[18]
Channel Length (μm)
Lch = 3μm
50
[15] [8]
0.1
10-5
55
[12]
[9]
Figure 8. BP transistors on high-k dielectrics deliver improved subthreshold slope performance as compared to the conventional SiO2 dielectric.
VDS=-0.1V
0.0
[7]
[10] [5]
[13]
1
[17]
[6]
[1]
10-4
-0.5
[3]
BP FET on Al2O3 MoS2 FETs
Figure 5. A significant improvement in Ni/BP contact quality is evident from the significant reduction in the Schottky barrier at the Ni/BP interface upon a suitable RTP annealing process.
10-7
[2]
BP FET on HfO2
10
Contact metal
10-6
[4]
BP FET on SiO2
Reducing ΦB with anneal
Zero anneal
0.15
BP FET on HfO2 (this work)
0.206 [3]
SS slope (V/dec)
Schottky barrier ΦB (eV)
This work
0.20
25 20 15
Lch=5 μm
B. Black Phosphorus FETs Characteristics
10 5 L =21 μm ch 0 -1.0
-0.8
-0.6
-0.4
-0.2
0.0
Drain-Source Voltage (V) Figure 7. Improved output characteristics IDS-VDS for shorter channel lengths and higher gate overdrives.
Fig. 5 compares the Schottky barrier heights (ΦB) of the various metal contacts formed on BP crystal. Good ohmic contact was demonstrated in this work using nickel (Ni) which shows a low ΦB of ~130 meV. When subject to thermal annealing at 200°C for 60s under N2 ambient condition, the ΦB was further reduced to ~20 meV. Although limited reports were found on the extracted ΦB for different metal candidates, our results still compare favorably with Kamalakar et al., [3] which utilizes Cobalt contacts (ΦB~130 meV) and Cobalt/TiO2 contacts (ΦB~25 meV).
Fig. 6 shows the transfer characteristics of the BP transistors demonstrated in this work with varying channel lengths (i.e. 3 μm, 5 μm, and 21 μm). As seen in the plot, BP FET with a shorter channel length of 3 μm shows a smaller threshold voltage (Vt) of ~1.8 V as compared to the 5 μm and 21 μm long channel devices which exhibit a Vt ~ 2.2 V. It is worthy to note that the high Vt seen in these devices are due to an un-doped BP channel and the use of a relatively thick HfO2 high-k of ~15nm. Further Vt optimization could be possible through metal-gate workfunction tuning and/or equivalent oxide thickness (EOT) scaling. Fig. 7 plots the corresponding output characteristics of the BP transistors with different channel lengths (Lch). Reducing the Lch and increasing the gate overdrive (VBG-VT) have been shown to deliver improved drive current performance. For a channel bias of VDS=-1.0 V, the measured drive current is approaching 50 μA/μm for a VBG-VT of -1.0 V. Fig. 8 shows the subthreshold slope benchmark of the BP transistors demonstrated in this work over previously reported
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transition metal dichacolgenides (TMD) based transistors (MoS2, MoSe2, WSe2) [1]-[20]. In general, BP transistors utilizing high-k gate dielectrics such as HfO2 and Al2O3 exhibit improved subthreshold slope over other BP transistors fabricated on conventional SiO2 gate dielectric (>1 V/dec). A respectable SS slope of ~200 mV/dec was achieved in this work as compared to other previously reported BP and TMD-based transistors. A benchmark of the field-effect hole mobility performance for BP and TMD-based transistors is summarized in Fig. 9. This work achieved a record-high hole mobility of ~413 cm2/Vs over other previously reported BP transistors with high-k gate dielectric. In general, BP transistors demonstrated an enhanced carrier transport property as compared to other reported TMD transistors, showing potential as a new channel material for next generation electronic devices.
[5]
[6]
[7]
[8]
[9]
[10]
[11]
IV.
CONCLUSION
Multi-layer black phosphorus field-effect transistors were demonstrated with high-k gate dielectric (HfO2) using CMOScompatible processes. Superior carrier transport property was observed in BP crystals over other TMDs materials, where a hole mobility of ~413 cm2/Vs was achieved in this work. The BP FETs also demonstrated a respectable subthreshold slope of ~200 mV/dec, surpassing other BP transistors fabricated using SiO2 as the gate dielectric. Ohmic contacts with an ultra-low Schottky barrier height of ~20 meV were realized using nickel (Ni) as the metal contact. The ability to achieve low contact resistance coupled with enhanced carrier transport properties makes BP a potential channel material for next generation transistor applications.
[12]
[13]
[14]
[15]
[16]
ACKNOWLEDGMENT This research was supported by the NUS Start-Up Grants R-263-000-B21-133 and R-263-000-B21-731.
[17]
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