Nickel Silicide and Nickel Germanosilicide

ECS Transactions, 6 (1) 451-457 (2007) 10.1149/1.2727432, © The Electrochemical Society

Nickel Silicide and Nickel Germanosilicide Processing in a Near-Isothermal Cavity: Sheet Resistance Curves for Blanket Ni/Si and Ni/SiGe Substrates and Electrical Data for CMOS Devices Igor J. Malik, Michel Ouaknine, Takashi Fukada, Takeshi Ueda, Woo Sik Yoo, Patrick Pressa, and Robert Bindera a

WaferMasters, Inc., 246 E. Gish Road, San Jose, CA 95112, USA AMD Saxony LLC & Co. KG, Wilschdorfer Landstrasse 101, D-01109 Dresden, Germany

INTRODUCTION Nicket silicide (NiSi) and nickel germanosilicide (NiSiGe) have become preferred materials in CMOS technology for source and drain contacts and NiSi is being considered as a metal gate material as well [1-4]. With strain engineering demanding different types of strain for NMOS and PMOS transistors [5], Ni metal reacts with substrates that have a wide variety of properties (i.e., chemical composition, doping level, different crystalline phases). All of the relevant material combinations need to be taken into account when designing and optimizing an IC manufacturing process. The first part of this study was performed on 300 mm diameter blanket wafers and focuses on nickel silicide and nickel germanosilicide formation through Ni metal reactions with lightly doped single-crystal Si and Si0.8Ge0.2, respectively. The former is typically used for sources and drains for NMOS transistors (need tensile stress in the channel for electron mobility enhancement), the latter for PMOS transistors (need compressive stress in the channel for hole mobility enhancement). Sheet resistance data from blanket Ni/Si and Ni/Si0.8Ge0.2 wafers are used for identifying the IC process window. In the second part of this study, we used 300 mm diameter device wafers (K8 microprocessor, 65 nm design rule) and targeted four distinct annealing conditions that were chosen based on the blanket wafer experiments.

EXPERIMENTAL The Ni-Si and Ni-SiGe reaction was performed in a near-isothermal cavity annealing tool (SAO301LP, made by WaferMasters, Inc.). The tool schematic is shown in Figure 1; a more detailed description can be found in [6]. We focused on relatively slow kinetics of the reaction: all process times discussed in this study are 600s. The annealing was done predominantly by natural convection and heat conduction through a nitrogen environment with 350ºC would be interesting for establishing if we can obtain still lower device resistances without introducing unacceptable levels of structural defects. The electrical device trends (all device measurements were performed after processing the devices through metal 1) are shown in Figures 5-8. Figure 5 shows narrow (~110nm) and wide (~330 nm) active resistor trends as a function of the annealing conditions. The expectation that the 290ºC temperature is too low is confirmed. Actually, even 310ºC is an insufficient temperature for the completion of the nickel

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ECS Transactions, 6 (1) 451-457 (2007)

silicidation/ germanosilicidation process. 330ºC and 350ºC show a more satisfactory performance, both for the average resistance as well as the resistance variability.

c) Wide n-active line

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Figure 5: Narrow (~110 nm) and wide (~330 nm) active resistor performance for the four annealing conditions studied: a) narrow NMOS, b) narrow PMOS, c) wide NMOS, and d) wide PMOS. 290ºC and 310ºC are not sufficient for full silicidation/ germanosilicidation, while 330ºC and 350ºC show a satisfactory performance. For Figures 5-7: 290ºC - wafers #5,8; 310ºC – wafers #1,6,7; 330ºC – wafers #2,4; 350ºC – wafers #3,9.

Figure 6 shows small poly-Si lines with CD ~43-48 nm for both NMOS and PMOS devices. The trend is similar to the active resistors (shown in Fig. 5): satisfactory performance for 330ºC and 350ºC anneals but not for 290ºC and 310ºC.



a) Small n-type poly line



b) Small p-type poly line

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Figure 6: Small poly-Si line silicidation/ germanosilicidation data: a) NMOS, b) PMOS. 290ºC and 310ºC are not sufficient, while 330ºC and 350ºC show a satisfactory performance. The physical CD of the poly lines is ~43-48 nm.

Contact chain performance is shown in Figure 7. The chains studied consist of ~5,000 contacts that are alternatively connected to active area and metal 1. The results again show that 330ºC or 350ºC gives a significantly better performance than the lower processing temperatures.

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b) PMOS chain

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Figure 7: Chains consisting of ~5,000 contacts between active area and metal 1: a) NMOS, b) PMOS. 290ºC and 310ºC are not sufficient for full silicidation/ germanosilicidation, while 330ºC and 350ºC show a satisfactory performance.

Figure 8 shows metal 1 ring oscillator data: the current leakage as a function of the oscillator frequency. The more the curves are shifted to the right, the better the performance (for a particular oscillator speed,



there is less leakage). The trend shown is in agreement with the rest of the device data shown in Figures 5-7. The best performance is shown for 330ºC and 350ºC annealing conditions – the curves for these two temperatures virtually overlap.

Metal 1 Ring Oscillator

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OSCILLATOR SPEED (arb. units) Figure 8: Metal 1 ring oscillator data showing ~equivalent performance of devices processed at 330ºC and 350ºC. Devices processed at 290ºC show the worst performance, while devices processed at 310ºC are in between as far as the performance goes. [Note: Both x- and y-axes have linear scales.]

It is interesting to note that the metal 1 performance of the devices processed at 330ºC and 350ºC is ~equal and in some parameters slightly better than the POR (process of record). Since no optimization of the process integration was performed for the experiments described in this paper, we believe this shows a potential process improvement if the process can be re-optimized for the NiSi and NiSiGe annealing process (600s at ~330ºC - 350ºC or even higher temperatures).



CONCLUSIONS A near-isothermal cavity annealing was used for a NiSi & NiSiGe process on 300 mm blanket wafers and 65 nm microprocessors. Rs curves were obtained for both Ni/Si and Ni/Si0.8-Ge0.2 layers from the blanket wafers. Subsequently, four annealing conditions were chosen for 65 nm design rule microprocessors. 600s anneals at 330ºC and 350ºC for the NiSi & NiSiGe module are shown to provide metal 1 electrical performance equivalent or better to the optimized process of record. Further studies are planned that are going to address the potential for further improvement of the device performance.

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