Noise Induced Jitter Performance of Digitally ...

Noise Induced Jitter Performance of Digitally Controlled CMOS Delay Lines A

B

Mónica J. Figueiredo AB, Rui L. Aguiar B

Instituto Politécnico de Leiria, Escola Superior de Tecnologia e Gestão Universidade de Aveiro, Dpt. Electrónica e Telecomunicações / Instituto de Telecomunicações email: [email protected], [email protected]

Abstract — Analysing the impact of noise sources on jitter performance of delay elements and lines is important for understanding the performance of controlled delay lines, buffered clock distribution networks, etc.. This paper presents simulation evaluation of theoretical work on noise induced jitter in CMOS delay lines. Because of the increasing switching noise and reduced power supply voltage, digitally controlled delay lines are increasingly important and the focus of this work. For these circuits, output capacitance and drivability of delay elements are key parameters for the design of low jitter delay lines. Also, it is shown that delay lines are more sensitive to low than to high frequency noise components. Simulation results are presented for a 0.35μm CMOS technology.

I. INTRODUCTION Noise has become a major problem in the design of digital integrated circuits. Since the operating voltage is decreasing roughly 20% per technology node [1], noise sensitivity is becoming an increasingly important issue in the design of functional devices and products. This is becoming more evident due to lower noise headroom in low-power devices, increasingly coupled interconnects, larger IR drop and ground bounce in the supply voltage, thermal impact on device off-currents and interconnect resistivities, mutual inductance, and substrate coupling. Noise is a key perturbation on the clock network, leading directly to jitter. This induced jitter, if greater than a certain threshold, may cause incorrect operation of the circuit. Since clock frequencies are becoming higher, timing jitter has increasingly tighter limitations, and thus electronic circuitry is increasingly affected by noise. Delay elements are often used in VLSI (Very Large Scale Integration) circuits for clock generation, distribution and synchronization. They are used in digital delay-locked loops (DLLs), digitally controlled oscillators (DCOs), buffered clock distribution networks, and deskew circuits. In the above mentioned applications, the delay element is one of the crucial components and its precision directly affects the performance of these circuits. Delay can be here controlled by either analog or digital means. Although analog control has been widely used in the past and is still commonly used for its performance and simplicity, the increasing noise levels in circuits have been driving the use of all digital architectures [2], which are traditionally seen as more resilient in terms of noise. However, technology evolution has changed somewhat this picture and noise is now a problem even in purely digitally controlled designs. In this paper, the relationship between design parameters of delay circuits and the output jitter, noise induced, will be analyzed. In section II a brief review of noise sources in

CMOS digital circuits will be presented. The relationship between noise and jitter in delay lines will be presented in section III. In section IV, the two most common architectures for digitally controlled delay lines are compared in terms of noise induced jitter and simulation results are presented. Section V provides conclusions. II. NOISE SOURCES IN CMOS DIGITAL CIRCUITS Physical noise arises from the discrete nature of electronic charge and from the stochastic nature of the electronic transport process. The most common types of physical noise impacting the frequencies of interest of actual digital systems are thermal; flicker; and shot noise. The most traditional expressions for the drain current noise spectral densities are given in Table I [3], where gt is the total transconductance at the bias point, g is a bias-dependent factor, q is the electron charge, ID is the forward junction current, and KF, AF and EF are fitting parameters from the Spice2 flicker noise model. For deep submicron devices, more accurate (but also more complex) expressions have already been developed and published but this is still an open research field [1]. Table I - Drain current noise spectral density. Thermal Noise Flicker Noise Shot Noise

s I thermal = 4k B T ggt s I flic ker = K F ( I DS )

AF

2

Cox Leff f

EF

s I shot = 2qI D

Noise processes are also characterized by their statistical properties. Thermal and shot noises are generally accepted as statistically stationary random processes, with constant mean and standard deviation. Thermal noise is usually characterized by gaussian distributions and shot noise tends toward a gaussian distribution, by the central limit theory. On the contrary, flicker noise is usually seen as a statistically non-stationary random process, which implies that its mean changes with time and its uncertainty on any period can not be reduced by averaging over longer periods. Digital circuits also create additional noise by virtue of their switching operation and the current changes thus induced. Digital circuit noise may be classified as power supply (switching noise and IR-drop noise); substrate; and coupling noise (crosstalk). Modeling these noise sources in large digital circuits is not a trivial task as they depend on the circuit’s switching activity, parasitics coupling, package inductance, etc. [4]. Substrate noise and crosstalk (both capacitive and inductive) are typically addressed proactively or by repair schemes, as proper floorplanning, layout and routing can minimize their effects.

III. TIMING JITTER IN DELAY CIRCUITS When developing a model for calculating a circuit’s output timing jitter from a given total noise spectral density, the most frequent approach has been the first passage time model (FPT) [5]. The FPT model applies to ideal inverter cells, assuming that subsequent stages in a series of gates begin to switch exactly when their input crosses a particular voltage for the first time. Therefore, a given amount of voltage noise will produce a variance in the time domain given by the slew rate of the input signal as shown in (1).

Dt 2 = Dv 2 × ( CL I L )

2

(1)

Voltage noise (like switching noise) may be introduced in a node by some coupling mechanism or it may be the result of noise currents (thermal, shot or flicker) integration in the node capacitance. Current noise integrates on the load capacitor (CL) over a time window of width td to form a voltage Dvn that modulates the threshold crossing time instant. Thus, the load filters out the noise’s high frequency components. Voltage noise variance will therefore be proportional to the total noise current variance (sI2), to the noise frequency and to the load capacitance (2).

Dvn =

1 td iL ( t ) dt Þ Dvn 2 » s2I C ò0

( wCL ) 2

(2)

If we look at these equations we can observe a twofold influence of the load capacitance in current noise induced jitter: a big capacitance results in lower current to voltage conversion but on the other hand, it implies a higher voltage to jitter conversion as it reduces the signal’s slew rate. Also, it must be pointed out that the output impedance is actually in parallel with the transistor’s parasitic reactances and thus, their relative magnitude will influence the current noise transfer from the active devices to the output load. If their magnitudes are similar, only a fraction of the total generated noise current will contribute to the output noise voltage (we have a current divider), as shown in Figure 1.

in(t) Zp

ZL

in (t ) =

i noise × Z p Z p + ZL

because a higher capacitance reduces the signal slew rate which increases noise sensibility but on the other hand it integrates better the noise current. However, current noise transfer (illustrated in Figure 1) was not considered in these equations, and in fact jitter will be affected by the output capacitance. On the contrary, the influence of switching and flicker noises in the output jitter is directly proportional to the output load capacitance. Table II – Noise induced jitter variance models. Induced by

Jitter variance

Thermal & Shot Noise

sw =

Flicker Noise

s flk = s I flk C LVdd (1 + b ) 2 I n sat - b I p sat

Switching Noise

s sw = Dvsw × C L

2

2

2

( 4k

B

(

T gz + 2 q ) × I n sat + b I p sat w × I n sat - b I p sat

)

(

(

2

2

2

(

(

(I

n sat

)

(1)

2

- b × I p sat

))

)

2

)

2

2

(1): b is a fitting parameter to reflect the short-circuit current during the threshold crossing and z relates the drain saturation currents to the transistor’s transconductance.

B. Delay Line noise Induced Jitter Fixed delay elements may be cascaded and associated to some sort of multiplexer to create a delay line (DL). The number of delay stages through which the input signal travels determines the total amount of delay. If the output load of the basic inverter, or its drive current, can be digitally adjusted, it is possible to control the output slew rate and thus create a variable delay through the inverter. This may be done with a digital shunt capacitor (SCI) inverter or with a current starved delay element. However, when maximum speed and power consumption are of concern, SCI is generally preferred [7]. In Figure 2 a DL with fixed elements associated to a multiplexer and a SCI are shown.

Figure 2 - Digitally controlled a) delay line; b) SCI.

The basic and most widely used delay element in digital circuits is the static CMOS inverter with a fixed or variable output load. Based on equations (1) and (2), noise induced jitter variance at the output of a basic inverter has been derived in [6] for thermal, shot, flicker and power supply noise sources. These equations are shown in Table II.

In a DL, if full cell switching is initiated when the input voltage reaches a certain threshold, the voltage noise of one stage simply shifts the timing of the beginning of the next. For independent noise sources, the total jitter variance at the end of N stages is just N times the individual variances induced by noise sources. However, the noise at the output of the first cell will be amplified by the second cell transconductance gain, filtered by its output capacitance and sum up with its intrinsic noise - there is a jitter amplification phenomenon and noise sources can not be considered totally independent. In this case, the total output noise variance will not be just the sum of the noise variance introduced by each cell (s2Jcell) and thus, will be higher than N*s2Jcell.

It is interesting to notice that the thermal noise induced jitter does not seem to depend on the load capacitance

Because binary weighted shunt capacitor inverters may achieve the same phase ranges as delay lines with fewer

Active Device

inoise

Zp: total parasitic reactance ZL: output load reactance

Figure 1 – Current noise transfer illustration.

A. Delay Cell Noise Induced Jitter

elements, there is a general belief that they produce less jitter as there is less jitter amplification and accumulation. However, the delay control in these lines is based on a variable output load, which affects the noise current to voltage conversion, the current noise transfer to the output and the noise to jitter conversion. On the other hand, if the SCI capacitance is MCL and we use equations presented in Table II, flicker and switching noise induced jitter will be M2 times higher than jitter at the output of a basic delay cell, while white noise current will have a reduced contribution to the overall output noise voltage (equation (3)) [6]. 2 2 sSCI = Dvout × ( MCL I L ) = s2w + M 2 × ( s2flk + s 2sw ) (3) 2

Moreover, when the delay is large in a SCI, the output slew rate is lower than the input slew rate and there is no shortcircuit current during the threshold crossing. This means that white noise induced jitter is smaller for higher delays in a SCI which is exactly opposed to what happens in a DL, where jitter grows with the length of the line due to noise accumulation and amplification. It is important to notice that this noise amplification phenomenon will occur only for the high frequency noise spectrum, as low frequency noise current is not amplified by the delay cells. In fact, if the noise period is higher than the signal’s rise/fall time, it will only have influence on the signal’s output slew rate. Thus, noise amplification occurs only for noise frequencies above the inverse of the mean signal’s rise/fall time [6]. IV. JITTER SIMULATION RESULTS The number of delay elements (N) in a DL, like the one presented in Figure 3, depends essentially on the load and on the transistors drivability of each element and may be calculated using a simple delay model for the basic inverter [8]. To build a SCI with the same delay, the total switched load capacitance should be M times bigger than the unit inverter load capacitance. Figure 4 shows the SCI model used, with neighbour sections driven in phase opposition to achieve balanced rise and fall times.

simulator from Dolphin Integration, with a 0.35mm AMS technology. A. Physical Noise Induced Jitter The noise effects can be simulated in the transient domain if the noise of each component can be simulated (a noise model or the noise spectrum is available). SMASH uses a method based on the inverse fast Fourier transform function of the noise spectrum. During transient simulation, the biasing condition is able to change and to modulate the power spectrum density shape of each noise component. Jitter performance of both lines has been evaluated using noisy transistors (generating thermal and flicker noise with a gain parameter) in order to obtain a better simulation precision. Thermal noise in parasitic resistances has not been considered. The lines have been designed to introduce the same delay, using N=8 cascaded inverters in the DL and two buffered delay stages in the SCI, and long term jitter has been obtained. This jitter measures the maximum change in a clock’s transition from its ideal over a large number of cycles, and may be described by its standard deviation or by its root mean square (rms) value. Simulation results presented in Figure 5 show that long term jitter standard deviation (StdDev) at the output of the DL is slightly inferior to the jitter observed at the output of the SCI, despite the higher number of delay elements (dashed lines). This means that the SCI lower output slew rate and higher noise current transfer overcomes the higher noise integration capacity of its output load. Also, as jitter sources are non-correlated between stages and the amplification parameter is small, jitter variance grows with the number of stages (N) and jitter standard deviation grown with the root of N. Delay Line LTJitter rms SCI Line LTJitter rms

Delay Line LTJitter StdDev SCI Line LTJitter StdDev

1,8E-11 1,5E-11 1,2E-11 9E-12 6E-12

Figure 3 – Delay Line with basic inverters.

3E-12

Thermal and Flicker Noise

0 IN

INV1 INV2 INV3 INV4 INV5 INV6 INV7 INV8 SCI1 Buf1 SCI2 Buf2

Figure 5 – Physical noise induced long term jitter.

Figure 4 - Shunt capacitor delay line with two bufered elements.

The number M was calculated using the same propagation time expressions used for the DL, and we have found that to achieve the same delay in both lines we should have M=N-4. This result has been used in simulation to evaluate the jitter performance of the lines, for different noise levels. Transient noise simulations have been performed with SMASH

The similarity of these results show that the use of a SCI should be considered when low-power is a major concern as it is expected to consume less than the DL (as it has fewer elements, with lower output slew rates), with comparable jitter performance. Simulation’s mean power consumption for the DL was measured to be 23% higher than for the SCI (Vdd= 3.3V; IRMS SCI = 297mA; IRMS DL = 241mA). The rms long term jitter exhibited higher values than the StdDev jitter, because it includes the mean jitter value. This

non-zero mean long-term jitter is a consequence of the limited bandwidth of the measurements (determined by simulation time) during which there is a low frequency nonzero mean noise. The rms jitter behaviour of these lines is interesting to analyse, because flicker noise is effectively a non-stationary process with varying mean and because in most synchronization problems we wish to measure relative uncertainty between two delay lines, in which they will certainly exhibit different (noise) mean values during each comparison period. If this is the case, we can see that the DL behaves better than the SCI, probably because of the higher output load of shunt capacitor inverters.

frequency spectrum. Results are shown in Figure 7, where we can also observe that jitter standard deviation grows almost linearly in both lines due to the strong correlation between noise sources during the travel time of a transition along the lines. Also, higher low frequency noise components lead to higher jitter, which is higher at the output of the SCI stages because of their lower output slew rate (higher capacitive load). However, as the SCI line has fewer elements, its performance ends up (again) being better in this situation with a lower output jitter. For a more uniform noise spectrum (FLN=1) the DL performs better than the SCI.

B. Switching Noise Induced Jitter

DL LTJitter StdDev FLN=1 SCI LTJitter StdDev FLN=1

To further compare both lines, we have introduced zero mean gaussian voltage noise in both Vdd and Vss lines, with the same absolute value in each instant but different signs, to simulate the known negative feedback effect of switching noise on decoupled power lines [4]. In Figure 6 we show the simulation results when white noise sources are used, with different cut-off frequencies (1GHz and 10GHz). DL LTJitter StdDev FC=1G SCI LTJitter StdDev FC=1G

DL LTJitter StdDev FLN=20 SCI LTJitter StdDev FLN=20

1,5E-10 1,2E-10 9E-11 6E-11 3E-11 0 IN

DL LTJitter StdDev FC=10G SCI LTJitter StdDev FC=10G


Figure 7 - Switching noise induced long term jitter, with different low frequency content (FLN=1; FLN=20).

6E-11 5E-11 4E-11

V. CONCLUSIONS

3E-11 2E-11 1E-11 0 IN


Figure 6 – Switching noise induced long term jitter, with different cut-off frequencies (FC=1GHz; FC=10GHz).

It’s evident from these results that the higher the noise bandwidth, the higher is the long term jitter for both lines. For the 1GHz case, although jitter grows faster in the SCI line (it has a higher voltage to jitter conversion) its final value is lower because it has less number of stages. Also, because the noise is a low frequency signal there will be some correlation in jitter components introduced along the stages and final jitter will be higher than what would be expected for uncorrelated noise sources (in Figure 6 the standard deviation is linear with N and not with the root of N). On the other hand, when we increase the noise bandwidth to 10GHz, the correlation factor decreases and jitter variance grows linearly with N. In this case, jitter grows faster in the SCI due to its higher capacitances, but its final performance is slightly better than the DL because it has fewer stages and thus less jitter accumulation. Jitter amplification does not seem to be a relevant parameter for this technology because it may be much lower than unity, as predicted in [6]. We have also varied the low frequency content of supply noise sources, applying a varying gain (FLN) in the low

In this paper, simulation results of noise induced jitter in two different digitally controlled delay lines are presented. Jitter induced by thermal and flicker noise has shown to have a superior impact in SCI jitter performance due to its higher output capacitance which results in a higher voltage to jitter conversion. However, a SCI exhibits less jitter than a DL if broad-band switching noise is present (although only slightly less) or if switching noise has significant low frequency content due to jitter accumulation. Moreover, it has been shown that the correlation between noise sources has a significant impact in jitter accumulation along a delay line. VI. REFERENCES [1] [2] [3] [4] [5]

[6] [7]

[8]

International Technology Roadmap for Semiconductors, ITRS 2005. Toshiyuki Okayasu, et al. “0.25 µm CMOS Circuit Technology for Precise GHz Timing Generator”, ITC 2002. T. Ytterdal, Y. Cheng, and T. A. Fjeldly, Device Modeling for Analog and RF CMOS Circuit Design: John Wiley & Sons, 2003. P. Larsson, "Power supply noise in future IC's: a crystal ball reading," in Proc. IEEE CICC, pp. 467-474, 16-19 May, 1999. T. Weigandt, "Low-phase-noise, low-timing-jitter design techniques for delay cell based VCOs and frequency synthesizers," Ph. D. dissertation, Univ. California, Berkeley, 1998. M. Figueiredo, Rui L. Aguiar, "Noise and Jitter in CMOS Digitally Controlled Delay Lines," in Proc. ICECS, Nice, Dec. 2006. P. Andreani, et al., "A Digitally Controlled Shunt Capacitor CMOS Delay Line," Analog Integrated Circuits and Signal Processing, Kluwer Academic Pub., vol. 18, pp. 89-96, 1999. T. Sakurai and R. Newton, "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas," IEEE JSSC, vol. 25, no. 2, pp. 584-594, 1999.