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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 2, FEBRUARY 2018

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Nonisolated High Gain DC–DC Converter for DC Microgrids M. Lakshmi and S. Hemamalini

Abstract—DC microgrids are popular due to the integration of renewable energy sources such as solar photovoltaics and fuel cells. Owing to the low output voltage of these dc power generators, high efficient high gain dc– dc converters are in need to connect the dc microgrid. In this paper, a nonisolated high gain dc–dc converter is proposed without using the voltage multiplier cell and/or hybrid switched-capacitor technique. The proposed topology utilizes two nonisolated inductors that are connected in series/parallel during discharging/charging mode. The operation of switches with two different duty ratios is the main advantage of the converter to achieve high voltage gain without using extreme duty ratio. The steady-state analysis of the proposed converter using two different duty ratios is discussed in detail. In addition, a 100 W, 20/200 V prototype circuit of the high gain dc–dc converter is developed, and the performance is validated using experimental results. Index Terms—Efficiency analysis, nonisolated high gain dc–dc converter, voltage stress on switches and diodes.

I. INTRODUCTION C MICROGRID technology is evolving due to the penetration of distributed generating sources. DC power generators produce low output voltage and hence require high efficient high gain dc–dc converters to meet the dc load requirements [1], [2]. Nowadays, high gain dc–dc converters are used in many applications other than the renewable energy conversion, such as battery backup systems for uninterrupted power supplies, high intensity discharge lamp ballasts for automobile headlamps, electric tractions, and some medical equipment [3]– [5]. In the recent past, conventional dc–dc boost converter is used to step up the voltage. However, the voltage stress on the switch is equal to the output voltage. Hence, high rated switch is selected to meet the voltage stress on the switch that results in high conduction loss. In addition, selection of large duty ratios to achieve high voltage gain not only increases the conduction

D

Manuscript received January 30, 2017; revised April 25, 2017 and June 6, 2017; accepted July 2, 2017. Date of publication July 31, 2017; date of current version December 8, 2017. This work was supported in part by the Power Electronics Laboratory, School of Electrical Engineering, VIT University, Chennai, India. (Corresponding author: S. Hemamalini.) The authors are with the School of Electrical Engineering, VIT University, Chennai 600 127, India (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2017.2733463

, Member, IEEE

losses and high voltage spikes but induce serious diode reverse recovery problem as well [6]–[9]. Various isolated dc–dc converter topologies are proposed in the literature to achieve desired high voltage gain [10]–[12]. Nevertheless, the problem associated with this type of converter is transformer core saturation. Therefore, nonisolated dc–dc converters can be used to achieve high voltage gain with reduced size and cost, where the galvanic isolation is not needed [13], [14]. Some of the nonisolated high gain converters are cascade boost [15], the quadratic boost [16], voltage lift [17]– [19], the capacitor–diode voltage multiplier [20], [21], and the conventional boost converter integrated with switched-capacitor technique [22]. The inclusion of switched-capacitor or a switched-inductor stage increases the cost and complexity of the circuit. Several coupled inductor based boost converter topologies provide high voltage gain and low voltage stress on the switch based on the selection of duty ratio [23]–[26]. Sometimes, turns ratio of the coupled inductor is increased to reach the desired voltage conversion ratio, resulting in high input current ripple. Therefore, input filter is needed to reduce the current ripple [27]. A cascaded high gain converter with a single input inductor is proposed [28] to meet the high voltage requirement and low input current ripple. Hybrid high gain high power topologies are also developed [29], [30]. In this paper, a novel high gain dc–dc converter is developed to overcome the issues mentioned above. The proposed converter has high voltage gain by selecting appropriate duty cycle and by designing proper inductor and capacitor values. It has the following advantages. 1) The three power switches in the proposed converter operate with two different duty ratios to attain high voltage gain. 2) The stored inductor energy is supplied to the load without additional clamping circuit. 3) The voltage gain achieved by the proposed converter is greater than the conventional boost converter and the converter presented in [8] and [9]. 4) Voltage stress on the diodes and switches is reduced based on the percentage output voltage. 5) The proposed converter is capable of achieving high voltage gain without voltage multiplier cell (VMC) and/or hybrid switched-capacitor techniques. The circuit description of the proposed converter is presented in Section II. Section III explains the steady-state analysis of the high gain converter. Efficiency analysis of the proposed

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Fig. 1.

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 2, FEBRUARY 2018

Proposed high gain dc–dc converter.

converter is presented in Section IV. Section V discusses the performance of the proposed converter in terms of voltage gain, voltage stress on the switches and diodes. The experimental results for a 100 W prototype of the proposed converter are analyzed in Section VI. Finally, Section VII concludes results of the proposed converter. II. CIRCUIT DESCRIPTION The proposed high gain dc–dc converter shown in Fig. 1 consists of three active switches S1 , S2 and S3 , two inductors L1 and L2 , two diodes D1 and D2, and one output capacitor Co . The switches S1 , S2 and S3 operate at a switching frequency of fs . The duty ratio of the switches S1 and S2 is D1 and of the third switch S3 is D2 . In order to explain the steady-state operation of the proposed converter, some assumptions are made as follows: 1) All the components in the circuit are ideal. The effects of ON-state resistance of the switches, forward voltage drop of the diodes, equivalent series resistance (ESR) of the inductors and capacitors are neglected. 2) The output capacitance Co is sufficiently large to maintain constant output voltage. Let the number of turns in the two inductors is equal so that L1 = L2 = L.

(1)

The voltage across the inductors vL 1 and vL 2 are given as follows: diL 1 diL 1 =L dt dt diL 2 diL 2 =L = L2 dt dt

vL 1 = L1

(2)

vL 2

(3)

Fig. 2.

CCM operation of the proposed converter.

A. CCM Operation Mode I: During the time interval [t0 , t1 ], S1 and S2 are turned is turned OFF. The current path in the circuit is shown in Fig. 3(a). The source energy is transferred to the inductors L1 , L2 and the energy stored in the capacitor Co is discharged to the load. Here, the diode D1 and D2 are in reverse bias condition, but the internal diode of the switch S3 is in forward bias condition. Therefore, the conduction voltage of this diode appears across switch S3 when it is turned OFF. In this mode, inductors are parallel to the source and thereby the voltages across the inductors are given as follows:

ON and S3

where iL 1 and iL 2 are the current through the inductors L1 and L2 , respectively.

v L 1 = vL 2 = V i .

(4)

Substituting (2) and (3) into (4), (5) is obtained as follows: III. STEADY-STATE ANALYSIS OF THE PROPOSED CONVERTER In this section, the operating modes of the proposed converter in continuous conduction mode (CCM) are discussed. There are three modes of operation for a single switching period with two different duty ratios. Fig. 2 shows the waveforms of the proposed converter in CCM.

L

diL 2 diL diL 1 =L =L = Vi , dt dt dt diL 2 diL Vi diL 1 = = = . dt dt dt L

t0 ≤ t ≤ t 1

(5) (6)

Mode II: During the time interval [t1 , t2 ], S1 and S2 are turned OFF and S3 is turned ON. The current path during this

LAKSHMI AND HEMAMALINI: NONISOLATED HIGH GAIN DC–DC CONVERTER FOR DC MICROGRIDS

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S3 is the addition of input and output voltages. In this mode, the inductors are in series to the source. The current through and the voltage across the inductors are given as follows: iL 1 = iL 2 = iL

(10)

vL 1 + v L 2 = V i − V o

(11)

where Vo is the output voltage of the high gain converter. Substituting (2) and (3) into (11), the following equation is obtained: diL Vi − Vo = , dt 2L

t2 ≤ t ≤ t 3 .

(12)

Using state space averaging method, the following equation is obtained from (6), (9), and (12): I II  D1 Ts   D2 Ts  diL diL dt + dt dt dt 0 0 III  (1−D 1 −D 2 )T s  diL dt = 0 (13) + dt 0 where the superscripts I, II, and III denote the modes of operation. Simplifying (13), the voltage gain is obtained as (1 + D1 ) Vo . = Vi (1 − D1 − D2 )

(14)

B. Voltage Stress on the Switches and Diodes

Fig. 3.

CCM operation. (a) Mode I, (b) Mode II, and (c) Mode III.

period is depicted in Fig. 3(b). The source energy is transferred to the inductors and the current flows through L1 , D1 and L2 . In this mode, the voltage across the switches S1 and S2 is half of the input voltage. The stored energy in the capacitor Co is delivered to the load since diode D2 is in the reverse bias condition. In this mode, the inductors are in series to the source. The current through and the voltage across the inductors are given in the following equations: iL 1 = iL 2 = iL

(7)

vL 1 + v L 2 = V i

(8)

where iL is the current through the inductors L1 and L2 , when they are connected in series and Vi is the input voltage. Substituting (2) and (3) into (8), the following relation is obtained: diL Vi = , dt 2L

t1 ≤ t ≤ t 2 .

(9)

Mode III: During the interval [t2 , t3 ], S1 , S2 , and S3 are turned OFF. The current direction in the circuit is shown in Fig. 3(c). In this mode, both source and the inductors supply the load. Diode D1 is in reverse bias condition. In addition, the capacitor Co is in charging mode as the diode D2 is forward biased. The voltage across the switches S1 and S2 is the average of the input and output voltages, whereas the voltage across switch

From Fig. 2, the voltage stress VD S 1 , VD S 2 , and VD S 3 on the switches S1 , S2 , and S3 , respectively, is given as ⎧ Vo + Vi ⎨ VD S 1 = VD S 2 = (15) 2 ⎩V =V . DS3

o

The voltage stress VD 1 and VD 2 on the diodes D1 and D2, respectively, is expressed as  VD 1 = Vi (16) VD 2 = Vi + Vo . C. Inductor Design The selection of inductor [20] depends upon the input voltage (Vi ), ripple current (ΔiL ), switching frequency (fs ), and duty ratio (D1 ). The critical value of the inductance to operate the proposed converter in CCM is obtained using the following equation: L1, critical = L2, critical =

Vi D1 . ΔiL fs

(17)

D. Capacitor Selection The value of output capacitor Co [20] depends upon the power rating of the converter (Po ), output voltage (Vo ), voltage ripple (ΔVc ), and switching frequency (fs ) which is obtained using the following equation: Co,critical =

Po . Vo ΔVc fs

(18)

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 2, FEBRUARY 2018

Simplifying (25), the current through the inductor IL 1 is obtained as Vo . (26) IL 1 = Ro (1 − D1 − D2 ) Applying volt-second balance principle on any of the inductor L1 or L2 , the following equation is obtained:  D1 Ts  D2 Ts  (1−D 1 −D 2 )T s VLI1 dt + VLII1 dt + VLIII 1 dt = 0. 0

0

0

(27)

Simplifying (27), the output voltage is obtained as Vo = Fig. 4.

Equivalent circuit of the proposed converter.

IV. EFFICIENCY ANALYSIS In this section, the converter efficiency for all the three modes of operation is discussed. The equivalent circuit of the converter is shown in Fig. 4. rL 1 and rL 2 are the ESR of the inductors L1 and L2 , respectively. Similarly, rD 1 , rD 2 are the internal resistances and VD 1 , VD 2 are the voltage drops across the diodes D1 and D2, respectively. rS 1 , rS 2 , and rS 3 represent the ONstate resistance of the switches S1 , S2 , and S3 , respectively. Ro is the load resistance. Mode I: When S1 and S2 are turned ON and S3 is turned OFF, the average values of the capacitor current Ico and the inductor voltage VL 1 during the time interval D1 Ts is given as I Ico

VLI1

Vo =− Ro

(19)

= Vi − iL 1 (rS 1 + rL 1 ) .

(20)

Mode II: When S1 and S2 are turned OFF and S3 is turned ON, the average values of the capacitor current Ico and the inductor voltage VL 1 during the time interval D2 Ts is given as II Ico = −

VLII1 =

Vo Ro

(21)

Vi − iL 1 (rS 3 + rL 1 + rL 2 + rD 1 ) − VD 1 . 2

(22)

Mode III: When S1 , S2 , and S3 are turned OFF, the average values of the capacitor current Ico and the inductor voltage VL 1 during the time interval (1 − D1 − D2 )Ts is given as III Ico = IL 1 −

VLIII 1 =

Vo Ro

(23)

Vi − Vo − iL 1 (rL 1 + rL 2 + rD 2 ) − VD 2 . 2

(24)

Applying ampere-second balance principle for the output capacitance Co , the following equation is obtained:  0

D1 Ts

 I Ico dt

+

0

D2 Ts

 II Ico dt

+

0

(1−D 1 −D 2 )T s

Vi (1+D1 )−(VD 1 D2 )−(VD 2 (1−D1 −D2 ))

2(D 1 A 1 +D 2 A 2 +A 3 ) + (1 − D1 − D2 ) R o (1−D 1 −D 2 ) ⎧ ⎨A1 = rS 1 + (rD 2 /2) where A2 = 1/2 (rD 1 − rD 2 + rS 3 ) ⎩ A3 = rL 1 + (rD 2 /2) .

(28)

(29)

The input and output powers for the proposed converter is obtained as Pi = 2 Vi IL 1 D1 + Vi IL 1 D2 + Vi IL 1 (1 − D1 − D2 ) . (30) Substituting (26) into (30), the input power is given as Pi =

Vi Vo (1 + D1 ) Ro (1 − D1 − D2 )

(31)

Po =

Vo2 . Ro

(32)

From (28), (31), and (32), the efficiency of the proposed high gain dc–dc converter (considering only conduction losses) is calculated as Po [Vi (1 + D1 ) − VD 1 D2 − VD 2 (1 − D1 − D2 )] = . 1 A 1 +D 2 A 2 +A 3 ) Pi Vi (1 + D1 ) 1 + 2 (D 2 R o (1−D 1 −D 2 ) (33) Considering the switching losses (Psw ), the output power of the proposed converter is given as η=

Po =

Vo2 − PSW Ro

PSW = VDS ID (tr + tf ) fSW

(34) (35)

where VDS is the drain source voltage of the MOSFETs, ID is the drain current of the MOSFETs, fsw is the switching frequency, tr and tf are the rise and fall time of the MOSFETs. Using (28), (29), (31), and (34), the efficiency of the proposed converter is calculated as 2

Vo − P SW Ro Po . = η= (36) V i V o (1+D 1 ) Pi R o (1−D 1 −D 2 )

V. PERFORMANCE COMPARISON III Ico dt = 0.

(25)

The proposed converter is compared with converters in [8] and [9] and with the conventional boost converter in terms of

LAKSHMI AND HEMAMALINI: NONISOLATED HIGH GAIN DC–DC CONVERTER FOR DC MICROGRIDS

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TABLE I COMPARISON OF STEADY-STATE CHARACTERISTICS AND THE COMPONENT USAGE Parameters

Proposed Converter

Converters in [8]

Converters in [9]

Conventional Boost Converter

(1 + D 1 ) (1 −D 1 −D 2 )

(1 + D ) (1 −D )

(1 + D ) (1 −D )

1 (1 −D )

Voltage gain Voltage gain representation similar to conventional boost converter Voltage stress on switches

1 2D 1 + D 2 1− 1 + D1

No. of MOSFETs No. of diodes No. of inductors No. of capacitors

Fig. 5.

1 1 −D new[ p ]

V DS1 = V DS2 = V DS3 = V o

Voltage stress on diodes

=

Vo +Vi 2

1 1 − 12+DD

=

1 1 −D new[ 8 ]

V DS1 = V DS2 =

VD 1 = Vi VD 2 = Vi + Vo 3 2 2 1

Comparison of voltage gain.

usage of components, voltage gain, voltage stress on the switches and diodes as given in Table I. It is observed from Table I that the conventional boost converter and the converter presented in [8] and [9] uses single duty ratio D. Whereas, the proposed converter uses two different duty ratios D1 and D2 to achieve high voltage gain. The voltage gain equation of the converter in [8] and [9] and for the proposed converter can be rewritten similar to the conventional boost converter and is shown in Table I. The voltage gain representation of the proposed converter differs from the converter in [8] and [9] by the addition of a duty ratio D2 in Dnew[p] , which is the cause for increase in voltage gain, i.e., the addition of switch S3 which is operating at the duty ratio of D2 increases the voltage gain of the proposed converter. Moreover, the calculated value of Dnew[p] is 0.9 while considering D1 = 0.5 and D2 = 0.35. For this calculated value of Dnew[p] , reliable operation (extreme duty ratio) is not possible for any converter which uses single duty ratio D. The voltage gain against duty ratio is plotted for the different converters and is shown in Fig. 5. In this plot, for the proposed converter, the voltage gain is shown for different duty

Vo +Vi 2

1 1 − 12+DD

=

1 1 −D new[ 9 ]

V DS1 = V DS2 = V DS3 = V i + V o

Vo +Vi 2

Vo

VD = Vi + Vo



Vo

2 1 2 1

3 0 2 1

1 1 1 1

Fig. 6. Voltage gain corresponding to variations in duty ratio D 1 and D 2 for the proposed converter.

ratios D1 and for a fixed duty ratio D2 of 0.35. It is observed that the proposed converter provides a high voltage gain of 32 for the duty ratio of D1 = 0.6 and D2 = 0.35. However, for the same duty ratio of 0.6, the conventional boost converter and the converters in [8] and [9] provides a voltage gain of 2.5 and 4, respectively. For the proposed converter, the voltage gain corresponding to variation in duty ratio D1 and D2 is illustrated in Fig. 6. It is seen that the proposed converter is capable of providing high voltage gain by varying the duty ratios to the switches appropriately. In the proposed converter, the voltage stress on the switches S1 and S2 is computed as 55% of the output voltage and for the switch S3 is 100% of the output voltage. Whereas, the voltage stress on switches S1 and S2 for the converter presented in [9] is 66% of the output voltage and on switch S3 is 133% of the output voltage. Therefore, the percentage of the voltage stress on the proposed converter with respect to the output voltage is less, in comparison to the converter in [9]. Likewise, the percentage of the voltage stress on the diode is also less in comparison to the

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TABLE II PROTOTYPE SPECIFICATION AND COMPONENT RATINGS Parameters Rated Power (P o ) Input Voltage (V i ) Output Voltage (V o ) Duty Ratio (D 1 ) Duty Ratio (D 2 ) Switching Frequency (fS 1 , fS 2 and fS 3 ) Inductor (L 1 , L 2 ) Capacitor (C o ) Power MOSFET (S 1 , S 2 and S3 ) Diodes (D1, D2)

Fig. 7.

Theoretical efficiency for various duty ratios D 1 and D 2 .

Fig. 8.

Experimental setup for the proposed converter.

converter in [8]. The number of inductors and capacitors used in the proposed converter and the converter in [8] and [9] are the same. The number of switches used in the proposed converter is same as that for converter in [9]. The theoretical efficiency plot of the proposed converter for different duty ratio D1 and D2 is illustrated in Fig. 7. It can be seen that the efficiency of the converter is well above 87.5% for various combinations of duty ratios D1 and D2 . In order to achieve high voltage gain and high efficiency, the following constraints are to be taken care of 1) D1 and D2 should not be equal to 0.5, and 2) sum of the duty ratios D1 and D2 should not exceed 1. VI. EXPERIMENTAL RESULTS To validate the theoretical analysis of the proposed converter, a 100 W prototype circuit shown in Fig. 8 is developed and tested in the laboratory with the specifications given in Table II. The TMS320F2812 processor is used to generate the gate pulses with appropriate duty ratio, switching frequency, and the phase delay. Fig. 9(a) shows the gate pulses VG S 1 , VG S 2 , and VG S 3 . It can be seen that the gate pulses VG S 1 and VG S 2 operate at 50 kHz with the duty ratio of 0.5. The gate pulse VG S 3 is phase

Values (Unit) 100 W 20 V 200 V 0.5 0.35 50 kHz 360 μH 100 μF FDP20N40 SBR20A300CTB

shifted by 180° and operates at the same switching frequency 50 kHz with the duty ratio of 0.35. Fig. 9(b) shows the gate pulses, the input, and output voltage waveforms Vi and Vo for the proposed converter. It can be seen that a voltage gain of 9.6 with a ripple voltage of 2% is observed when the input is 20 V. This experimental voltage gain is also validated with the theoretical calculation. Fig. 9(c) shows the gate pulses, the input, and output current waveforms ii and io . It is observed that the average value of the input current is 4.92 A and the output current is 477 mA. Also, the ripple in the current through each of the inductors is observed as 12% of the input current and the input current ripple is about 24%. It is seen in Fig. 9(d), the inductor currents iL 1 and iL 2 are continuous. The input current is double the value of the inductor current iL 1 (or iL 2 ) when switches S1 and S2 are ON and the input current is equal to inductor current iL 1 (or iL 2 ) when switches S1 and S2 are OFF. Fig. 9(e) shows the gate pulses and the switch voltage stresses. It is observed that the voltage stress on switches S1 and S2 is the average of the input and output voltages. Whereas, the voltage stress on switch S3 is equal to the output voltage. The voltage stress on the switch S3 in comparison to the converter in [9] is less with respect to the percentage of output voltage. Fig. 9(f) shows the gate pulses and diode voltage stress VD 1 and VD 2 . It is evident that the voltage stress on diode D1 is equal to the input voltage and for diode D2 , it is the sum of the input and output voltages. From the experimental results, it is evident that the proposed converter is able to provide high voltage gain with reduced voltage stress on the switches and diodes. Fig. 10(a) shows the theoretical and experimental values of the output voltage with respect to the output power. It is observed that the variation in the output voltage is minimum for different loading condition. Also, the average deviation between the theoretical and experimental output voltage is 0.75%. Fig. 10(b) shows the theoretical and experimental values of the efficiency with respect to the output power. The experimental efficiency of the proposed converter for various load condition is above 92% and the full-load efficiency is 93.6%. The theoretical efficiency for full-load condition is 94% which is almost equal to the experimental efficiency. Also, the average deviation between the theoretical and experimental efficiency is 0.5%.

LAKSHMI AND HEMAMALINI: NONISOLATED HIGH GAIN DC–DC CONVERTER FOR DC MICROGRIDS

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Fig. 9. Experimental results for the proposed high gain converter. (a) Gate pulse voltages (V GS1 , V GS2 and V GS3 ). (b) Output and input voltage (V o and V i ). (c) Output and input current (io and ii ). (d) Inductor currents (iL 1 and iL 2 ). (e) Switch voltages (V DS1 , V DS2 and V DS3 ). (f) Diode voltages (V D 1 and V D 2 ).

Fig. 10.

Comparison of theoretical and experimental values. (a) Output power versus output voltage. (b) Output power versus efficiency.

VII. CONCLUSION In this paper, a nonisolated high gain dc–dc converter was presented to achieve high voltage gain. For any converter that uses single duty ratio D, the extreme duty ratio operation is not reliable. In the proposed converter, the inclusion of switch S3 and the operation of three switches with two different duty ratios are the main advantages. Theoretical and experimental analysis was done for the voltage gain, efficiency, voltage stress on the switches and diodes for the proposed converter. A 100 W prototype model of the proposed converter was developed and the experimental results validate that high voltage gain was obtained without using VMC and/or hybrid switched-capacitor technique. The percentage of the voltage stress on the diodes and switches with respect to the output voltage was less in the proposed converter compared with the converters in [8] and [9].

At full-load condition, the efficiency of the proposed converter was 93.6%, which is nearly equal to the theoretical efficiency. In open-loop condition, the output voltage variation was about 2.5% for the variations in loads. To regulate the output voltage variation, closed-loop control strategy is to be implemented, which makes the converter suitable for microgrid applications. REFERENCES [1] N. Eghtedarpour and E. Farjah, “Distributed charge/discharge control of energy storages in a renewable-energy-based DC micro-grid,” IET Renewable Power Gener., vol. 8, no. 1, pp. 45–57, Jan. 2014. [2] J. M. Carrasco et al., “Power-electronic systems for the grid integration of renewable energy sources: A survey,” IEEE Trans. Ind. Electron., vol. 53, no. 4, pp. 1002–1016, Jun. 2006. [3] B. Bryant and M. K. Kazimierczuk, “Voltage-loop power-stage transfer functions with MOSFET delay for boost PWM converter operating in CCM,” IEEE Trans. Ind. Electron., vol. 54, no. 1, pp. 347–353, Feb. 2007.

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M. Lakshmi received the B.E. degree in electrical and electronics engineering from Bharathidasan University, Tiruchirappalli, India, in 2003, and the M.E degree in power systems from Anna University, Chennai, India, in 2011. She is currently working toward the Ph.D. degree in analysis of converters in a grid connected photovoltaic system in the School of Electrical Engineering, VIT University, Chennai. Her research interests include power electronics applications in power systems, high gain dc–dc converters, and renewable energy applications.

S. Hemamalini (M’17) received the B.E. degree in electrical and electronics engineering from the Thiagarajar College of Engineering, Madurai, India, in 1993, and both the M.Tech. and Ph.D. degrees in power systems from the National Institute of Technology, Tiruchirappalli, India, in 2005 and 2011, respectively. She has about 20 years of teaching and research experience. She is currently a Professor in the School of Electrical Engineering, VIT University, Chennai, India. Her current research interests include power system optimization, renewable energy, microgrids, power electronics applications in power systems, reliability and protection in microgrids, and electric vehicles. Dr. Hemamalini is a member of the IEEE Power and Energy Society and the IEEE Power Electronics Society, as well as a Lifetime Member of the Indian Society for Technical Education.

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