IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 10, OCTOBER 2012
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Normally Off GaN Power MOSFET Grown on Sapphire Substrate With Highly Resistive Undoped Buffer Layer Jae-Hoon Lee, Senior Member, IEEE, Jae-Hyun Jeong, and Jung-Hee Lee, Senior Member, IEEE
Abstract—A high-performance normally off GaN-based MOSFET was fabricated. The buffer layer of the MOSFET was grown by varying the growth temperature to control the size of nucleation sites which results in an extremely high buffer resistance (> 1012 Ω/sq). The fabricated small-area MOSFET exhibited excellent normally off device characteristics, such as a threshold voltage of 2 V, maximum drain current of 253 mA/mm, on–off current ratio of 5.5 × 107 , destructive breakdown voltage of 830 V, and leakage current of 0.7 μA/mm at a VDS of 600 V. The corresponding values of the large-area MOSFET with a multifinger pattern were 0.6 V, 6 A, 1.3 × 107 , 670 V, and 50 μA (0.28 μA/mm). Index Terms—AlGaN/GaN, breakdown voltage, metal–oxide– semiconductor field-effect transistor (MOSFET), multifinger pattern, normally off, nucleation sizes.
I. I NTRODUCTION OST of the GaN-based power transistors are fabricated on the AlGaN/GaN heterostructures grown on Si due to its large wafer size and cost effectiveness. Nevertheless, the growth of GaN on sapphire still has potential advantages in view of the facts that the growth of GaN on sapphire is much easier and the crystalline quality of the grown GaN on sapphire is much better, compared to that on Si. The size of the sapphire substrate becomes steadily increased now up to 6 in in diameter, and the cost also becomes cheaper. Furthermore, the bad thermal conductivity of the sapphire substrate could be solved by forming backside via-hole contact after thinning the sapphire substrate or by using laser lift-off technique to remove the substrate developed for the vertical-type GaN-based LED [1], [2]. It is well known that the usual undoped GaN layer grown on a normal growth condition generally exhibits n-type conductivity due to residual donor impurities such as nitrogen vacancies and oxygen atoms which cannot be used as a buffer layer of the AlGaN/GaN-based heterostructure field-effect transistor (HFET). Therefore, the semi-insulating GaN layer is required to avoid the parallel conduction and to minimize the OFF-state leakage current. The semi-insulating GaN layer was successfully obtained by doping compensating
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Manuscript received January 17, 2012; revised June 19, 2012; accepted June 28, 2012. Date of publication August 8, 2012; date of current version September 21, 2012. This work was supported by Brain Korea 21. The review of this letter was arranged by Editor S.-H. Ryu. J.-H. Lee and J.-H. Jeong are with the GaN Power Research Group, R&D Institute, Samsung LED Company, Ltd., Suwon 443-743, Korea (e-mail:
[email protected]). J.-H. Lee is with the School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu 702-701, Korea (e-mail:
[email protected]). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2012.2207366
acceptors such as C, Fe, or Mg, even though some problems such as the redistribution of dopant atoms toward the channel region may exist [3], [4]. These impurities can also exhibit a strong memory effect in epitaxial growth, thereby precluding abrupt transitions in doping. To avoid these problems, the introduction of threading dislocations or other defects during the growth was suggested to obtain the semi-insulating GaN layer. However, the device fabricated on this semi-insulating buffer layer suffers from the trapping/detrapping of electrons due to the degraded crystalline quality which occasionally results in a severe current collapse in AlGaN/GaN HFET [5]. To minimize the trapping effect, therefore, it is necessary to grow a semiinsulating GaN layer while maintaining the crystalline quality as high as possible. To meet the requirement, in this work, we suggest a simple method of growing a highly resistive GaN buffer layer grown on a sapphire substrate by controlling the size of the nucleation sites. Higher device performances for the metal-oxide-semiconductor field-effect transistors (MOSFETs), fabricated on the AlGaN/GaN heterostructure with this proposed buffer layer, are also demonstrated. II. E XPERIMENTS The AlGaN/GaN heterostructure investigated in this work was grown by metal–organic chemical vapor deposition on 4-in (0001) c-plane sapphire substrates which consists of 30-nmthick low-temperature-grown initial GaN layer, 3-μm-thick highly resistive undoped GaN buffer layer, and 25-nm-thick AlGaN barrier. Different from the normal growth, the undoped GaN buffer layer of the heterostructure was first grown at a relatively low temperature of 950 ◦ C for 2 min, and the temperature was elevated to the normal growth temperature of 1100 ◦ C to complete the remaining growth. The time for the temperature ramping was 2 min, and no growth interruption was applied. The Al content in the AlGaN barrier is 30%, determined by high-resolution X-ray diffraction. The mobility and the density of the 2-D electron gas (2DEG) formed at the AlGaN/GaN heterointerface were 1600 cm2 /V · s and 8 × 1012 /cm2 , respectively. For the device fabrication, the active region of the device was defined by inductively coupled plasma reactive ion etching using a BCl3 /Cl2 gas mixture. The 25-nmthick AlGaN layer in the gate region was fully recessed by using the same gas mixture. A 25-nm-thick Al2 O3 gate insulator layer was then deposited on the recessed GaN surface by plasma-assisted atomic layer deposition (ALD) at 450 ◦ C, subsequently annealed at 600 ◦ C for 30 min in N2 ambient to recover plasma damage and improve the dielectric quality. After opening contact holes, a Ti/Al/Ni/Au metal layer for ohmic contact was deposited and followed by rapid thermal annealing at 850 ◦ C for 30 s in N2 ambient. The specific contact resistance
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IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 10, OCTOBER 2012
TABLE I S TRUCTURAL AND E LECTRICAL P ROPERTIES OF U NDOPED GaN W ITH S MALL AND L ARGE G RAIN S IZES IN THE I NITIAL G ROWTH S TATE
Fig. 1. Schematic cross-sectional and TEM images of fabricated MOSFET.
Fig. 3. HFET. Fig. 2. I–V measurement of GaN film with the proposed temperature grade growth method. The insets show [(a) and (c)] SEM and [(b) and (d)] TEM images of films grown with small grain size and large grain size in the initial growth stage.
of 2 × 10−5 Ω · cm−2 was obtained for the annealed sample using transmission line measurements (TLMs). After depositing Ni/Au for the gate metal, a Si3 N4 interdielectric layer with a thickness of 800 nm was deposited to cover the entire surface of the device. Ti/Al pad metals were finally deposited to connect the gate and the source/drain region. Schematic cross-sectional and transmission electron microscope (TEM) images of the fabricated MOSFET are shown in Fig. 1. III. R ESULTS AND D ISCUSSION Fig. 2 shows a typical electrical property of the undoped GaN buffer layer grown by the proposed sequence. An extremely high sheet resistance (Rs ) of ∼ 1012 Ω/sq was measured by using a circular-type TLM pattern between two ohmic contact pads with an inner diameter of 400 μm and interelectrode distance varied from 5 to 100 μm. The curve in the figure represents the current–voltage (I–V ) characteristic between two contacts with an interelectrode distance of 100 μm. The key feature for the growth of the buffer layer in the initial stage of the growth is that many nucleation sites with smaller grain sizes tend to be generated when the growth proceeds at a relatively low temperature of 950 ◦ C, as shown in inset (a) of Fig. 2. The growth with smaller grain sizes leads to large mismatches in growth orientation and direction which results in the generation of many crystal defects such as dislocations and stacking faults in the subsequently grown GaN layer at a relatively high temperature of 1100 ◦ C, as shown in inset (b) of Fig. 2. These defects are generally known to act as deep traps in the GaN layer, which makes the layer very resistive [6]. In contrast, the normal GaN growth without varying temperature results in the growth with larger grain size and less nucleation density, as observed in inset (c) of Fig. 2, and hence, the density of coalescence boundary decreases as shown in inset (d) of Fig. 2, which eventually produces improved structural and electrical properties of the layer [7]. The properties for the undoped GaN layers grown by the normal and proposed sequence are compared in Table I. The
Pulsed IDS –VDS characteristics for normally on small-sized GaN
full-width at half-maximum of asymmetric (102) rocking curve for the sample grown by the proposed sequence is 475 arcseconds, which is much narrower than that (5100 arcseconds) of previously reported semi-insulating GaN buffer layer [8], even though it is wider than that (240 arcseconds) for the undoped GaN layer grown under a normal growth condition which usually exhibits n-type conduction. The photoluminescence (PL) spectral intensity of the sample is approximately an order lower in magnitude than that for the sample grown by normal sequence, which indicates that the sample grown by the proposed sequence contains many deep traps as discussed earlier, mostly known as acceptor-like defects associated with Ga vacancy and edge-type dislocation [9]. Lee et al. reported that edge-type dislocations in GaN can act as acceptor-like deep trap center for electrons [10]. The present asymmetry (102) rocking curve results therefore explain that the edgetype dislocations in GaN play a role in compensating n-type background carriers which makes the GaN layer highly resistive as the semi-insulating GaN layer obtained in this work. These results explain that the proposed sequence is very effective in growing a highly resistive GaN buffer layer even without any additional compensation doping. To evaluate the trapping effect in the buffer layer, the pulsed IDS –VDS measurement, as shown in Fig. 3, was performed for the normally on small-sized GaN HFET device which has been fabricated on the same GaN buffer layer as the GaN power MOSFET. The gate length and width of the device are 2 and 140 μm, respectively. To measure the gate and drain lags, the bias voltage changed from VDS = 0.0 V/VGS = 0.0 V to VDS = 0.0 V/VGS = −7.0 V and from VDS = 20 V/VGS = −2.0 V to VDS = 20 V/VGS = −7.0 V, respectively [4]. The duration and separation of the pulse were 0.5 μs and 0.5 ms, respectively. The pulse measurement exhibits that the current collapse related to the gate and drain lags is insignificant for the device. Negligible drain lag observed for the device probably confirms that the trap levels in the proposed semiinsulating GaN buffer layer are very deep, and hence, the trapping/detrapping of electrons through the traps is not active. Fig. 4 shows the I−V characteristics of the fully recessed AlGaN/GaN MOSFET with the GaN buffer layer grown by the proposed sequence. The gate length, the gate width, and the gate-to-drain distance of the device were 2, 140, and 20 μm,
LEE et al.: NORMALLY OFF GaN POWER MOSFET GROWN ON SAPPHIRE SUBSTRATE
Fig. 4. I–V characteristics of the fabricated unit patterned normally off MOSFETs with 25-nm-recessed gate. (a) Drain current, (b) transfer characteristics, (c) gate leakage current, and (d) breakdown voltage.
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were observed at a VDS of 8 V as shown in Fig. 5(b), which are slightly decreased compared to the values obtained for the small-sized devices. The reason of the lower threshold voltage for the large-sized device is maybe due to the nonuniform 2DEG density, which resulted from the nonuniform recess etching of the AlGaN barrier over a large surface area. The onresistance (RDS(on) ) of the large-sized device with a dimension of 3000 × 3000 μm2 is 0.3 Ω (27 mΩ · cm2 ) at IDS = 1 A and VGS = 5 V as shown in Fig. 5(c). In spite of large chip size, however, the reverse breakdown voltage and the leakage current (measured at a VDS of 600 V) were not significantly degraded, showing 670 V and 50 μA (0.28 μA/mm), respectively, as shown in Fig. 5(d). The higher breakdown voltage and lower leakage current are mainly attributed to the extremely high GaN buffer resistance and the effective surface passivation with the high-quality ALD-Al2 O3 layer. IV. C ONCLUSION
Fig. 5. I–V characteristics of the large-sized normally off MOSFET with the multifinger pattern. (a) Drain current, (b) transfer characteristics, (c) onresistance, and (d) breakdown voltage.
respectively, and the total size of the device was 500 × 500 μm2 . The device with an effective area of 150 × 200 μm2 (except the contact pad area) exhibits a maximum drain current (Id max ) of 253 mA/mm at a drain voltage of 10 V, and the specific ON-state resistance is 10 mΩ · cm2 , as shown in Fig. 4(a). The transfer curve (IDS –VGS ) of the device at a fixed VDS of 8 V is shown in Fig. 4(b), showing a threshold voltage of 2 V, extrapolated from the I–V characteristics in the linear region (at a VDS of 2 V), and a very high on/off drain-current ratio (ION /IOFF ) of 5.5 × 107 . These excellent device performances are because of the very high buffer resistance achieved by the proposed growth sequence which greatly decreases the OFF-state current and, in addition, the high-quality ALD-Al2 O3 gate insulator which ensures a low gate leakage current of 2 × 10−6 A/mm (at VGS = 30 V). Fig. 4(d) shows the excellent OFF-state characteristics with a very low leakage current of 0.7 μA/mm at 600 V and high destructive breakdown voltage of 870 V. Fig. 5 shows the device performance for the large-sized MOSFET with the multifinger pattern for the high-power application. The large device has the same device configurations as the small device, except that the gate width and the total size of the device were increased to 180 mm and 3000 × 3000 μm2 , respectively. Id max is as high as 6 A at a VDS of 4 V and at a VGS = 5 V as shown in Fig. 5(a), which corresponds to the normalized value of 30 mA/mm, five times lower compared to that of the small-sized device (150 mA/mm at VGS = 5 V). This is mainly due to the decreased channel mobility at an elevated device temperature under high-current operation and also the significant current crowding effect caused by high series resistance in such a large-area device. The threshold voltage and ION /IOFF ratio of 0.6 V and 1.3 × 107 , respectively,
The growth of a highly resistive GaN buffer layer has been proposed, which varies the growth temperature during the layer growth to control the sizes of the nucleation sites. The layers grown by the proposed sequence have been shown to be semi-insulating with an extremely high sheet resistance (> 1012 Ω/sq), even though any intentional impurities have not been doped. The successful normally off operation has been achieved from the GaN MOSFET fabricated on the AlGaN/ GaN heterostructure with this buffer layer. The large-sized MOSFET with a multifinger pattern has exhibited a threshold voltage of 0.6 V, maximum drain current of 6 A, ION /IOFF of ∼107 , breakdown voltage of 670 V, and leakage current of 50 μA at a VDS of 600 V. R EFERENCES [1] J. H. Lee, J. T. Oh, S. B. Choi, Y. C. Kim, H. I. Cho, and J. H. Lee, “Enhancement of InGaN-based vertical LED with concavely patterned surface using patterned sapphire substrate,” IEEE Photon. Technol. Lett., vol. 20, no. 5, pp. 345–347, Mar. 2008. [2] J. H. Lee and K. S. Kim, “Gallium Nitride Based Semiconductor Devices and Methods of Manufacturing the Same,” US Patent 2 012 006 172 7A1, Mar. 15, 2012. [3] Y. Ohba and A. Hatano, “A study on strong memory effects for Mg doping in GaN metalorganic chemical vapor deposition,” J. Cryst. Growth, vol. 145, no. 1–4, pp. 214–218, Dec. 1994. [4] S. Heikman, S. Keller, S. P. DenBaars, and U. K. Mishra, “Growth of Fe doped semi-insulating GaN by metalorganic chemical vapor deposition,” Appl. Phys. Lett., vol. 81, no. 3, pp. 439–441, Jul. 2002. [5] S. C. Binari, K. Ikossi, J. A. Roussos, W. Kruppa, D. Park, H. B. Dietrich, D. D. Koleske, A. E. Wickenden, and R. L. Henry, “Trapping effects and microwave power performance in AlGaN/GaN HEMTs,” IEEE Trans. Electron Devices, vol. 48, no. 3, pp. 465–471, Mar. 2001. [6] M. Sumiya, N. Ogusu, Y. Yotsuda, M. Itoh, S. Fuke, T. Nakamura, S. Mochizuki, T. Sano, S. Kamiyama, H. Amano, and I. Akasaki, “Systematic analysis and control of low-temperature GaN buffer layers on sapphire substrates,” J. Appl. Phys., vol. 93, no. 2, pp. 1311–1319, Jan. 2003. [7] L. Sugiura, K. Itaya, J. Nishio, H. Fujimoto, and Y. Kokubun, “Effects of thermal treatment of low-temperature GaN buffer layers on the quality of subsequent GaN layers,” J. Appl. Phys., vol. 82, no. 10, pp. 4877–4882, Nov. 1997. [8] G.-Y. Lee, H.-H. Liu, and J.-I. Chyi, “High-performance AlGaN/GaN Schottky diodes with an AlGaN/AlN buffer layer,” IEEE Electron Device Lett., vol. 32, no. 11, pp. 1519–1521, Nov. 2011. [9] J. Elsner, R. Jones, M. I. Heggie, P. K. Sitch, M. Haugk, Th. Frauenheim, S. Öberg, and P. R. Briddon, “Deep acceptors trapped at threading-edge dislocations in GaN,” Phys. Rev. B, Condens. Matter, vol. 58, no. 19, pp. 12 571–12 574, Nov. 1998. [10] S. M. Lee, M. A. Belkhir, X. Y. Zha, and Y. H. Lee, “Electronic structures of GaN edge dislocations,” Phys. Rev. B, vol. 61, no. 23, pp. 16 033– 16 039, Jun. 2000.
