Normally-off GaN recessed-gate MOSFET fabricated by ... - IOPscience

Applied Physics Express 7, 016502 (2014) http://dx.doi.org/10.7567/APEX.7.016502

Normally-off GaN recessed-gate MOSFET fabricated by selective area growth technique Yao Yao1, Zhiyuan He1, Fan Yang1, Zhen Shen1, Jincheng Zhang1, Yiqiang Ni1, Jin Li1, Shuo Wang1, Guilin Zhou1, Jian Zhong1, Zhisheng Wu1, Baijun Zhang1, Jinping Ao2, and Yang Liu1* 1 School of Physics and Engineering, State Key Laboratory of Optoelectronic Materials and Technologies, Sun Yat-Sen University, Guangzhou 510275, People’s Republic of China 2 Institute of Technology and Science, University of Tokushima, Tokushima 770-8502, Japan E-mail: [email protected]

Received November 6, 2013; accepted December 3, 2013; published online December 27, 2013 In this letter, a normally-off GaN recessed-gate MOSFET is demonstrated using a nonplasma gate recess technique, in which the access region with AlGaN/GaN heterostructure was selectively grown on a semi-insulating GaN/Si template to naturally form a recessed gate. The normally-off recessed-gate Al2O3/GaN MOSFET presents a high threshold voltage of 3.5 V and a maximum drain current density of 550 mA/mm (at a positive gate bias of 12 V). A maximum field-effect mobility of 170 cm2 V%1 s%1 and a large on/off current ratio of more than 107 was obtained, which indicates the high quality of the Al2O3/GaN interface. © 2014 The Japan Society of Applied Physics

he AlGaN/GaN heterostructure field-effect transistor (HFET) is a promising candidate for next-generation high-power and high-frequency applications owing to the superior properties of GaN-based materials, such as high breakdown electric field and high saturation velocity. For such applications, normally-off devices are necessary for fail-safe operation. The main methods to achieve normally-off AlGaN/GaN HFETs are commonly based on the dry-etching-based recessed gate,1–3) p-type gate,4,5) or fluorine-based ion implantation gate.6) These methods all require plasma treatment, which unavoidably introduces lattice damage to the active region, and further influences the reliability and stability of the device. Correspondingly, a novel normally-off recessed-gate AlGaN/GaN HFET formed by the selective area growth (SAG) technique,7) in which a thick AlGaN access region was selectively grown on a thin AlGaN/GaN heterostructure, was proposed. In this way, the damage introduced by the plasma treatment in drying recessed gate devices can be efficiently avoided.8) However, besides the lower threshold voltage (Vth < 1 V) limited by the Schottky gate, this SAG device also suffered from a higher access resistance in comparison with that of a conventional HFET. This may be attributed to the partial relaxation of regrown AlGaN on the thin AlGaN/GaN, which results in poor two-dimensional electron gas (2DEG) properties. In this work, a normally-off GaN recessed-gate MOSFET was fabricated using the SAG technique. The access region with the AlGaN/GaN heterostructure was selectively grown on a semi-insulating GaN/Si (SI-GaN/Si) template to naturally form a recessed gate, which eliminates the dryetching-induced lattice damage and maintains the atomically flat surface morphology in the gate region. Moreover, the location of the AlGaN/GaN heterointerface was moved far from the regrowth interface by the insertion of a thicker SAG-GaN buffer layer. Thus, the crystalline quality of the regrown access region is expected to be improved. Furthermore, by combining with an Al2O3 gate insulator obtained by atomic layer deposition (ALD), a high-performance normallyoff GaN MOSFET with high Vth is demonstrated. The SI-GaN/Si template used for SAG was first grown on a 2-in.-diameter Si(111) substrate by metal organic chemical vapor deposition (MOCVD). The epilayer consists of a 20 nm high-temperature AlN (HT-AlN, ³1100 °C) buffer layer and 1.4 µm undoped GaN layer with two 15 nm low-temperature

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AlN (LT-AlN, ³700 °C) interlayers (the thickness of the top GaN layer is 800 nm).9) The undoped GaN layer on the silicon substrate shows high resistivity, which is considered to be due to the acceptor-like edge dislocations compensating the n-type background carriers.10,11) This can be confirmed from the good pinch-off features of AlGaN/GaN HFETs based on the SI-GaN/Si template; the off-state leakage current at Vds = 20 V reaches a general level as low as 10¹3 mA/mm,7,9) which is comparable to other published data of unintentional compensation doped highly resistive GaN.10,12–14) The SI-GaN/Si template was dipped in H2SO4 and HCl solutions for 10 min before the regrowth process to ensure a clean SAG interface. Then, the regrowth process was performed over the SI-GaN/Si template by MOCVD, in which the gate region was masked by a 100-nm-thick SiO2 film deposited by plasma-enhanced chemical vapor deposition (PECVD). Thus, the regrowth process was performed selectively in the access region (the gate region was masked by SiO2) to naturally form a recessed gate structure. The regrown epilayer is composed of, first, a 90-nm-thick GaN buffer layer and, subsequently, a 25-nm-thick Al0.3Ga0.7N barrier layer, by which a high-quality 2DEG conductive channel can be expected. After device isolation, the SiO2 mask pattern was removed using a buffered oxide etch (BOE) solution. Then, the source and drain ohmic electrodes consisting of Ti/Al/Ni/Au were deposited by evaporation and annealed at 830 °C for 30 s in nitrogen ambient. A gate dielectric layer of 30 nm ALD Al2O3 was deposited at 300 °C. Finally, the gate metal Ni/Au was deposited after the ohmic electrode windows were opened using the diluted BOE solution. The gate width (Wg), gate length (Lg), length between gate and source (Lgs), and length between gate and drain (Lgd ) are 100, 3.5, 2, and 4 µm, respectively, in which the length of the SiO2 masked region Lg0 is 1.5 µm. The proposed structure is schematically shown in Fig. 1. The properties of the access region, which contains a regrown AlGaN/GaN heterostructure, were evaluated first, because the conductive performance of the device is strongly dependent on them. The surface morphology of the access region was directly observed by atomic force microscopy (AFM) measurements [see Fig. 2(a)], because it can reflect the roughness of the AlGaN/GaN interface to some extent. The clear step flow growth mode with the root-mean-square (RMS) roughness of 0.393 nm for a scanned area of 3 © 3

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Fig. 1. Schematic cross section of fabricated normally-off GaN recessed MOSFET.

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(b) Fig. 2. Surface morphology of (a) regrown and (b) conventional AlGaN/ GaN heterostructure in access region observed by AFM with a scanned area of 3 © 3 µm2. The RMS values are 0.393 and 0.343 nm, respectively.

µm2, which is similar to the conventional AlGaN/GaN surface [see Fig. 2(b), with RMS value of 0.343 nm], indicates that the high crystalline quality in the access region was obtained by using a regrown AlGaN/GaN heterostructure on the SI-GaN/Si template. It can be explained as follows. By the insertion of a thick SAG-GaN buffer layer between the SI-GaN/Si template and the SAG-AlGaN barrier layer, the location of the AlGaN/GaN heterointerface is moved far

from the regrowth interface, so the influence of the regrowth interface on the quality of the SAG layers is mitigated and the SAG layers can coalesce better and accordingly result in a flat surface and interface. Thus, the improved conductive performance in the access region was expected, as the electron mobility of the 2DEG formed at the AlGaN/GaN interface strongly depends on the interface roughness.15) To validate it, we evaluated the electrical properties of the access region by transmission line measurement (TLM), in which the sheet resistance (Rsh) and specific contact resistance (rc) of the SAG AlGaN/GaN sample were significantly reduced to 219 ³/□ and 0.22 ³0mm, respectively, in comparison with those of the SAG AlGaN sample in Ref. 7 (Rsh = 1036 ³/□, rc = 1.0 ³0mm). The results confirm the high crystalline quality of the SAG AlGaN/GaN heterostructure and improved conductive performance in the access region. Besides the access region, the property of the recessed gate channel region is another key factor that influences the conductive performance of the whole device. The AFM measurement of the mask-protected SI-GaN in the recessed gate region shows a clear flow step surface, which is almost the same with that of the as-grown GaN and much lower than that of the sample recessed by dry etching.8) Thus, the SAG method, by which the recessed gate was naturally formed, can help eliminate the surface damage caused by plasma etching and maintain a much flatter and natural semiconductor surface,8,16) which may improve the interface quality between the Al2O3 gate insulator and the GaN surface. Such conjecture was confirmed by capacitance–voltage (C–V) measurement of the Ni/Al2O3/i-GaN circular MOS diode with a 300 µm anode diameter [see Fig. 3(a)]. The fabrication process of the MOS diode was compatible with that of the SAG-MOSFET, whose ohmic cathode was formed on the regrown AlGaN/GaN, and Al2O3 was deposited by ALD on the SI-GaN surface. The C–V curve shows that a good electron accumulation appears under the forward bias, which indicates the formation of a high-quality interface between the gate insulator and SI-GaN surface. A clockwise hysteresis is observed in the C–V curves of the MOS diode. The small hysteresis of about 0.25 V, which was determined by the flat voltage difference (¦VFB) of the curves measured by positive and negative sweeping, is attributed to the low density of interface trap charges and/or oxide trap charges.17–19) Furthermore, using ®FE = gmL/(WCMOSVDS), the maximum field-effect mobility of 170 cm2 V¹1 s¹1 is extracted from transfer properties [see Fig. 3(b)] when the SAG-MOSFET works at the linear region (Vd = 0.1 V), which is comparable to the values reported by others.20,21) This high mobility confirms the high-quality MOS interface and good conductive performance at the recessed gate region. The true normally-off operation and large on/off current ratio of more than seven orders of magnitude were confirmed in the semilog scale transfer properties [see Fig. 4(a)]. A high Vth of 3.5 V and peak transconductance of 85 mS/mm were obtained [see Fig. 4(b), the Vth was determined from the gate bias intercept of the extrapolation of the drain current curve in the transfer characteristics]. We believe that the high Vth is due to the excellent MOS interface properties in the recessed gate region, as well as the insertion of a high-quality gateinsulating dielectric Al2O3, by which the gate voltage was partially shared when forming an accumulation electron at

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Fig. 3. (a) C–V characteristics of Ni/Al2O3/u-GaN MOS diode at measurement frequency of 100 kHz; hysteresis measurement was from negative to positive (¹4 to 12 V), and then swept back; the total sweeping time was 62 s. (b) Transfer characteristics at Vd = 0.1 V and calculated fieldeffect mobility.

(b) Fig. 5. (a) Comparison of dc and pulsed output characteristics of the device with 100 µm gate width. The inset shows the variation trend of onresistance with switching frequency for SAG-MOSFET and conventional MOSHFET. (b) Benchmark of ID_max and Vth of normally-off GaN MOSFETs for power switching applications. The Vth was uniformly determined from the gate bias intercept of the extrapolation of the drain current curve in the transfer characteristics (PKU: Peking Univ., KNU: Kyungpook National Univ., NCTU: National Chiao-Tung Univ., HKUST: Hong Kong Univ. of Science and Technology).

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(b) Fig. 4. (a) Transfer curves of fabricated MOSFET in semilog scale, (b) transfer characteristics with gate bias sweeping rate of 0.48 V/s (with sweeping time of 66 s) at Vd = 8 V.

the Al2O3/SI-GaN interface [see Fig. 3(a)]. It is worth mentioning that a clockwise hysteresis is also observed in the ID–VGS curves [see Fig. 4(b)]. The hysteresis of Vth is 0.25 V; it is almost the same as the hysteresis observed in C–V curves [see Fig. 3(a)]. The density of traps can be estimated to be 2.9 © 1011 cm¹2 using Dit = CMOS¦Vth/q. It is about one order of magnitude lower than those reported in the Al2O3/ GaN MOSFET with a gate recess (2.6 © 1012 cm¹2 14)) and the Al2O3/AlGaN/GaN MOSHFET without a gate recess (1.4 © 1012 cm¹2 22)), which confirms the high quality of

the MOS interface between the Al2O3 and the masked SI-GaN. Figure 5(a) shows the comparison of the dc and pulsed output characteristics of the device, and the inset shows the increase ratio of on-resistance (Rpulse/Rdc). The quiescent biases for pulse measurement are VD = 20 V and VG = 0 V. The switching frequency varies from 100 Hz to 10 kHz, and the duty ratio is 20%. The VD of 20 V is mainly limited by the breakdown voltage, which is about 50–100 V (not shown here). This low breakdown voltage is attributed to the high conductive properties of the LT-AlN interlayer, which was embedded in the SI-GaN.9) It can be seen that there is no significant current collapse with such criteria. The pulse ID–VD characteristics of the planar gate MOSHFET based on the conventional AlGaN/GaN heterostructure on silicon substrate were also evaluated for comparison [see inset of Fig. 5(a), the quiescent biases are VD = 20 V and VG = ¹12 V for conventional MOSHFET]. The variation trend of on-resistance, which increases with switching frequency, is almost the same for SAG-MOSFET and conventional MOSHFET, and the increase ratios of on-resistance are as low as 1.31 and 1.27 at the frequency of 10 kHz, respectively.

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It can be confirmed that the SAG interface and SAG process have no influence on current collapse. Moreover, a much higher maximum drain current density (ID_max) of 550 mA/mm with a low on-resistance (9.5 ³0mm) was obtained from the dc output characteristics in comparison with the case in Ref. 7. It also indicates that a high-quality conductive channel was formed, which includes both in the access region and in the recessed gate channel region, as mentioned above. Figure 5(b) shows the benchmark of ID_max and Vth (Vth was uniformly determined from the gate bias intercept of the extrapolation of the drain current curve in the transfer characteristics for comparison) of normally-off GaN MOSFETs for power switching applications.3,10,12–14,16,20,23–25) The high Vth of 3.5 V with a high ID_max of 550 mA/mm achieved in this work is one of the best results among the published reports. A normally-off recessed-gate GaN MOSFET was fabricated utilizing the nonplasma low-damage SAG technique. The device has a high Vth of 3.5 V, a maximum drain current density of 550 mA/mm, a maximum field-effect mobility of 170 cm2 V¹1 s¹1, and a large on/off current ratio of more than 107. It benefits from the fact that the SAG technique not only eliminates the plasma-bombardment-induced lattice damage, maintains the atomically flat surface morphology in the gate region, and results in a high-quality MOS interface, but also improves the crystalline quality of the regrown access region by the insertion of a thicker SAG-GaN buffer layer to move the location of the AlGaN/GaN heterointerface far from the regrowth interface. In addition, no significant current collapse was observed in the proposed device. All the performances presented here for the proposed device imply that the SAG technique is promising for the fabrication of high-performance normally-off GaN-based MOSFETs. Acknowledgments The work was supported by the Natural Science Foundation of China (Grant Nos. 51177175 and 61274039), “973” Key Fundamental Research Project of China (Grant Nos. 2011CB301903 and 2010CB923200), Ph. D. Programs Foundation of Ministry of Education of China (Grant No. 20110171110021), International Science and Technology Collaboration Program of China (Grant No. 2012DFG52260), and “863” National HighTech R&D Program of China (Grant No. 2011AA03A101).

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