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Normally OFF Trench CAVET With Active Mg-Doped GaN as Current Blocking Layer Dong Ji, Matthew A. Laurent, Anchal Agarwal, Wenwen Li, Saptarshi Mandal, Stacia Keller, and Srabanti Chowdhury Abstract — A normally OFF trench current aperture vertical electron transistor (CAVET) was designed and successfully fabricated with Mg-doped p-GaN current blocking layers. The buried Mg-doped GaN was activated using a postregrowth annealing process. The source-to-drain body diode showed an excellent p-n junction characteristics, blocking over 1 kV, sustaining a maximum blocking electric field of 3.8 MV/cm. Three-terminal breakdown voltages of trench-CAVETs, measured up to 225 V, were limited by dielectric breakdown. This paper highlights the achievement of the well-behaved buried p-n junction that has been a formidable challenge in the success of vertical GaN devices. Index Terms — Current aperture vertical electron transistor (CAVET), gallium nitride (GaN), power transistor, vertical transistor.
I. I NTRODUCTION OWER switches using wide bandgap semiconductors, such as silicon carbide (SiC) and gallium nitride (GaN), present the potential to serve the needs of next-generation power converters. Their high breakdown electric field and high operation temperature make them attractive solutions for power converters that currently rely on Si-based devices. From the material point of view, both SiC and GaN have greater than 10× larger breakdown electric field than Si, but what makes GaN a more promising emerging technology is the high electron mobility (1100 cm2 /Vs) in the bulk material [1]. By taking advantage of the availability of high-quality bulk GaN substrates, GaN vertical devices are being developed, which offers significant advantages over lateral devices in applications over 10 kW. Prior to this paper, a variety of GaN vertical structures have been proposed and reported, such as vertical junction FETs [2], [3], MOSFETs [4], and current aperture vertical electron transistors (CAVETs) [5], [6].
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Manuscript received October 1, 2016; revised November 17, 2016; accepted November 17, 2016. Date of publication December 16, 2016; date of current version February 24, 2017. This work was supported by the ARPA-E SWITCHES Program. The review of this paper was arranged by Editor J. Vobecky. D. Ji, W. Li, S. Mandal, and S. Chowdhury are with the Department of Electrical and Computer Engineering, University of California at Davis, Davis, CA 95616 USA (e-mail:
[email protected]). M. A. Laurent was with the Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA 93106 USA. He is now with the Department of Electrical and Computer Engineering, University of California at Davis, Davis, CA 95616 USA. A. Agarwal and S. Keller are with the Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA 93106 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2016.2632150
Fig. 1. Schematic of GaN CAVETs. (a) Conventional GaN CAVET with implanted p-GaN as CBLs. (b) Proposed trench CAVET with MOCVD p-GaN as CBLs.
It is worth mentioning that a CAVET, which embodies a lateral HEMT geometry merged with a vertical bulk drift region, utilizes the benefit of a high electron mobility channel. Therefore, compared with other vertical device structures, a CAVET, by its very design, presents a pathway to achive smaller specific ON-resistance (RON,SP ). From our previous theoretical study, we have concluded that GaN CAVETs have the potential for faster switching speed and lower power losses than commercial SiC devices at voltage levels of 1.2 kV and above, owing to the high bulk electron mobility in the drift region as well as in the channel [7]. The conventional GaN CAVET, schematically shown in Fig. 1(a), has been fabricated and reported using Mg-implanted p-GaN for the current blocking layer (CBL) [8]. However, two key issues that are yet to be addressed are the out diffusion of implanted [Mg] during high-temperature regrowth process and the difficulty in achieving normally OFF operation. In this paper, a trench CAVET based on a bulk GaN substrate was designed and fabricated using a metal organic chemical vapor deposition (MOCVD) regrown channel and aperture. The schematic of the trench CAVET is shown in Fig. 1(b). Instead of using Mg-implanted p-GaN for the CBL, the trench CAVET adopts MOCVD-grown Mg-doped p-GaN as the CBL material. Previously reported devices [9] were fabricated with the regrowth process that planarized the sample prior to AlGaN deposition and two-dimensional electron gas (2-DEG) formation. Our trench CAVET design places the channel at the sidewall of the etched trench, which enables the normally OFF operation. This paper is organized into five sections, with Section II–IV dedicated to the technical discussion. In Section II, the device fabrication procedure is described in detail. Section III
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Fig. 4. Side profile of the CAVET from SEM.
Fig. 2. Schematic of the process flow steps. (a) Base structure includes a MOCVD-grown 400-nm Mg-doped GaN layer on the top of a 5.3-µm lightly doped n-type GaN and conductive nC GaN substrate. (b) 500-nm-deep trench was etched using an ICP on the aperture region. (c) Si3 N4 /AlGaN/GaN MOCVD regrowth. (d) Postregrowth anneal in nitrogen at 700 °C for 20 min to diffuse out hydrogen through a via etched 200-nm-deep by ICP. (e) Nickel was deposited as the source-connected contact for buried p-GaN CBLs. (f) Full device with source, gate, and drain metals.
trench (larger L trench ), a shorter trench (smaller L trench ) features higher defect density at the bottom, which might degrade the device performance by increasing the device leakage. Moreover, the sidewall growth rate is significantly higher than the c-plane growth, which filled up the trench reducing its opening (which corresponds to the length by definition) after regrowth. After the regrowth, 200-nm-deep via holes were etched along the source traces, using reactive ion etching (RIE) and ICP, respectively, to remove Si3 N4 /AlGaN/GaN from the top of the p-GaN CBLs. The sample was subsequently annealed in nitrogen at 700 °C for 20 min to diffuse out the hydrogen [10], [11]. Nickel was deposited through the via holes to contact the p-GaN CBLs. A Ti/Al metal stack was used to form the source contact after the top SiN was etched from the rest of the defined region using RIE, followed by a 600 °C anneal to form ohmic contacts. The drain contact was deposited on the back of the substrate using the same metal stack as the source and Ni/Au/Ni formed the gate contact. III. D EMONSTRATION OF ACTIVE CBL
Fig. 3. SEM figures of the postregrown trenches with different lengths (a) 10 and (b) 4 µm.
discusses the source-to-drain body diode behavior. It was found to be a well-behaved p-n diode with a breakdown voltage over 1 kV, and indicates a sucessful realization of buried p-GaN CBL. The device chrarterization and discussion are elaborated in Section IV. II. D EVICE FABRICATION The fabrication process is shown in Fig. 2. The epitaxial device structure was grown on a Furukawa n-GaN free-standing substrate via MOCVD. The epitaxial structure began with a 2-µm n-GaN layer with a doping desnity of 2 × 1018 cm−3 , followed by a 5.3 µm unintential doped n-GaN layer to serve as the drift region (doping density ∼1 × 1016 cm−3 ). This was then followed by the growth of a 400-nm-thick layer of p-GaN ([Mg] = 5 × 1019 cm−3 ) to form the CBL. A 500-nm-deep trench was etched using an inductively coupled plasma (ICP) process to form the aperture region. After the aperture patterning, the sample went through the MOCVD regrowth of the channel and cap region, which consisted of 140-nm-thick GaN to form the channel, followed by a 25-nm-thick Al0.3 Ga0.7 N, covered with a 30-nm-thick MOCVD Si3 N4 . Fig. 3 shows the scanning electron microscopy (SEM) images of the trenches after regrowth. Compared with a longer
Fig. 4 shows the SEM image of the CAVET side profile. The figure shows part of the regrown HEMT structure and the p-GaN CBL under the gate metal. The white-color layer is the 400-nm p-GaN, which forms a p-n junction with the n-GaN drift region, as shown in Fig. 4. The source-to-drain body diode using a two-terminal measurement shows a p-n diode-like I –V characteristic, as shown in Fig. 5. The turn-ON voltage is 3 V, which is consistent with the values reported on bulk GaN p-n diodes [12], [13]. The high-voltage blocking capability of the source-to-drain body diode is shown in Fig. 6, where the reverse breakdown characteristics show blocking up to 1 kV, demonstrating a blocking electric field of 3.8 MV/cm. This is very close to the theoretical breakdown field value of GaN [14]. IV. E-M ODE CAVET C HARACTERISTICS Fig. 7 shows the I –V characteristics of the CAVET and the corresponding transfer curve is shown in Fig. 8. The saturation current density is 62 A/cm2 and the threshold voltage is 20 V. The I –V characteristics of a zero-trench CAVET, which was measured as a planar device, are shown in Fig. 9. This planar device shows a comparable high ON-state resistance. It is important to mention that the pinch-off voltage of the planar device is less than −10 V, indicating that there is a large amount of charge located in the AlGaN/GaN heterostructure.
JI et al.: NORMALLY OFF TRENCH CAVET WITH ACTIVE Mg-DOPED GaN AS CBL
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Fig. 5. I–V characteristics of the source-drain body diode. Fig. 8. Transfer curve (red curve) and the gate leakage (blue curve) of the CAVET showing a 20 V threshold voltage.
Fig. 6. diode.
Reverse breakdown characteristics of the source-drain body
Fig. 9. I–V characteristics of a planar device.
Fig. 7. I–V characteristics of the CAVET.
The conclusions drawn from CAVET and HEMT measurements on zero-trench devices verify the fact that the transistors displayed high Ron primarily due to high source resistance. An unoptimized annealing temperature resulted in poor source conatcs offering high contact resistance. In an attempt to avoid spiking of source metals deep into the drift region (a common outcome of annealed HEMT contacts [15]), the anneal temperature was conservatively maintained at 600 °C, which resulted in a significant source resistance. In the future, a different source metal stack optimized for low anneal temperature will be pursued as a solution to realize the low source resistance [16], [17]. Alternatively, implanted sources can alleviate this problem. The gates covering sidewall of the aperture, being a nonpolar plane, has no polarization-induced charges. It can
Fig. 10. OFF-state characteristics of the CAVETs.
also be safely assumed that the mass flow during regrowth from the sidewall carried a significant concentration of Mg toward the aperture. The lack of the 2-DEG combined with the Mg presence resulted in a high positive threshold voltage (20 V). The OFF-state characteristics of the CAVETs are shown in Fig. 10. The breakdown voltage increases as the trench length shrinks. For a given trench length of 2 µm, the transistor breakdown voltage is 225 V. The electric field distribution in
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temperature (600 °C), as well as Mg-incorporation into the regrown AlGaN/GaN sidewall. The transistor breakdown voltage of 225 V was limited by gate to drain leakage. ACKNOWLEDGMENT The authors would like to thank Dr. T. Hiedel, Dr. I. Kizilyalli, Dr. E. Carlson, and Dr. D. Cunnignham for supporting this work under the ARPA-E SWITCHES Program. The fabricaton process was done at ASU NanoFab. R EFERENCES
Fig. 11. Simulated electric field distribution in a trench-CAVET under a VDS D 300 V.
Fig. 12. Two-terminal measurements of the breakdown of gate to drain.
a CAVET at the OFF-state under a VDS = 300 V is shown in Fig. 11. The high electric field regions are located at the corner of the trench, which is one of the causes of premature breakdown of the device. Since the source-to-drain diode withstands over 1 kV, as shown in Section II, it can be concluded that breakdown of the three-terminal device was limited by the gate-to-drain breakdown voltage. Fig. 12 shows two terminal I –V measurements between gate and drain. The gate-to-drain breakdown mirrored the three-terminal breakdown characteristics, including its dependence on the trench length. In a well-designed CAVET, the trench length must be chosen, such that the CBL screens the gate dielectric from the applied field. With the increasing distance between the two halves of the p-type CBL (denoted by increasing trench length), the gate region becomes more exposed to high electric field generated by the drain bias, allowing higher leakage current. V. C ONCLUSION In summary, normally OFF trench CAVETs on bulk GaN substrate were fabricated and characterized. The buried Mg-doped p-GaN CBL was activated successfully implementing a post-MOCVD regrowth annealing process. The buried p-n body diode sustained remarkably a high breakdown electric field of 3.8 MV/cm. The maximum saturation current was limited to 62 A/cm2 , due to high source contact resistance as a consequence of low source metal annealing
[1] P. Kruszewski et al., “Vertical schottky diodes grown on low-dislocation density bulk GaN substrate,” in Proc. Int. Workshop Nitride Semiconductors, Aug. 2014. [2] I. C. Kizilyalli and O. Aktas, “Characterization of vertical GaN p-n diodes and junction field-effect transistors on bulk GaN down to cryogenic temperatures,” Semicond. Sci. Technol., vol. 30, no. 12, p. 24001, Nov. 2015. [3] D. Ji and S. Chowdhury, “Design of 1.2 kV power switches with low Ron using GaN-based vertical JFET,” IEEE Trans. Electron Devices, vol. 62, no. 8, pp. 2571–2578, Aug. 2015. [4] W. Li and S. Chowdhury, “Design and fabrication of a 1.2 kV GaNbased MOS vertical transistor for single chip normally off operation,” Phys. Status Solidi A, vol. 213, no. 10, pp. 2714–2720, Jul. 2016, doi: 10.1002/pssa.201532575. [5] I. Ben-Yaacov, Y.-K. Seck, U. K. Mishra, and S. P. DenBaars, “AlGaN/GaN current aperture vertical electron transistors with regrown channels,” J. Appl. Phys., vol. 95, no. 4, p. 2073, 2004. [6] S. Chowdhury, B. L. Swenson, and U. K. Mishra, “Enhancement and depletion mode AlGaN/GaN CAVET with Mg-ion-implanted GaN as current blocking layer,” IEEE Electron Device Lett., vol. 29, no. 6, pp. 543–545, Jun. 2008. [7] D. Ji, Y. Yue, J. Gao, and S. Chowdhury, “Dynamic modeling and power loss analysis of high-frequency power switches based on GaN CAVET,” IEEE Trans. Electron Devices, vol. 63, no. 10, pp. 4011–4017, Oct. 2016. [8] S. Chowdhury and U. K. Mishra, “Lateral and vertical transistors using the AlGaN/GaN heterostructure,” IEEE Trans. Electron Devices, vol. 60, no. 10, pp. 3060–3066, Oct. 2013. [9] M. Kanechika et al., “A vertical insulated gate AlGaN/GaN heterojunction field-effect transistor,” Jpn. J. Appl. Phys., vol. 46, no. 21, pp. L503–L505, May 2007. [10] S. Nakamura, N. Iwasa, M. Senoh, and T. Mukai, “Hole compensation mechanism of P-type GaN films,” Jpn. J. Appl. Phys., vol. 31, no. 5A, pp. 1258–1266, May 1992. [11] S. Nakamura, T. Mukai, and M. Senoh, “Thermal annealing effects on P-type Mg-doped GaN films,” Jpn. J. Appl. Phys., vol. 31, no. 2B, pp. L139–L142, Feb. 1992. [12] I. C. Kizilyalli, A. P. Edwards, O. Aktas, T. Prunty, and D. Bour, “Vertical power p-n diodes based on bulk GaN,” IEEE Trans. Electron Devices, vol. 62, no. 2, pp. 414–422, Feb. 2015. [13] I. C. Kizilyalli, “High voltage vertical GaN p-n diodes with avalanche capability,” IEEE Trans. Electron Devices, vol. 60, no. 10, pp. 3067–3070, Oct. 2013. [14] A. M. Ozbek and B. J. Baliga, “Planar nearly ideal edge-termination technique for GaN devices,” IEEE Electron Device Lett., vol. 32, no. 3, pp. 300–302, Mar. 2011. [15] S. Chowdhury, “AlGaN/GaN CAVETs for high power switching application,” Ph.D. dissertation, Dept. Elect. Comput. Eng., Univ. California, Santa Barbara, CA, USA, 2010. [16] A. Malmros, H. Blanck, and N. Rorsman, “Electrical properties, microstructure, and thermal stability of Ta-based ohmic contacts annealed at low temperature for GaN HEMTs,” Semicond. Sci. Technol., vol. 26, no. 7, p. 075006, Mar. 2011. [17] B. D. Jaeger et al., “Au-free CMOS-compatible AlGaN/GaN HEMT processing on 200 mm Si substrates,” in Proc. 24th Int. Symp. Power Semiconductor Devices ICs, Jun. 2012, pp. 49–52.
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