IEEE ELECTRON DEVICE LETTERS, VOL. 35, NO. 7, JULY 2014
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Development and Electrical Properties of (Ca0.7Sr0.3) (Zr0.8Ti0.2)O3 Thin Film Applied to Embedded Decoupling Capacitors Seung-Hwan Lee, Hong-Ki Kim, Min-Gyu Kang, Chong-Yun Kang, Sung-Gap Lee, Young-Hie Lee, and Jung-Rag Yoon
Abstract— A formed device embedded-type 0402 sized (Ca0.7 Sr0.3 )(Zr0.8 Ti0.2 )O3 (CSZT) embedded capacitor was fabricated for use in embedded printed circuit board. The capacitance and dielectric loss of the CSZT embedded capacitor were 406.1 pF and 0.015, respectively, at 1 MHz. The CSZT embedded capacitor exhibits stable capacitance with varying applied voltage and C Zero G (−55 °C–125 °C, delta C/C = ±30 ppm/°C) properties. The measured values of equivalent series resistance and equivalent series inductance were 6.1 and 62.39 μH, respectively. The leakage current density was 0.78 μA/cm2 at 3 V of applied voltage. These electrical properties indicate that the CSZT embedded capacitor holds promise for use as an embedded passive capacitor. Index Terms— CSZT, embedded capacitor, FDE.
I. I NTRODUCTION
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HE market for portable devices such as smart phones and tablet PCs has expanded and technological trends demand miniaturization, lightness, and high-functionalization. For most portable devices, the number of passive components (capacitors, resistors, inductors) and their occupied areas are far greater than those of the active components (IC). The passive components tend to have extremely small dimensions because of a built-in embedded PCB. Most attention regarding passive components has focused on the capacitors, because the ratio of capacitors to total passive components may exceed 60%. Most passive components are still provided as surface
Manuscript received April 7, 2014; revised April 22, 2014; accepted April 22, 2014. Date of publication May 12, 2014; date of current version June 24, 2014. This work was supported by the Fundamental Research and Development Program for Core Technology of Materials funded by the Ministry of Trade, Industry and Energy (MOTIE) of Korea. The review of this letter was arranged by Editor A. Chin. S.-H. Lee is with the Department of Electronic Materials Engineering, Kwangwoon University, Seoul 139-701, Korea, and also with the Research and Development Center, Samwha Capacitor, Yongin 449-884, Korea. H.-K. Kim and Y.-H. Lee are with the Department of Electronic Materials Engineering, Kwangwoon University, Seoul 139-701, Korea. M.-G. Kang and C.-Y. Kang are with the Electronic Materials Research Center, Future Convergence Research Division, Korea Institute of Science and Technology, Seoul 136-791, Korea. S.-G. Lee is with the Department of Ceramic Engineering, Engineering Research Institute, Gyeongsang National University, Jinju 660-701, Korea. J.-R. Yoon is with the Research and Development Center, Samwha Capacitor, Yongin 449-884, Korea (e-mail:
[email protected]). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2014.2320295
mounted device (SMD) types. Although SMD type passive components are of very small size, they occupy a large portion of the substrate and have inferior electrical properties due to longer interconnection length and low reliability owing to the presence of numerous solder joints. Many studies have been performed to resolve these problems, and in particular embedded capacitors, located in one of the inner layers of the PCB, have been widely investigated. The embedded capacitors have the following major benefits: (1) reduction of surface area; (2) no separate interconnects to the substrate; (3) superior electrical properties; (4) lower cost; and (5) ease of processing [1]. In this letter, we fabricated a 0402 sized embedded capacitor with a metal-insulator-metal (MIM) structure. The CSZT ceramics with perovskite structure were used as a dielectric layer, because this material and their ratio of components are suitable for stable capacitance with varying applied voltage and C0G properties [2], [3]. In addition, Pt was used as top and bottom electrodes due to their stability in high temperature [4]. II. E XPERIMENTAL P ROCEDURES A CSZT ceramics target of the RF sputtering method was fabricated by the conventional mixed oxide method. The starting materials were CaCO3 (Aldrich, 99%), SrCO3 (Aldrich, 99.93%), TiO2 (Aldrich, 99.76%) and ZrO2 (Aldrich, 99.8%). Those materials were weighed according to the composition of the CSZT, the weight ratio of zirconia ball to powder in the mill was 1:1 and ethyl alcohol was used as a process control agent. The slurry was dried at 100 °C for 24 h and calcined at 1100 °C for 10 h. The calcined powders were screened by mesh (#325) and then pressed to cylindrical pellets in steel die ( = 2 inch). The CSZT samples were sintered at 1500 °C for 4 h. The 0402 (400 μm × 200 μm) sized CSZT embedded capacitors were produced using Micro Electro Mechanical System (MEMS) process. The CSZT films with 100 nm thickness were deposited by RF sputtering on a Pt/Ti/SiO2 /Si substrate. The following deposition conditions were employed for the RF sputtering: (1) deposition temperature: 700 °C; (2) Ar/O2 ratio: 9:1; (3) RF power: 80 W; and (4) working pressure: 20 mTorr. After rapid thermal annealing (RTA) at 800 °C for 5 min, Pt top electrodes with 200 nm thickness
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IEEE ELECTRON DEVICE LETTERS, VOL. 35, NO. 7, JULY 2014
Fig. 2. (a) X-ray diffraction pattern of CSZT thin film and (b) SEM image of CSZT embedded capacitor.
Fig. 1.
Experimental flow chart of 0402 sized CSZT embedded capacitor.
were deposited on the CSZT film by DC sputtering. The Pt top electrodes and CSZT films were etched by inductively coupled plasma (ICP) and reactive ion etching (RIE), respectively. A SiO2 passivation layer with 500 nm thickness was deposited by RF sputtering at room temperature. Two via holes were formed in the SiO2 passivation layer to connect the external top and bottom electrodes with the inner layers. Lastly, Pt external electrodes were deposited on the top of the MIM capacitor and external electrodes were divided into top and bottom by ICP etching. The MIM capacitors were annealed at 300 °C for 5 min by rapid thermal annealing (RTA). A flowchart of the overall experiment is shown in Fig. 1. The top surface of the CSZT embedded capacitor was observed by a scanning electron microscope (SEM). The dielectric properties, ESL, and ESR were measured using an impedance analyzer (Agilent 4294A) from 1 kHz to 1 MHz within a temperature range of −55 °C to +125 °C. The leakage currents were obtained by a Radiant Technologies Precision Premier II Test System, Keithley 4200 Semiconductor Characterization System. III. R ESULTS AND D ISCUSSION Figure 2 (a) shows the XRD pattern of the CSZT thin film. The XRD pattern indicates that the CSZT phase was well crystallized. A top view of the CSZT embedded capacitor is shown in Fig. 2(b). Figure 3 (a) shows the capacitance and dielectric loss as a function of frequency for the CSZT embedded capacitor. The measured capacitance and dielectric loss decreased slightly (but not significantly) with respect to the frequency. From above results, it was confirmed that the dielectric properties of CSZT embedded capacitor are stable depending on frequency [5]. The capacitance, dielectric constant, and dielectric loss of the CSZT embedded capacitor were 406.1 pF, 55.5, and 0.015, respectively, at 1 MHz. Figure 3 (b) shows the capacitance-voltage plot by applying sweeping voltage from −5 V to +5 V at 100, 500, and 1000 kHz. From the C-V plot, it shows stable
Fig. 3. (a) Capacitance, dielectric loss, (b) Capacitance-voltage plot, (c) temperature stability, (d) ESR, and ESL of CSZT embedded capacitor.
capacitance with varying applied voltage at 100, 500, and 1000 kHz. In addition, we measured capacitance variation at different temperature ranged from −55 °C ∼ 125 °C at 100 kHz as shown in Fig. 3 (c). As a result, we obtained the C0G (−55 °C ∼ 125 °C, delta C/C = ±30 ppm/ °C) properties. Figure 3 (d) shows plots of the ESR (equivalent serial resistance) and ESL (equivalent serial inductance) as functions of frequency. Because the ESR is a significant parameter, manufacturers must be able to reduce ESR for device applications. From the ESR plot as shown in Fig. 3 (d), the ESR decreased with increasing frequency This is caused by the effect of frequency on the dielectric resistance. The ESR consists of dielectric loss, electrode loss, and the CSZT/Pt interface. The CSZT embedded capacitor applied to a thin film process shows a value of approximately 6.1 at 1 MHz. Kim et al reported that the frequency-dependent ESR due to dielectric and skin losses is dominant in low and high frequency ranges, respectively [6]–[8]. The low ESR value of the CSZT embedded capacitor is ascribed to the low electrode loss resulting from the thinner dielectric layer. The ESL value was determined by the length and width of the electrode. The CSZT embedded capacitor shows a low ESL value of 62.39 μH at 1 MHz due to the reduced length and width of the electrode. This low ESL is considered to be useful for application to high-frequency devices.
LEE et al.: DEVELOPMENT AND ELECTRICAL PROPERTIES OF CSZT THIN FILM
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conduction mechanism of the CSZT embedded capacitor was deduced to be SE at all electric field range due to their reasonable optical dielectric constant. IV. C ONCLUSION
Fig. 4. (a) Current density versus applied voltage curves at applied voltage from 0 to 12 V according to various temperatures ranging from 25 to 85 °C, (b) Ln(J/E2 ) versus 1/E plots, (c) Ln(J) versus E1/2 plot, and (d) Ln(J/E) versus E1/2 plot.
Figure 4 (a) shows leakage current density versus applied voltage curves of the fabricated CSZT embedded capacitor. Embedded capacitors are typically utilized in electronic devices with operating voltage of 3 V. In the case of the fabricated CSZT embedded capacitor, the leakage current density is 0.78 μA/cm2 at an applied voltage of 3 V at 25 °C. Being lower than 1 μA/cm2 at an operating voltage of 3 V, this value is suitable for embedded capacitor applications [9]. In addition, it was confirmed that the breakdown did not occur until an applied voltage of 12 V. To investigate a leakage current mechanism of the CSZT embedded capacitor, the Ln(J/E2 ) versus 1/E for FowlerNordheim tunneling (FN), Ln(J) versus E1/2 for Schottky emission (SE), and Ln(J/E) versus E1/2 for modified-Schottky emission (M-S) and Poole-Frenkel emission (PF) were plotted based on the current density versus applied voltage curves as shown in Fig. 4.(b), (c), and (d) [10]–[14]. From the FN plots as shown in Fig. 4.(b), we could confirm the FN tunneling is not dominant. Because, the leakage currents curves with various temperature ranges show not the temperature dependence but electric field dependence [14]. In order to clarify which conduction mechanism is dominant among the SE, M-S, PF conduction mechanism, reasonable values of the optical dielectric constant (= n 2 , where n is the refractive index), was calculated by conduction mechanism formulas and the linearized curves of Ln(J) and Ln(J/E) as a function of E1/2 yields a straight line as shown if Fig. 4 (c) and (d) [14]. In the case of the CSZT material, it was confirmed that the reasonable optical dielectric constant range is from 2.99 to 4.62 obtained by ellipsometry measurement [inset of Fig. 4 (c)]. The calculated optical dielectric constants were KSE = 3.12, KM−S = 19.57, and KPF = 78.27. From above results, the
In this letter, a 0402 sized CSZT embedded capacitor has been fabricated in an innovative manner. We have obtained capacitance of 406.1 pF, dielectric constant of 55.5, and dielectric loss of 0.015, at 1 MHz. Moreover, the CSZT embedded capacitor shows stable capacitance with varying applied voltage and C0G properties. The ESR and ESL values show superior values of 6.1 and 62.39 μH at 1 MHz, respectively. The leakage current density of the CSZT embedded capacitor as a function of applied voltage is 0.78 μA/cm2 at 3 V of applied voltage. From the above results, we can conclude that the proposed 0402 sized CSZT embedded capacitor can be used in practical applications. R EFERENCES [1] C. C. Wu et al., “The chemical and dielectric properties of epoxy/(Ba0.8 Sr0.2 )(Ti0.9 Zr0.1 )O3 composites for embedded capacitor application,” Eur. Polymer J., vol. 45, pp. 1442–1447, May 2009. [2] Y. S. Kimu et al., “The electrical characterization and relaxation behavior of Ag(Ta0.8 Nb0.2 )O3 ceramics,” Trans. Electr. Electron. Mater., vol. 15, no. 2, pp. 100–102, Apr. 2014. [3] H. H. Shin, S. W. Lee, and H. S. Jung, “Sintering and glass-added dielectric properties of Li2 O-B2 O3 -Al2 O3 -SiO2 (Ca0.7 Sr0.3 O)1.03 (Ti0.1 Zr0.9 )O2 for copper electrode,” Int. J. Appl. Ceram. Technol., vol. 10, no. 4, pp. 716–722, Aug. 2013. [4] A. Tombak et al., “Voltage-controlled RF filters employing thin-film barium-strontium-titanate tunable capacitors,” IEEE Trans. Microw. Theory Techn., vol. 51, no. 2, pp. 462–467, Feb. 2003. [5] S. Siami, C. Joubert, and C. Glaize, “High frequency model for power electronics capacitor,” IEEE Trans. Power Electron., vol. 16, no. 2, pp. 157–166, Mar. 2001. [6] J. H. Kim et al., “Characterization of discrete decoupling capacitors for high-speed digital systems,” in Proc. 54th Electron. Compon. Technol. Conf., vol. 1. Jun. 2004, pp. 259–265. [7] N. Lamrani et al., “Influence of strontium substitution on the dielectric properties of Ca(1−x) Srx Ti0.9 Zr0.1 O3 solid solutions,” Mater. Lett., vol. 65, no. 2, pp. 346–349, Jan. 2011. [8] J. Lu et al., “Low-loss tunable capacitors fabricated directly on gold bottom electrodes,” Appl. Phys. Lett., vol. 88, no. 11, pp. 112905-1–112905-3, Mar. 2006. [9] S. J. Kim et al., “PVD HfO2 for high-precision MIM capacitor applications,” IEEE Electron Device Lett., vol. 24, no. 6, pp. 387–389, Jun. 2003. [10] K. Y. Yiang et al., “Study of leakage mechanisms of the copper/Black DiamondTM damascene process,” Thin Solid Films, vols. 462–463, pp. 330–333, Sep. 2004. [11] P. Riess et al., “Electric field and temperature dependence of the stress induced leakage current: Fowler–Nordheim or Schottky emission?” J. Non-Cryst. Solids, vol. 245, pp. 48–53, Apr. 1999. [12] M. S. Jeon and D. K. Choi, “Influences of the [(Ba, Sr)TiO3 ]modified RuO2 interface on the dielectric constant and currentvoltage characteristics,” J. Vac. Sci. Technol. B, vol. 15, pp. 928–934, May 1997. [13] Y. L. Chiou, J. P. Gambino, and M. Mohammad, “Determination of the Fowler–Nordheim tunneling parameters from the Fowler–Nordheim plot,” Solid-State Electron., vol. 45, pp. 1787–1791, Oct. 2001. [14] H. K. Kim et al., “Dielectric strength of voidless BaTiO3 films with nano-scale grains fabricated by aerosol deposition,” J. Appl. Phys., vol. 115, pp. 014101-1–014101-6, Jan. 2014.
