IEEE ELECTRON DEVICE LETTERS, VOL. 36, NO. 9, SEPTEMBER 2015
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Observation of Degenerate One-Dimensional Subbands in Single n-Channel Junctionless Nanowire Transistors Liuhong Ma, Weihua Han, Hao Wang, Xiang Yang, and Fuhua Yang Abstract— We experimentally investigate one-dimensional electron transport in single n-channel junctionless nanowire transistor at low temperature. Current step increases with the gate voltage is clearly observed at the temperature of 6 K, attributed to the electron transport through one-dimensional subbands formed in the nanowire. The height of the first and the fourth steps is half of that of the second and the third steps, resulting from the twofold degeneracy of certain subbands. Index Terms— Junctionless nanowire transistor, current step, low temperatures, quantum confinement effect, degenerate subband levels.
I. I NTRODUCTION
R
APID downscaling of conventional silicon MOSFET devices faces many fundamental challenges, such as: excessive gate leakage current, exponentially increasing source to drain sub-threshold leakage current, gate stack reliability and channel mobility degradation from increasing perpendicular fields. In addition, it becomes exceedingly arduous to form abrupt p-n junctions between source/drain and channel as the gate length is decreased down to 10 nm or even less. Recent year, a unified heavily doped nanowire resistor, called “junctionless nanowire transistor (JNT)” [1], has captured great attentions as a promising candidate for the further continuation of Moore’s law because of the excellent gate control ability and simplified fabrication process [2], [3]. To ensure full depletion of carriers when the device is turned off, the channel of JNT must be thin and narrow enough. Theory shows the carrier confinement in a one-dimensional nanowire makes the conduction band split into several subbands. JNTs have shown much more remarkable quantum confinement effects than conventional devices [4]. Obvious conductance oscillations of nanowire transistors at low temperature have been reported in several publications, which are attributed to successive filling of individual subbands [5]–[7]. In this letter, single n-channel JNTs were fabricated on silicon-on-insulator (SOI) substrate. One-dimensional electron
Manuscript received May 15, 2015; revised June 16, 2015; accepted June 29, 2015. Date of publication July 1, 2015; date of current version August 21, 2015. This work was supported in part by the National Natural Science Foundation of China under Grant 61327813, Grant 61376096, and Grant 61404126, and in part by the National Basic Research Program of China under Grant 2010CB934104. The review of this letter was arranged by Editor X. Zhou. The authors are with the Engineering Research Center for Semiconductor Integration Technology, Institute of Semiconductors, Chinese Academic of Science, Beijing 100083, China (e-mail:
[email protected]). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2015.2451646
Fig. 1. (a) Top view SEM image of device after the gate formation. The gate length is 280 nm and the channel with the cross section of 18 × 30nm 2 . (b) Three dimensional schematics of JNT after Al pad formation.
quantum confinement effect is clearly observed at low temperature of 6 K. Interestingly, the twofold degeneracy of certain subbands is experimentally observed. II. D EVICE FABRICATION AND C HARACTERIZATION Single n-channel JNTs used in this work were fabricated on a [100]-oriented SOI wafer with top silicon has a uniform phosphorus concentration of 2 × 1018 cm−3 . The thickness of top silicon layer and buried oxide layer (BOX) are 55 nm and 145 nm, respectively. Electron beam lithography (EBL) and inductively coupled plasma (ICP) etching were used to make two pads and nanowire along [110] direction. The sample was oxidized in dry oxygen at 900° for 1 hour, resulting in the formation of silicon core with width of 18 nm and height of 30 nm. The thickness of SiO2 gate dielectric formed by thermal oxidation was about 22 nm. The polycrystalline silicon gate was patterned by EBL and ICP etching. Fig. 1(a) shows a top view SEM image of device with the gate length of 280 nm. It was followed by the evaporation of 20 nm Ti to form Ni/Si ohmic contact and 300 nm Al was used for final metallization via conventional optical lithography. The schematic structure of a JNT is shown in Fig. 1(b). For the low temperature electrical characterization, the single n-channel JNTs were measured in a vacuum chamber, which can be cooled down to 6 K with the help of Lakershore-340 temperature controller. III. R ESULTS AND D ISCUSSION Fig. 2(a) shows the drain current IDS as a function of the gate voltage VGS at the low temperature of 6 K. The applied source-drain voltage VDS ranged from 2 mV to 10 mV with a step of 2 mV. When VGS is increased above the threshold voltage, several step-like current oscillations are
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IEEE ELECTRON DEVICE LETTERS, VOL. 36, NO. 9, SEPTEMBER 2015
Fig. 3. Conductance and the number of subbands as a function of gate voltage for VDS = 10 mV at T = 6 K. Twofold degeneracy of subbands is observed. The insert shows the tendency of normalized transmission coefficients Tn /T2 versus the subband index.
to a new subbands populated by electrons in the confined channel [10]. The experimental subband energy spacing E related to the gate voltage spacing can be estimated by [11] π2 Cox VG . (1) 2m ∗ e Here Cox is the gate capacitance per unit area and estimated as 1.56 × 10−7 F/cm2 (≈22 nm gate oxide) and m* is the effective electron mass. Thus, we can convert the gate voltage spacing of 0.88 V, 1.18 V and 0.49 V between the current steps to the energy spacing of 4.96 meV, 6.65 meV and 2.76 meV, respectively. Fig. 3 illustrates the conductance characteristic with VDS = 10 mV at low temperature of 6 K. The interesting point is that the height of the first and fourth current step is about half of that of the second and third step. The ground state of subbands is a single state. Thus, the second and third subbands are twofold degenerate [12]. The number of subbands Nsubbands verses VGS is shown on the right side of the axis. The twofold degeneracy for subbands is included in the calculated Nsubbands. Here, we take an average of the height of those six subbands (two degenerate subbands are included) as the attribution of one subband. We can clearly see the increase of Nsubbands with the increasing gate voltage. The height of the second and the third conductance steps is twice that of the other two steps, which can be ascribed to the filling of twofold degenerate subbands. The classical quantum wire conductance GN , in which N is the number of one-dimensional subbands populated at the Femi energy, is simply given by Landauer formula [13] E =
Fig. 2. Drain current (a) and transconductance (b) characteristics of JNT measured at T = 6 K with the drain voltage ranging from 2 mV to 10 mV. Current steps and transconductance oscillations as a function of VGS are observed, due to the electron population of individual one-dimensional subbands.
clearly observed. Fig. 2(b) shows the curves of the transconductance Gm verses VGS (i.e., Gm = ∂ I D S /∂ VG S ). As can be seen, the Gm oscillations are independent of VDS within the range from 2 mV to 10 mV. The black arrows mark the fixed gate voltage positions for the Gm valleys for varying VDS . The marked sub-valley positions correspond to the gate voltages of 2.97 V, 3.85 V, 5.03 V and 5.52 V. The extracted gate voltage spacing VGS between adjacent transconductance peaks is 0.88 V, 1.18 V and 0.49 V, respectively. The observed step-like features in the drain current are in close agreement with one-dimensional transport, which manifests oscillatory quantum features in the transfer characteristics of nanowire transistors. Carrier confinement in a one-dimensional nanowire splits the energy bands into discrete subbands, which influents the electrical characteristics of the nanowire transistor [8]. ¯ In our device, the channel is confined in both [110] and [100] directions. The carriers are free to move only in the direction of [110] through discrete subbands. The subband energy levels are determined by the six equivalent valleys in the conduction band, which are anisotropic on the different directions. The six valleys are split into twofold degenerate valleys and fourfold degenerate valleys according to the effective mass [9]. As the gate voltage VGS is increased, the current step corresponds
GN =
N 2e2 Mn Tn . h
(2)
n=1
Here M is the degeneracy of energy level and Tn is the transmission coefficient for the nth subband. The insert of Fig. 3 shows the tendency of normalized transmission coefficients Tn /T2 versus the subband index. A noteworthy point is that
MA et al.: OBSERVATION OF DEGENERATE ONE-DIMENSIONAL SUBBANDS
the transmission coefficient of each subband is not exactly the same, reflecting the scattering for each subband is different in some ways. The decline of transmission coefficient at higher VGS can be ascribed to inter-subband scattering, which is enhanced with new subband that becomes populated [14]. However, the impact of inter-subband scattering is very weak in comparison with strong impurity scattering in the heavily doped channel at low temperature. As consequence, inerratic conductance steps can be still observed obviously although with very small conductance spacing. IV. C ONCLUSION In conclusion, single n-channel JNTs were fabricated on SOI substrate by the electron beam lithography, the anisotropic dry etching and the thermal oxidation. The one-dimensional quantum electron transport properities in single channel n-type JNT were electrically characterized at the low temperature of 6 K. Current steps as the function of gate voltage are clearly observed, due to the population of individal one-dimentional subbands for electrons in confined channel. The height of the second and third steps in the conductance curve is approximately twice that of the first and the fourth steps, origining from the twofold degeneracy in subband energy levels. ACKNOWLEDGMENT The authors acknowledge Professor Zhong-Chao Fan, Mr. Jan-Jun Tang, Mrs. Yan Li, and Mr. De-Song Wang for their supports in device fabrication.
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