OFF-State Degradation in Drain-Extended NMOS Transistors

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 10, OCTOBER 2007

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OFF-State

Degradation in Drain-Extended NMOS Transistors: Interface Damage and Correlation to Dielectric Breakdown Dhanoop Varghese, Student Member, IEEE, Haldun Kufluoglu, Student Member, IEEE, Vijay Reddy, Hisashi Shichijo, Dan Mosher, Member, IEEE, Srikanth Krishnan, Associate Member, IEEE, and Muhammad Ashraful Alam, Fellow, IEEE

Abstract—OFF-state degradation in drain-extended NMOS transistors is studied. Carefully designed experiments and wellcalibrated simulations show that hot carriers, which are generated by impact ionization of surface band-to-band tunneling current, are responsible for interface damage during OFF-state stress. Classical ON-state hot carrier degradation has historically been associated with broken ≡ Si–H bonds at the Si/SiO2 interface. In contrast, the OFF-state degradation in drain-extended devices is shown to be due to broken ≡ Si–O– bonds. The resultant degradation is universal, which enables a long-term extrapolation of device degradation at operating bias conditions based on shortterm stress data. Time evolution of degradation due to broken ≡ Si–O– bonds and the resultant universal behavior is explained by a bond-dispersion model. Finally, we show that, under OFF-state stress conditions, the interface damage that is measured by charge-pumping technique is correlated with dielectric breakdown time, as both of them are driven by broken ≡ Si–O– bonds. Index Terms—Bond-dispersion (B-D) model, drain-extended devices, gate dielectric breakdown, hot carrier degradation, interface damage, OFF-state degradation, Si–O bonds, universal degradation.

I. INTRODUCTION

T

HE DEVICE dimension and supply voltage for the core logic and memory transistors have been scaled down systematically over the last few decades. This, however, is not the case for input/output (IO) devices (e.g., LDMOS, DeMOS, etc. [1]–[3]) that interface ICs to the outside world and, therefore, must continue to operate at supply voltages higher than that of core transistors. Such high operating biases often lead to unique reliability issues which are different from the core transistors and which cannot be understood in terms of uncorrelated combinations of classical theories of NBTI, hot carrier injection (HCI), or time-dependent dielectric breakdown (TDDB) [4], [5]. This makes the lifetime estimations of IO transistors particularly difficult and sometimes overly conservative.

Manuscript received April 24, 2007; revised June 26, 2007. The review of this paper was arranged by Editor J. Suehle. D. Varghese, H. Kufluoglu, and M. A. Alam are with Purdue University, West Lafayette, IN 47907 USA (e-mail: [email protected]). V. Reddy, H. Shichijo, D. Mosher, and S. Krishnan are with the Texas Instruments Inc., Dallas, TX 75243 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2007.904587

Hot carrier degradation (HCI) has been a major issue for core transistors since the early 1980s, when the device dimensions started shrinking while the supply voltage (VDD ) remained at 5 V [6]. However, HCI is a voltage-driven (but not a field driven) phenomenon; therefore, by mid 1990s, it ceased being a dominant degradation mode as VDD was scaled down from 5 V. Classical hot carrier is an extensively studied topic, with the following well-known characteristics: 1) Hot carriers that are responsible for the damage are due to impact ionization (II) of source current, and the degradation is found to maximize at peak substrate current (IB ) stress conditions (VG ≈ VD /2) corresponding to peak hot carrier generation [7]–[11]. 2) Interface damage during the stress is known to have a power law behavior (∆NIT = Atn ), with the time exponent n close to 0.5 [11]–[14]. 3) A fraction of damage that is generated during classical hot carrier stress is found to recover on the removal of the stress conditions [13], [14]. 4) The degradation is believed to be due to broken ≡ Si–H bonds at the Si/SiO2 interface, as confirmed by the isotope effect observed during the stress [11], [15]. 5) The classical hot carrier degradation shows no correlation with the dielectric breakdown (TDDB, [16]–[18]), presumably because TDDB results from broken ≡ Si–O– bonds. However, some recent reports show that oxide degradation can indeed occur during hot carrier stress conditions [19], [20]. In this paper (expanded version of the study in [21]), we study the reliability of drain-extended NMOS (DeNMOS) transistors subjected to OFF-state hot carrier stress (VG = 0 V, VD > 5 V), and we find that the characteristics of this degradation are distinct and unique compared to classical ON-state HCI. It has been hypothesized that an interface damage during OFF-state operation is due to generation of hot carriers by the high electric field localized near the drain end, and their subsequent injection into the gate oxide. However, unlike the classical ON-state hot carrier degradation where hot carriers are generated by the II of source current, the source current that flows in OFF-state is just the subthreshold leakage and might not be a significant source for hot carriers. Second, the interface trap generation during OFF-state degradation is found to have high time exponents (n ≈ 0.7–0.8), which are higher compared to that obtained during classical ON-state studies (n ≈ 0.5). In addition, unlike the classical ON-state hot carrier stress, the interface traps that are generated during the OFF-state stress do not recover on the removal of the stress

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Fig. 1. Device structure of DeNMOS transistor used in the study. Current components present during OFF-state bias conditions [namely, (a) subthreshold leakage ISD , (b) substrate leakage IB,leak , (c) gate edge direct tunneling IEDT , and (d) surface BTBT] can impact ionize at the peak electric field region and lead to generation of hot carriers (step 2). The hot carriers get injected into the gate oxide and create damage (shaded region).

conditions. Finally and most surprisingly, the DeNMOS transistors undergo gate dielectric breakdown during the OFF-state stress, and the interface damage during the OFF-state stress is found to correlate well with the breakdown time. Although the subthreshold leakage might not be a significant source of hot carriers, various other current components can be present during OFF-state bias conditions that can lead to hot carrier generation. It is important to identify these components and isolate the dominant current component responsible for hot carrier generation. By properly designed experiments and well-calibrated MEDICI [22] and Monte-Carlo based Simplex Monte Carlo (SMC) simulations [23], we demonstrate that the II of the surface band-to-band tunneling (BTBT) current generates hot carriers during the OFF-state stress in DeNMOS devices. The differences between OFF-state and classical ONstate degradation characteristics are explained by the fact that the interface damage during OFF-state stress is due to broken ≡ Si–O– bonds [14], [24], unlike the broken ≡ Si–H bonds for ON -state stress. The resultant OFF-state degradation is universal, or in other words, individual degradation curve at each drain bias, when scaled properly, forms a single degradation function. The time evolution of broken ≡ Si–O– bonds and the universal behavior are explained in terms of bond-dispersion (B-D) model [25], which is used to obtain a long-term degradation at lower operating biases from short-term stress data. Finally, we show that the correlation of interface damage with the device breakdown during OFF-state stress opens the possibility of replacing the time-consuming gate dielectric breakdown tests with simple charge-pumping (CP) measurements. This paper provides an illustrative example of nonclassical but predictive degradation in IO transistors and takes us a step closer to generalized degradation model for IO transistors, encompassing both hot carrier degradation and dielectric breakdown. II. DEGRADATION MECHANISM The device structure of the DeNMOS device used in this paper is shown in Fig. 1. The process conditions are similar to those discussed in [2]. When biased in OFF-state conditions (VG = 0 V, VD > 5 V), various current components can be

Fig. 2. (a) Multiterminal configurations to identify the dominant current component during OFF-state bias conditions. Active components are denoted by arrows, and inactive components are crossed out. (b) Drain–current measurements for multiterminal configurations identify IBTBT as the dominant current component.

present in the device, namely, subthreshold leakage (ISD ), substrate leakage (IB,leak ), gate edge direct tunneling (IEDT ), and surface BTBT (IBTBT ). Each of these components can lead to II (rate α) and subsequent generation of hot carriers. A current measurement at the drain terminal (ID ) gives the sum of these components along with the generated hot carriers, if any (see Fig. 1). In order to identify the dominant current component responsible for hot carrier generation, one should be able to control each of these components independently, which is achieved using a multiterminal measurement. The gate edge tunneling current (IEDT ) is measured separately at the gate terminal, and since IEDT is orders of magnitude smaller than the drain–current ID (data not shown), we neglect it during further analysis. In a standard four-terminal (4T) measurement [see Fig. 2(a)], all current components are active so that ID,4T = [ISD + IB,leak + IBTBT ](1 + α). One way to eliminate the subthreshold leakage current is to float the source terminal, and this is called the three-terminal measurement (3T; ID,3T = [IB,leak + IBTBT ](1 + α)). However, no significant reduction in drain–current is observed during the 3T measurement [see Fig. 2(b)], which implies that ISD cannot be the dominant current component. To study the impact of the remaining components, we note that IB,leak depends on the drain-to-substrate potential VDB , while IBTBT depends on the

VARGHESE et al.: OFF-STATE DEGRADATION IN DeNMOS TRANSISTORS

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Fig. 3. Drain–current measurement at various temperatures. Positive temperature dependence and good match with MEDICI simulation indicate that hot carrier component (αIBTBT ) should be small compared to IBTBT (α 1). αIBTBT obtained from SMC simulation is also plotted and is found to be orders of magnitude less than the net drain–current.

drain-to-gate potential VDG . Hence, by splitting the drain bias between the drain and gate terminals such that VDG remains constant, we can suppress IB,leak while keeping IBTBT constant. This voltage splitting technique (3T + VS; ID,3T+VS = IBTBT (1 + α)) [26] also showed no significant reduction in the drain–current, which singles out IBTBT as the dominant current component in the OFF-state. As an additional proof, we carried out a two-terminal measurement with the gate and source terminal floating (2T; ID,2T = IB,leak (1 + α)), and we found the corresponding drain–current to be orders of magnitude lower than that measured in other configurations. Note that since the total drain–current is unaffected by floating of the source terminal, but depends only on the drain-to-gate potential, the resultant degradation is expected to be independent of the device channel length. Although we have identified IBTBT as the dominant source of hot carriers, the relative contribution of IBTBT and hot carriers (αIBTBT ) toward the total drain–current measurement [IBTBT (1 + α)] is still unknown. Their relative contributions can be determined by studying the temperature dependence of the drain–current: in an indirect bandgap material like silicon, BTBT, which involves tunneling of electrons from valence to conduction band, is a phonon-assisted process and is expected to have a positive temperature dependence. On the other hand, the II is a process competing with phonon scattering, and it is expected to have much weaker or even negative temperature dependence [27]. The drain–current measurement at varying temperatures is shown in Fig. 3, and a clear positive dependence implies that hot carriers generated through II, if any, should be much less compared to IBTBT . This observation is also supported by the well-calibrated MEDICI and SMC simulations. The BTBT current that is obtained from the MEDICI simulation is found to be in excellent match with the measured drain–current for various temperatures (see Fig. 3). In addition, the hot carrier component (αIBTBT ) that is obtained from the SMC simulations is found to be orders of magnitude less than the drain–current, emphasizing the fact that, even though II is present, it is a rather weak process (α 1). The simulations based on MEDICI and SMC offer further insight into the hot carrier generation mechanism. The 2-D

Fig. 4. (a) Two-dimensional electric field and (b) band-to-band generation profiles during OFF-state bias condition. Both electric field and band-to-band generation peak at the Si/SiO2 interface, close to the gate edge.

Fig. 5. Conduction and valence band profiles close to Si/SiO2 interface during OFF -state stress. BTBT and subsequent II at the peak electric field region are shown schematically.

electric field profile in a DeNMOS transistor (biased in OFFstate) is shown in Fig. 4(a). It can be seen that the electric field peaks at the Si/SiO2 surface, close to the gate edge. The BTBT occurs at this peak electric field region, and it is confirmed by the 2-D band-to-band generation profile that is obtained from MEDICI [see Fig. 4(b)]. To show how II and subsequent generation of hot carrier occur, we plot the 1-D conduction and valence band profile close to the Si/SiO2 interface obtained from MEDICI (see Fig. 5). The corresponding electric field

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Fig. 7. One-dimensional hot electron and hot hole profiles obtained from SMC simulation (along the dotted lines in Fig. 6). Interface trap profile obtained from the CP measurement is also plotted. Peak interface damage occurs close to the gate edge and correlates well with the location of spatial overlap of hot carriers.

Fig. 6. (a) Two-dimensional hot hole and (b) hot electron profiles obtained from SMC simulation. Hot carriers close to the Si/SO2 interface get injected into the gate oxide and create damage.

peaks at the gate edge and leads to BTBT, as shown schematically in Fig. 5. The electrons thus generated gain energy from the electric field and lead to the generation of electron-hole pairs through II. The holes generated by II can further gain energy from the field and get injected into the oxide. The 2-D hot carrier profile that is obtained from the SMC simulation, as shown in Fig. 6, is in good agreement with the above picture. It can be seen that the hot carrier densities peak at the Si/SiO2 interface and close to the gate edge, as expected. Finally, in order to clearly establish the role of hot carrier in interface damage, we performed a lateral profiling of the interface traps generated during the stress using a CP technique [28]. The threshold and flat band voltage profiles required for the lateral profiling were obtained from the MEDICI simulations. The interface trap profile obtained for various stress drain biases and the corresponding interfacial hot carrier densities (along the dotted lines in Fig. 6) are plotted in Fig. 7. Good spatial correlation of peak damage region with hot carrier profiles unequivocally establishes the fact that the interface damage is caused by hot carriers. III. NATURE OF DAMAGE AND ITS TIME EVOLUTION Now that we have established that the interface damage generation during OFF-state stress is due to hot carriers generated

by II of surface BTBT component, let us focus on the nature of the damage and its time evolution. We begin with a background discussion illustrating the characteristic differences between HCI-broken Si–H and Si–O bonds. We then show that the OFFstate degradation in DeNMOS transistors is associated with broken ≡ Si–O bonds and that the corresponding time evolution exhibits universal behavior. Interface trap generation during classical ON-state hot carrier stress is believed to be due to broken ≡ Si–H bonds, as suggested by the isotope effect observed during the stress. The 2-D reaction-diffusion (R-D) model [13] offers a plausible explanation for the n ≈ 0.5 time exponent of classical HCI based on a two-step process, involving breaking of ≡ Si–H into ≡ Si– dangling bond and H species (reaction step), followed by the 2-D diffusion of H species. Since the breaking of ≡ Si–H bond is reversible, a fraction of the H species can diffuse back and anneal the ≡ Si– dangling bonds on the removal of the stress conditions. The 2-D R-D model can successfully explain both the generation and recovery phases of the classical hot carrier degradation [13]. A significant change to the above classical hot carrier picture came from the study of positive substrate bias on PMOS devices subjected to NBTI stress [24]. Application of positive substrate bias led to the generation of hot holes at the Si/SiO2 interface, apart from the cold holes present during the NBTI stress conditions, and resulted in accelerated interface trap generation. The additional interface traps that are generated in the presence of hot holes [i.e., ∆2 NIT = ∆NIT (VB > 0) − ∆NIT (VB = 0)] were found to have a higher time exponent (n ≈ 0.5), which correlated well with the time evolution of stress-induced leakage current (SILC) and showed zero recovery on the removal of the stress. SILC, which is a measure of increase in gate leakage during the stress, is believed to be due to the trap-assisted tunneling of electrons between the gate and the substrate [29]. The traps are generated due to broken ≡ Si–O– bonds in the bulk of the oxide, and the good correlation between the SILC and additional interface traps implies that both have the same physical origin. Indeed, it is possible that a fraction of the ≡ Si–O– bonds close to the Si/SiO2 interface get broken during the stress, and the traps thus generated respond to the CP pulse


Fig. 8. (a) Time evolution of interface damage for various stress drain biases and temperatures. (b) Time evolution of interface damage during consecutive stress and relaxation phases. (c) Integrated hot hole and electron densities underneath the gate overlap region for various drain biases (see Fig. 7). Damage generation rates at various stress biases are also plotted and found to correlate well with the integrated hot hole density.

and are measured as interface traps. The high time exponent and lack of recovery also points to the fact that the additional damage should be due to broken ≡ Si–O– bonds. A generalized hot carrier degradation model, even at ON-state, should therefore account for both broken ≡ Si–H and ≡ Si–O– bonds. To distinguish between damages due to these two bond types, we note that the 2-D R-D model limits the power law time exponent of degradation due to broken ≡ Si–H bonds to a maximum value of 0.5, and further suggests that a fraction of the broken bonds recover on the removal of the stress conditions. Time evolution of the interface traps during OFF-state degradation for various drain bias and temperature is plotted in Fig. 8(a). It can be seen that the degradation shows a much higher time exponent (0.7–0.8) than the upper limit of 0.5 set for broken ≡ Si–H bonds. In order to check for the presence of recovery, devices were subjected to relaxation phase following the OFF-state stress, in which all device terminals were grounded. The interface damage during consecutive stress and relaxation phases is shown in Fig. 8(b), which does not show any significant recovery during the relaxation phase. The high time exponent during the stress phase and the lack of recovery during the relaxation phase point to the fact that the dominant contribution to the interface damage during OFF-state stress should be from broken ≡ Si–O– bonds. The third clue to this puzzle comes from the correlation of the interface damage with hot hole density. It is shown in [24] that ≡ Si–O– bonds are preferentially broken in the presence of hot holes. To check this, we integrated the hot hole

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and electron density underneath the gate, corresponding to the interface damage region obtained from lateral profiling experiments. The integrated hot hole and electron densities along with the interface trap generation rate for various drain biases are plotted in Fig. 8(c). The generation rate for interface traps is inversely proportional to the time required for the interface damage to reach an arbitrarily specified level. A good correlation between the damage rate and the hot hole density also confirms the fact that the dominant contribution is due to broken ≡ Si–O– bonds. Unlike the damage due to broken ≡ Si–H bonds, there exists no formal theory that explains the time evolution of damage due to broken ≡ Si–O– bonds. The time evolution of the interface damage during the OFF-state stress at various drain biases is shown in Fig. 9(a). It can be seen that the degradation curves show faster degradation rates (n ≈ 0.8) at short stress times and low stress biases, which gradually saturate (n ≈ 0.2) at longer stress times or at higher biases. The most striking feature about these degradation curves is the fact that they exhibit a universal behavior, which is demonstrated by the fact that individual degradation profiles can be scaled along the time axis to form a single degradation curve! This implies that the degradation at each stress drain bias is following the universal curve, albeit at different rates determined by the stress bias. To prove this point independently, a long time measurement was carried out at a stress drain bias of 6.0 V [see Fig. 9(b)], and the measured degradation follows the predicted universal curve quite closely. IV. THEORY OF UNIVERSAL DEGRADATION The universality of OFF-state degradation and its saturating behavior set constraints to any theoretical model put forward to explain the degradation mechanism. Note that the universal degradation curve exhibits a fast degradation phase at early time (n ≈ 0.8) and enters a gradually saturating phase at later time (n ≈ 0.2). To understand the underlying physical mechanism, we start with the phenomenological rate equations for interface trap generation. Unlike the broken ≡ Si–H bonds, the rate equation for broken ≡ Si–O– bonds has only the forward reaction term, and no reverse reaction term, as broken ≡ Si–O– bonds do not recover on the removal of the stress conditions. The corresponding rate equation is dNIT (t) = k(p) (N0 − NIT (t)) dt

(1)

where N0 is the initial number of ≡ Si–O– bonds, NIT is the number of broken bonds, and k is the forward reaction rate which depends on the hot hole density p. Note that a linear dependence of reaction rate on hot hole density is observed in Fig. 8(c). By solving (1), we find that (2) NIT (t) = N0 1 − e−k(p)t . Unlike the universal degradation curve, (2) exhibits a hard saturating behavior. Hence, the above simple framework needs

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Fig. 9. (a) Time evolution of interface damage during various stress drain biases. Individual degradation profiles, when scaled along the time axis, form part of a universal degradation curve! (b) Long-term degradation measured at a single drain bias and obtained by scaling back the universal degradation curve. Measured degradation follows the predicted universal degradation curve closely.

to be modified, and we note that, in a disordered medium like SiO2 , the bond energies are not discrete as assumed by (1), but have a finite distribution [25]. Therefore, both the precursor density and reaction rate become functions of bond energy, and the net interface trap density is obtained by summing up the contributions over the entire energy distribution. The energy dependence of precursor density and reaction rate is assumed to be similar to that used in the B-D model [25]. g(E) =

e−(E−EAV )/σ N0 , σ 1+e−(E−EAV )/σ 2

for |E −EAV | < mσ (3)

k(E, p) =k0 (p)e−(E−EAV )/kT

(4)

EAV +mσ

NIT (t) =

g(E) 1 − e−k(E,p)t dE.

(5)

EAV −mσ

The above integration is done numerically (σ = 0.125 eV, m = 3.38), and Fig. 9(a) shows that (5) interprets the universal degradation curve several orders of magnitude in time. Apart from the B-D model, we also considered unsuccessfully, alternate theories that have been proposed to explain the saturating behavior of other HCI degradation curves. For example, Cham et al. [30] attributed the saturating behavior of

Fig. 10. (a) ON-state hot-carrier current measured at regular intervals during OFF -state stress. The ON -state hot-carrier current and, hence, the internal electric field show no significant reduction with stress time. (b) Lateral profile of interface traps at various stress times obtained using the CP technique. No significant shift in the damage region with stress time is observed, as suggested in [31] and [32].

classical hot carrier degradation to the reduction in stress levels with degradation time. In accordance with this model, interface charges due to the damage reduce the peak electric field, possibly leading to a reduction in II rate and subsequent generation of hot carriers and, thereby, reducing the reaction rate k(p). A direct measurement of the hot carrier current (αIBTBT ) during OFF-state stress is difficult, as it can only be measured along with the BTBT current at the drain terminal. Hence, we used an indirect method, which involves interrupting the stress briefly and measuring the ON-state hot carrier current at the substrate terminal. The measurement result is shown in Fig. 10(a), and only a slight reduction in ON-state hot carrier current with stress time is observed. This is insufficient to explain the large reduction in degradation rates, and therefore, we conclude that the reduction in electric field does not play a significant role in determining the time evolution of the interface damage during OFF-state stress.1 Another model to explain the soft saturation of degradation is the spatial variation of degradation rates, either due to a 1 The ON -state hot carrier current is due to II of I SD and might be occurring at a location different from the II of IBTBT during OFF-state stress. Hence, α (ON-state) need not be a true monitor of α (OFF-state), but its mild reduction suggests that local electric field has not changed significantly during the OFFstate stress. Reduction in IBTBT during OFF-state stress was also monitored (data not shown) and was found to be less than 30% of the t = 0 value, also in support of the above conclusion.


spatial variation in stress electric field [31] or due to shift in peak electric field with stress time [32]. Time evolution of interface traps for such scenarios is given by (2), with the damage at the peak degradation region saturating at an earlier time, and progressively followed by regions with lower degradation rates. Hence, the degradation region appears to grow laterally with stress time, and the net damage is obtained by summing up contributions over the entire degradation length. To check whether such a lateral growth of degradation region is observed during OFF-state degradation, we extracted the spatial profiles of the interface traps generated at various stress times using the CP technique and are plotted in Fig. 10(b). The degradation is found to occur close to the gate edge, and no spatial growth of damage profile with stress time is observed. This ruled out the possibility of spatial dispersion of degradation and led us to the energy dispersion model that was found to be in good agreement with the experimental observations.

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Fig. 11. Voltage acceleration for inverse of scaling factor (1/S) and integrated hot hole density [see Fig. 8(c)] underneath the gate overlap. Device lifetime is inversely proportional to scaling factor [see Fig. 9(b)] and, hence, is expected to have similar voltage dependence as 1/S.

V. UNIVERSAL DEGRADATION AND LIFETIME PROJECTION Irrespective of the underlying physical mechanism, the universality of degradation by itself is a powerful experimental tool, which enables extrapolation of device degradation to lower operating biases from the high stress conditions. Consider Fig. 9(a) where the device degradation curves at individual stress biases are scaled laterally to obtain the universal degradation curve. By knowing the shape of the universal degradation curve and the scaling factors, one can scale back the universal curve and obtain long-time degradation data at lower stress biases. In addition, since the scaling factors, which are used to obtain the universal degradation curve, are proportional to the reaction rate at each bias, the corresponding device lifetime (defined as the time it takes to reach a certain degradation level) can be shown to be inversely proportional to the scaling factors [see Fig. 9(b)]. Therefore, instead of a time-consuming measurement of the device lifetime or an erroneous lifetime extrapolation based on a short-term test, one can use short-term degradation data to obtain the scaling factors and, thereby, obtain the relative device lifetimes. Fig. 11 plots the inverse of the scaling factors (1/S) against stress drain bias, and the voltage dependence is expected to be the same as that of the actual device lifetime. Finally, since the reaction rate is found to linearly depend on the simulated hot hole density [see Fig. 8(c)], the hot hole density plotted against the stress drain bias also shows similar voltage dependence. This enables MEDICI and SMC as predictive simulation tools in the hands of a device designer for making reliability projections. VI. CORRELATION WITH DIELECTRIC BREAKDOWN In the previous sections, we showed that the interface damage during OFF-state stress is due to broken ≡ Si–O– bonds. The bonds can be broken both at the interface and (potentially) in the bulk. The traps that are generated due to broken ≡ Si–O– bonds in the bulk can form a percolating path between the gate and the substrate, leading to device breakdown [17]. As both

Fig. 12. Weibull statistics of breakdown times during OFF-state stress. Breakdown times at individual drain biases are combined (toward an arbitrary drain bias) using scaling factors from CP measurement. Corresponding Weibull slopes were obtained using maximum likelihood estimation (MLE) and least square fitting (LSQ).

the interface and bulk traps during OFF-state stress are due to the same underlying physical mechanism, their generation rates are expected to be similar. If this assumption holds true, one can use the scaling factors obtained from the CP measurements to obtain the voltage dependence of mean device breakdown times (TBD ) during OFF-state stress. If confirmed, this will be a significant result because conventional measurement of TBD requires a relatively large number of samples (TBD is Weibulldistributed [17]) and long stress times particularly at lower stress biases. In contrast to this, the CP scaling factors can be obtained using smaller number of samples and based on shorter duration tests. In order to check this hypothesis, we performed device breakdown measurements under OFF-state conditions, with the stress interrupted at regular intervals to monitor the interface damage. The breakdown times obtained from the measurements were found to be Weibull-distributed (see Fig. 12), with Weibull slope β ≈ 1.7. The breakdown times for the samples at each stress bias and the corresponding mean value are plotted in Fig. 13. The inverse of scaling factors (1/S) obtained from the CP measurements is also plotted, and an excellent match between the scaling factors and mean

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R EFERENCES

Fig. 13. Voltage dependence of device breakdown times and scaling factors from CP measurement for various stress drain biases. A good correlation between the breakdown time and scaling factors points to the same underlying physical mechanism for both interface and bulk damage.

breakdown time is observed! This proves the fact that the dielectric breakdown is indeed correlated to the interface damage during OFF-state stress conditions and independently confirms the fact that CP is indeed measuring the broken ≡ Si–O– bonds at the interface. Finally, this opens the possibility of replacing conventional device breakdown tests at OFF-state stress conditions with a simpler CP technique, thereby reducing the measurement costs in terms of time, instrumentation, and sample count. VII. CONCLUSION We have studied the OFF-state degradation in DeNMOS devices. Through properly designed experiments and wellcalibrated MEDICI and SMC simulations, we show that hot carriers generated through II of surface BTBT current are responsible for interface damage under OFF-state conditions. Unlike the classical ON-state hot carrier, the interface damage during OFF-state stress is primarily due to broken ≡ Si–O– bonds. The resultant degradation is universal, which is explained by a B-D model. The universality of OFF-state degradation enables lifetime extrapolation at operating biases, based on shorter duration tests. Finally, we show that the dielectric breakdown under OFF-state stress correlates well with the scaling factors obtained from CP measurements, as they both are driven by broken ≡ Si–O– bonds. This correlation opens up the possibility of replacing the time-consuming device breakdown studies at OFF-state stress conditions with simple CP measurements, and this takes us a step closer to the generalized degradation model encompassing the hot carrier degradation and dielectric breakdown. ACKNOWLEDGMENT The authors would like to thank the Texas Instruments Inc. for supporting the research, S. Mahapatra (IIT Bombay) for useful discussions, J. Bude for providing the SMC simulator, Network of Computational Nanotechnology at Purdue for providing the computational facilities, and Birck Nanotechnology Center at Purdue for the characterization facilities.

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Dhanoop Varghese (S’06) received the B.Tech. degree in electronics and communication engineering from the REC Calicut, India, in 2002 and the M.Tech. degree in electrical engineering from the Indian Institute of Technology, Bombay, India, in 2005. Since 2005, he has been working toward the Ph.D. degree at Purdue University, West Lafayette, IN. His current research interests are in the field of semiconductor device physics, simulation, modeling, and characterization. He has worked on bias temperature and hot carrier reliability issues in MOSFETs and high-κ gate dielectrics.

Haldun Kufluoglu (S’04) received the B.S. and M.S. degrees in electrical engineering from Purdue University, West Lafayette, IN, in 2001 and 2003, respectively. He is currently working toward the Ph.D. degree at the same university. His research interests include MOSFET reliability, and experimental characterization and modeling of semiconductor devices. Particularly, his Ph.D. research involves measurements and theoretical modeling of MOSFET degradation mechanisms such as NBTI, hot carrier injection, and time-dependent dielectric breakdown, and their implications on VLSI design. He also participates in OFF-state transistor reliability assessment. Previously, he worked on MEMS that was interfaced with live neurons for biological sensor applications. In 2006, he held a summer internship with Intel Corporation, Logic Technology Development Front End Quality & Reliability, Hillsboro, OR, working on experimental 65-nm NBTI reliability and modeling.

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Vijay Reddy received the Ph.D. degree in electrical engineering from the University of Texas, Austin, in 1994. Since then, he has been with Texas Instruments (TI) Inc., Dallas, and has worked on several topics concerning transistor and circuit reliability and product qualification methodologies. He is currently a Senior Member of Technical Staff with TI. He is the holder of nine patents and has several pending along with more than 20 publications, including at such conferences as IRPS, IEDM, and EOS/ESD Symposium. Dr. Reddy has served on the IRPS and IEDM program committees and has presented invited tutorials on CMOS Reliability at IRPS (during 2002–2004) and ICMTS (in 2006). He received the 2002 IRPS Outstanding Paper Award for his work on the circuit impact of NBTI and was a corecipient of the 2004 IRPS Outstanding Paper Award and the 2002 ESD/EOS Symposium Best Paper/Best Presentation Awards.

Hisashi (Sam) Shichijo received the B.S. degree in electronic engineering from the University of Tokyo, Tokyo, Japan, in 1976, and the M.S. and Ph.D. degrees in electrical engineering from the University of Illinois at Urbana–Champaign, in 1978 and 1980, respectively. Since 1980, he has been with Texas Instruments (TI) Inc., Dallas, as a member of the Technical Staff. He has since been involved in various projects including MOS SRAM process technology, submicrometer MOS devices, device scaling studies, SOI polysilicon FETs for DRAMs and 3-D ICs, trench transistor DRAM cell for 4-Mb DRAM, device and circuit design for 64-Mb DRAM, and 1-Gb DRAM process development. He was with the Central Research Laboratories for three years working on GaAs MESFET high-speed SRAMs and memory/logic integration, and GaAs-on-silicon devices before returning to Semiconductor Process and Design Center (Silicon R&D center) in 1989. He is currently a TI Fellow with TI’s Silicon Technology Development Group and has been involved in analog and RF integration in TI’s 180-nm, 130-nm, 90-nm, 65-nm, and 45-nm CMOS technologies in the last nine years. Dr. Shichijo served as the conference Chairman at the 1992 Device Research Conference.

Dan Mosher (S’75–M’79) received the B.S. degree in physics from Beloit College, Beloit, WI, in 1969, the M.S. degree from The University of Iowa, in 1976, and the Ph.D. degree in engineering from the University of Nebraska–Lincoln, Lincoln, in 1981. He joined Texas Instruments (TI) Inc., Dallas, in 1979, in the Central Research Laboratories to work on the TI solar energy system. He later moved to integrated circuit process integration positions to develop technologies for integrating power (high voltage or high current) transistors with regular CMOS logic, using process and device modeling tools to design the transistors and processes to satisfy unique customer requirements. These have included thruwafer bipolar, double-diffused NMOS, lateral RESURF, and drain-extended CMOS. He is currently a TI Senior Member of the Technical Staff with the Silicon Technology Development Division, TI.

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Srikanth Krishnan (S’86–M’87–A’92) received the B.Tech. degree in electrical engineering from the Indian Institute of Technology, Madras, India, in 1985, the M.S. and Ph.D. degrees in engineering science from The Pennsylvania State University, in 1988 and 1992, respectively, and the MBA from Southern Methodist University, University Park, TX. He later joined with the Plasma Etch Group, Semiconductor Process and Design Center, Texas Instruments Inc., Dallas, to work on plasma damage effects on transistor performance. In 1998, he joined the Reliability Group within Texas Instruments Inc. and, subsequently, led the 130-nm component reliability effort. He is currently the Device Reliability Manager with the Texas Instruments Inc., who is responsible for component reliability of CMOS technology nodes. During his 15-year career with the Texas Instruments Inc., he has authored 30 papers (6 invited), 20 patents, and 1 trade secret. Dr. Krishnan has served on the technical program committee for IRPS since 1999. He has been appointed to the Management Committee of IRPS since 2003. He served on the program committee of Plasma Process-Induced Damage Symposium (P2ID) and was the Vice-Chair and Chairman for the (P2ID) from 2003 to 2004.


Muhammad Ashraful Alam (M’96–SM’01–F’06) received the B.S.E.E. degree in electrical engineering from Bangladesh University of Engineering and Technology, Dhaka, in 1988, the M.S. degree in electrical engineering from Clarkson University, Potsdam, NY, in 1991, and the Ph.D. degree in electrical engineering from Purdue University, Lafayette, IN, in 1994. From 1995 to 2001, he was with the Silicon ULSI Research Department, Bell Laboratories, Lucent Technologies, Murray Hill, NJ, as a member of Technical Staff. From 2001 to 2003, he was a Distinguished Member of Technical Staff and the Technical Manager of the IC Reliability Group, Agere Systems, Murray Hill. He joined Purdue University in 2004, where he is currently a Professor of electrical and computer engineering. He has published over 75 papers in international journals. His current research and teaching focus on the physics, simulation, characterization, and technology of classical and novel semiconductor devices. His current research interests include the theory of oxide reliability, transport in nanocomposite thin-film transistors, and nanobio sensors. Dr. Alam received the Outstanding Paper Award in 2001 and the Best Paper Award in the International Reliability Physics Symposium in 2003 for his work on gate oxide reliability. He also received the IEEE Kiyo Tomiyasu Award for his contributions to device technology for communication systems. He has presented many invited and contributed talks in international conferences.