On a Comparative Study of Digital Redesign Methods

Proceedings of the American Control Conference Chicago, Illinois• June 2000

On a Comparative Study of Digital Redesign Methods C.A. R a b b a t h l'e a n d N. Hori 3 1 D e p a r t m e n t of M e c h a n i c a l E n g i n e e r i n g , M c G i l l University, M o n t r e a l , P Q , C a n a d a H 3 A 2 K 6 2 O P A L - R T T e c h n o l o g i e s Inc., M o n t r e a l , P Q , C a n a d a H 3 K 1G6

e-mail: [email protected] 3 I n s t i t u t e of E n g i n e e r i n g M e c h a n i c s , U n i v e r s i t y o f T s u k u b a , 1-1-1 T e n n o u - d a i , T s u k u b a , J a p a n

e-mail: hori@kz,tsukuba.ac.jp system rather than considering the controller blocks individually. Among the modern methods subscribing to this philosophy, which are named global digital redesign techniques, the so-called optimal digital redesign technique, introduced in [3], has been shown superior to the conventional methods. However, the optimal digital redesign approach suffers from one main problem: the complexity of the continuous-time controllers can be increased in the process, even after order reduction. An increase in controller complexity is not appealing for practicing engineers for reasons of increased burden on the processor in real-tirne [4], [5], more pronounced finite wordlength effects [6], and higher costs. For instance, the fastest sampling rate at which realtime simulations can be performed on a given target processor, whether it be a microprocessor or a digital signal processor, decreases with an increase in the order of the controller transfer functions due to longer computation times associated with the control law [7]. The complexity issue was solved in [8] with the so-called reduced-order plant input mapping technique, which is a global digital redesign method that enables the designer to constrain the order of the discrete-time controller blocks while achieving a satisfactory closed-loop performance.

Abstract

This brief paper compares the performances achieved with the conventional digital redesign techniques with those obtained with the modern global digital redesign methods such as the plant input mapping methods and the optimal digital redesign approach. The study based on a benchmark control system reveals that the reduced-order plant input mapping method, and not the optimal approach, offers what practicing control engineers are really looking for: simple controllers having a superior behavior in face of finite wordlength effects and over a relatively large band of sampling frequencies.

1 Introduction The digital redesign of a well-designed continuous-time control system has been widely used in industry and proven successful for several control strategies. Traditionally, the digital redesign has been accomplished in a local manner; that is, each controller block is discretized using any of the conventionaJ discretizations [1] and is implemented at the same location in the closed-loop as that of the continuous-time controller. However, the main disadvantage of a local approach is that the resulting sampled-data control system usually requires relatively fast sampling frequencies for preserving closed-loop stability and achieving a close performance to that of the continuous-time control system [1]. This fact renders the design process an iterative one where the designer must be extra careful in the selection of a sampling rate in order to avoid highly oscillatory and unstable responses.

This paper provides qualitative and quantitative comparisons of the performances achieved with the conventional digital redesign schemes, the modern plant input mapping techniques, which are explained in [8], [9], and [10], and the optimal digital redesign method. The control system that serves for the benchmarking of the digital redesign techniques, the performance evaluation criteria and the simulation results are described in Section 2. The conclusions follow in Section 3. The figures and tables can be found at the end of the paper.

As pointed out in [2], intuition suggests that the better digital redesign approach would be to perform an approximation to the closed-loop continuous-time control 0-7803-5519-9/00 $10.00 © 2000 AACC

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a complement to the conventional step response analysis. The norms can serve as criteria in the selection of a sampling period at which to perform the digital redesign process. In general, a digital redesign method resulting in the smallest error signal norms among the digital redesign methods, for a given T, would be the preferred choice. In Tables 3 and 4, for T = 0.4 , the norms and index are not calculated for the Tustin's and MPZ methods since they result in unstable closed-loop systems. For T = 0.1, the R O T P I M method offers the worst performance of all the digital redesign techniques, whereas for both T = 0.1 and T = 0.4 the optimal digital redesign has a slight edge over the ROPIM method. This is especially true at the controlled output and for T = 0.4 where the slower settling time of the ROPIMbased system as compared to that of the system based on the optimal redesign, as seen on Figure 3(b), renders the L 2 norm and ITAE index [11] of the error signal larger than those calculated for the optimal redesign.

2 Comparative Study Consider the linear, time-invariant continuous-time control system used in [3] as a benchmark with the structure of Figure l(a) and blocks given by H(s) = 1, F ( s ) = 1 and

~(s)

=

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=

s ~ + 10.42s + 20 s 2 + 32.44s + 2 0 ' 20 s(l+s/10)(l+s/30)"

(1) (2)

Digital redesign is performed using the optimal technique of [31, the reduced-order plant input mapping (ROPIM) method of [8], the reduced-order plus truncated plant input mapping (ROTPIM) method described in [10], and the Tustin's and matched pole-zero (MPZ) discretizations of f~(s), for sampling periods of T = 0.1 (which corresponds to half the rise time t~ of the closed-loop continuous-time control system) and T = 0.4, as used in [3]. The resulting sampled-data control systems have the structure shown in Figure l(b), where some blocks can be unity depending on the digital redesign method used, with the ZOH at control input. The set of discrete-time controllers calculated with the various methods is given in Tables 1 and 2, where e = (z - 1 ) / T .

2.2 Simulations w i t h F i x e d - P o i n t and R e s t r i c t e d N u m b e r of Bits

Arithmetic

A control system is truly practical when it performs relatively well under fixed- a n d / o r floating-point arithmetic and finite number of bits. With the worstcase scenario being the fixed-point arithmetic computations, it is expected that the orders of the discretetime controllers should influence the performance of the sampled-data control system, as opposed to the case when simulations are performed with floatingpoint arithmetic and a relatively large number of bits, e.g. > 32. In this subsection, the discrete-time controllers are subjected to fixed-point arithmetic, and 8and 16-bit representations and computations with scaling. The step responses for T = 0.1 and T = 0.4 are shown in Figures 4 and 5.

2.1 Simulations w i t h Floating-Point A r i t h m e t i c and Large N u m b e r of Bits Figures 2 and 3 present the step responses at control input and controlled output, where CT denotes the continuous-time control system. The responses are almost identical for the ROPIM and the optimal methods for both values of T. On the other hand, the local digital redesign methods result in unstable closed-loop systems at the largest sampling period, and the ROTPIM method offers no overshoot in the controlled output although it presents a slow rise time for the two sampling periods. The sampled-data control system obtained with the ROPIM method has one advantage over that obtained with the optimal digital redesign technique: it consists of low-order controllers. However, the ROPIM-based sampled-data control system possesses one drawback: two discrete-time controllers are implemented instead of only one. This problem can be solved by using the R O T P I M method if a slower rise time is tolerable.

The graphs show that the ROPIM-based sampled-data control system implemented with 8-bit controllers (8 bits are used for both T = 0.1 and T = 0.4) offers a superior performance to that obtained with the ROTPIM (which is also implemented with 8 bits for the two sampling periods) and the optimal digital redesign methods. It is worth noticing that the control blocks obtained with the optimal digital redesign are implemented with 8 bits for T = 0.1 and 16 bits for T = 0.4, and that doubling the number of bits for T = 0.4 is still not sufficient for the optimal digital redesign technique to match the performance attained with the ROPIM method.

Tables 3 and 4 provide the performance measures (norms and index) as applied to the control-input and controlled-output error signMs. The control-input error is defined as the difference between the control inputs of the sampled-data and continuous-time control systems, and a similar definition applies to the controlledoutput error with the controlled output signal replacing the control input. An analysis based on signal norms is

3 Conclusions For the benchmark control system considered in this paper, the comparative study has shown that the

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reduced-order plant input mapping method, and not the optimal digital redesign approach, offers what control engineers need in practice: simple controllers having a superior behavior in face of finite wordlength effects for fast and slow sampling frequencies. For a more exhaustive analysis of the performances obtained with the various digital redesign techniques, including experimental studies, the reader is referred to [10] and

[12] C.A. Rabbath, A Characterization and Performance Evaluation of Digitally Redesigned Control Systems, PhD Thesis, McGill University, Montreal, Canada, 1999.

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[121. References [1] K.J. Astrom & B. Wittenmark, ComputerControlled Systems: Theory and Design, Prentice Hall, N J, 1990.

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[2] B.D.O. Anderson, "Controller Design: Moving from Theory to Practice", IEEE Control Systems Magazine, pp. 16-25, August 1993. [3] N. Rafee, T. Chen and O.P. Malik, "A Technique for Optimal Digital Redesign of Analog Controllers", IEEE Trans. on Control Systems Technology, Vol. 5, No. 1, pp. 89-99, 1997.

(b)

Figure 1: (a) Continuous-time and (b) sampled-data control systems

[4] H. Oz, L. Meiroviteh and C.R. Johnson, "Some Problems Associated with Digital Control of Dynamical Systems", Journal of Guidance and Control, Vol. 3, No. 6, pp. 523-528, 1980.

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[5] B.D.O. Anderson and Y. Liu, "Controller Reduction: Concepts and Approaches", IEEE Trans. Automatic Control, Vol. AC-34, No. 8, pp. 802-812, 1989.

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[6] B. Bamieh, "Intersample and Finite wordlength Effects in Sampled-Data Problems", Proc. 35th Conf. Decision and Control, pp. 1272-1277, Kobe, Japan, 1996.

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[7] C.A. Rabbath, Real-Time Simulations: Pentium vs. DSP, Technical Report, Opal-RT Technologies, Montreal, Canada, December 1999.

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[8] C.A. Rabbath, N. Hori, P.N. Nikiforuk and K. Kanai, "Order Reduction of PIM-Based Digital Flight Control Systems", Proceedings of the IFAC World Congress, Vol. Q, pp. 127-132, Beijing, China, 1999.

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[9] A.H.D. Mark~zi and N. Hori, "A New Method with Guaranteed Stability for Discretization of Continuous-Time Control Systems", Proc. American Control Conference, pp. 1397-1402, 1992.

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[10] C.A. Rabbath and N. Hori, "Comparative Study of Digital Redesign Methods in the Control of a Fast Positioning Mechanism", Proc. Canadian Congress of Applied Mechanics, pp. 343-344, Hamilton, Canada, 1999.

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[11] D. Graham and R.C. Lathrop, "The Synthesis of Optimum Transient Response: Criteria and Standard Forms", Trans. AIEE, vol. 72, part II, pp. 273-288, 1953.

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T a bl e 1: C o n t r o l l e r p a r a m e t e r s for T = 0.1 Optimal Digital Redesign 0.51 le6-I-21.762e5-1-377.15e4 -1-3370.8e3t 16194~2 +39000E-I-35800 = e6 +49.271eh+971.98e4 +9678.4e3 +49803e2 +117290¢+78800 (with order r e d u c t i o n ) 0"098e~+1'379c+5"643 ROPIM ~-~T(£) = e2_t_14.730¢+56.335 ~[I TI,(E )\ = 0"462ez+3"553e+5'643 0.098e2+l.379et5.643 0"098e~tl'379e+5"643 rI ~ ~ ROTPIM ~ T (C) ~2+14.730e_t_56.335 , TiE) = I 0.588~ ~+4.648c+7.485 Tustin's Method ~-~T(£) e2+12,889~+7.485 0.478e~-l-3.677et 5.840 MPZ = e2+10.194e+5.840

Ta ble 2 : C o n t r o l l e r p a r a m e t e r s for T = 0.4 Optimal Digital Redesign O.162e4tl.46e3+4.9e2t7.278¢+4,041 T(C) = e4+9.77a3+35.038e2+54.731z+31.414 (with o r d e r r e d u c t i o n ) II ( ~ O=154~tO'612e+0'586 ROPIM ~ T ( e ) : O'094e~tO'47e+0'586 ~2+5.426¢+7.32 ~ T ~ ) : 0,094~2+0.47¢+0.586 0'094e~t0'47e+0'586 II z ROTPIM ~'~T(C) ¢2+5,426¢+7.32 ~ TiE) 1 0.469e~+2.222e+2.413 Tustin's Method ~ T (C) e2+4.879~+2.413 MPZ ~ T ( E ) "= 0.364e~+l.453e+l.390 ¢2+3.056¢+1.390

Ta ble 3: Q u a n t i t a t i v e m e a s u r e s on t h e c o n t r o l - i n p u t errors for T = 0.1 (top of each e n t r y ) a n d T = 0.4 ( b o t t o m ) L °° n o r m L ~ norm I T A E i n d ex 4.12 x 10 -1 8.68 x 10 - 2 1.27 x 10 - 2 Tustin MPZ ROPIM ROTPIM Optimal

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Ta ble 4: Q u a n t i t a t i v e m e a s u r e s on t h e c o n t r o l l e d - o u t p u t errors for T = 0.1 (top of each e n t r y ) a n d T = 0.4 ( b o t t o m ) L ~ norm L 2 norm I T A E index 2.27 × 10 -1 1.17 x 10 -1 5.42 × 10 - 2 Tustin MPZ ROPIM ROTPIM Optimal

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