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Abstract—In this paper the power losses of efficient capacitive converters with multitude transfer ratio values are discussed. The loss mechanism circuits, based ...
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 62, NO. 11, NOVEMBER 2015

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On Loss Mechanisms of Complex Switched Capacitor Converters Yuval Beck, Member, IEEE, Nir Eden, Shira Sandbank, Sigmund Singer, Member, IEEE, and Keyue Ma Smedley, Fellow, IEEE

Abstract—In this paper the power losses of efficient capacitive converters with multitude transfer ratio values are discussed. The loss mechanism circuits, based on general transposed series parallel (GTSP) topology, is studied and the losses are calculated, which in turn enables the “bottlenecks” to be identified and overcome. The calculations show that for a given number of switching cells the power losses of such converters are mainly dependent on the voltage conversion ratio, the topology function, the resistances of the switches in on and off states, the ESR of the capacitors, the switching frequency, the voltage drop, and the load. The theory explains the fact that was observed in experiments, that for low voltage conversion ratio values, efficiency decrease was measured. It is shown that for these low voltage ratio values the mechanism associated to the off resistance of the switches is more dominant and reduces the efficiency. This power loss estimation can be used as a powerful tool for the performance optimization of capacitive converters. The theoretical results are verified experimentally on a 10-cell GTSP converter prototype. The experimental results show good agreement with the proposed theory. Index Terms—DC-DC power conversion, integrated circuits, multiplying circuits, switched capacitor circuits.

I

I. INTRODUCTION

NTEREST IN switched capacitors (SC) converters has grown since they can be fabricated as integrated circuits [1], [2] and many topologies are proposed and implemented in the literature [3]–[5]. It should be noted that these converters have some disadvantages compared with inductive ones: 1) lower efficiency, especially in SC with increased numbers of DC-DC voltage ratios, which imply a larger number of capacitors and switches, and 2) in many topologies, a relatively small number of fixed input/output voltage transfer ratios are offered [6], [7]. Nevertheless, since SC converters are an attractive technology, they are also used in many practical applications Manuscript received April 21, 2015; revised July 23, 2015; accepted September 03, 2015. Date of publication September 28, 2015; date of current version October 26, 2015. This work was supported in part by the BSF under Grant No 2011507. Some of the topologies are protected under provisional Patent No.P-73186-USP. This paper was recommended by Associate Editor F. M. Neri. Y. Beck is with the Faculty of Engineering, Holon Institute of Technology, Holon 58102, Israel (e-mail: [email protected]). N. Eden was with the School of Electrical Engineering, Tel Aviv University, Tel Aviv 69978, Israel. He is now with Controlrad, Kfar Saba 4464004, Israel (e-mail: [email protected]). S. Snadbank was with the School of Electrical Engineering, Tel Aviv University, Tel Aviv 69978, Israel. She is now with the Medical School at Tel Aviv University, Tel Aviv 69978, Israel (e-mail: [email protected]). S. Singer is with the School of Electrical Engineering, Tel Aviv University, Tel Aviv 69978, Israel (e-mail: [email protected]). K. M. Smedley is with the Department of Electrical Engineering and Computer Science, University of California at Irvine, Irvine, CA 92697-2700 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSI.2015.2479056

where a converter with high voltage transfer gain and reduced semiconductor voltage stress or current is demanded, such as renewable energy systems [8], [9]. Among the various topologies of SC there is a large family of topologies which are “loss free” (in principle only) under the three following assumptions. 1) The voltage drop (between the charging and the dis. This is implied charging circuits) is negligible: by high switching frequency: . (conduction 2) Switch losses are negligible: losses, switching losses, etc.). 3) Capacitors ideally have no losses (ESR etc.). Clearly, in practical implementation of SC converters, switching frequency is finite and therefore there is a voltage drop on the capacitors. Moreover, very high frequency implies switching losses. Furthermore, the switches and capacitors have inherent conduction losses because of the capacitors' ESR and the switches' on resistance. The attractiveness of SC converters as integrated converters requires the understanding and analysis of their loss mechanisms. This analysis is essential for assessing the performance of these converters as well as their limits [10], [11]. Previous analysis mainly focused on computing limits for output impedance of conventional SC DC/DC converters [10], [12], [13] and optimization, which allows performance evaluation of SC converters and comparison among the SC topologies [10], [14]. Several authors [15], [16] have studied average state-space methods for analyzing SC DC/DC converters, and the influence of the on-resistance of the switch on the losses [17]. Another recent work addresses the issue by dividing the analysis of the entire efficiency problem into separate analysis of the charging and discharging circuits [16]. In this work alongside the presented theory a list of 40 papers dealing with various efficiency issues in SC converters are listed. However, little work has been done on analytical steady-state loss of more complex SC topologies, which apply a larger variety of DC/DC voltage conversion ratios. In these types of converters study of the loss mechanism is even more essential for defining the characteristics of the elements (especially the switches) used to implement the topology. Furthermore, such analysis enables us to identify the “bottleneck” parameters which influence the performance of the converter. It can also enable some conclusions to be drawn regarding future developments. It should be mentioned here that the complexity of these SC converters is in the sense of a more versatile switching system in order to implement a converter with a large amount of input/ output voltage ratios for applications such as voltage regulation and voltage modulation [12], [17]. Experiments on a 10 cell SC converter with 138 voltage ratios showed that in the low range of the voltage conversion, there is a sharp decrease of the efficiency. This led as to investigate

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Fig. 1. A single switched capacitor model with conduction losses.

deeper and we found out that in this type of converters the loss mechanism due to the off resistance of the switches, which at first glance seem to be negligible, have an essential influence on the total loss of the converter in the low range of the conversion ratios. This is due to the complexity of the topology which implies a connection of many switched in parallel that in turn reduce the total off resistance and increase the leakage currents in the converter. In this paper the general theory of calculating the average power losses owed to the various resistive parameters of the switch and capacitor equivalent series resistance is presented. A circuit containing a single capacitor is analyzed first, and power loss analysis also includes the choice of operation frequency and capacitor size in terms of reducing losses. This simple model which was thought to be sufficient was found unsatisfactory when more complex topology was examined. All topologies discussed in this paper are confined to circuits in which multitude but fixed conversion ratios and the topology determines the input/output voltage ratio by the control. The theory of analyzing the loss mechanisms as a multiplication of a function of the topology and a function of the circuit parameters is presented as the tool to assess the contribution of the topology structure, as well as the physical parameters of the switches and capacitors, on the total loss of the converter. The results of the theory developed in this paper show that the topology function related to the on as well as the off conductance of the switches are uniquely dependent on the topology of the converter. It is also shown that the seemingly negligible contribution of the off conductance of switches has substantial contribution to the total loss when a large number of cells are connected in parallel (which imply higher conductance and higher leakage currents) at the low voltage conversion ratios. The theory is devised for analyzing the power losses in a general configuration of a general transposed series parallel (GTSP) converter [17], [18]. This configuration is based on charging and discharging the capacitors in transposed configuration, such as parallel branches of series capacitors in the charging circuit and series elements of parallel capacitors in the discharging circuit, in order to achieve the desirable input/output DC voltage ratio. This type of conversion can be seen as transferring the topology through a gyrator [19], [20]. This topology has a large number of voltage conversion ratios and the ability to multiply and divide by integers, as well as fractions. It should be noted that many SC topologies (such as series/parallel topology) can be viewed as derived cases of GTSP. An experimental example of a 10-cell GTSP prototype converter is presented for measuring the power losses of all conversion ratios in the case of a 10-capacitor step-up GTSP converter. The theoretical results are verified experimentally and are in good agreement.

Fig. 2. Four switch dual circuit configuration for single capacitor.

power loss which affect the performance of the converter [21]. Three main mechanisms are: 1) Conduction losses owed to parasitic resistances of the capacitor and the switch on-state re. 2) Losses owed to voltage drop across sistance, the switching capacitor, which appears when the capacitor is charged from the input source (at the charging state circuit) and . connected to the load (at the discharging state circuit), . The total loss is 3) Switching losses, therefore: (1) Next an analysis of these mechanisms is performed on a single capacitor and a switch in order to evaluate the contribution of each term in (1). is connected as a SC. This In Fig. 1 a single capacitor can be considered as a simple case of a complete SC converter. When the switch is at terminal 1 the circuit is in a charging state and when the switch changes to terminal 2 the circuit is in a discharging state. The circuit operates at switching frequency , the on-state resistance of the switch is and the equivalent series resistance (ESR) of the capacitor is . The total series resistance of both on-state resistance and the (namely, capacitor ESR will be referred to as ). It should be mentioned here that for simplicity the converter is presented as in Fig. 1, however, closer look at the circuit imply that the output voltage is zero during the charging state due to the absence of energy storage elements to maintain the output voltage. In practice to avoid this in continuity and the necessity for an output large capacitor, a dual capacitor circuit is introduced as in Fig. 2. The concept presented in Fig. 2 consists of two identical complimentary circuits. On the charging circuit the switches are turned on and the are switched off. In this situation the upper capacitor is connected to the source and the lower converter is connected to the load. This situation is reversed when the switches are turned off and the switches are turned off. The process is then continuing in each cycle of the switching frequency and assure that a capacitor is always connected to the source and the load and therefore there no discontinuity in the input and output voltages and currents. B. Voltage Drop and Conduction Loss Contributions , the voltage When the capacitor is connected to a load, drop on the capacitor at the end of the discharging circuit (when the switch is connected to terminal 2) is:

II. LOSS ANALYSIS OF A SINGLE CAPACITOR A. General The switching process involves losses which are frequency-dependent. There are various mechanisms for these

(2) where

.

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The energy transferred to the load at the discharging time, T/2, is: (3) The energy loss on

can be written as: (4)

When the switch is connected to terminal 1 in the charging circuit the current through the capacitor will be: (5) Assuming that the capacitor is charged to the voltage of the , with a short time constant in comparison with the source, , at the time of conneccharging time of the circuit tion to terminal 1 the capacitor voltage will be: (6) substituting (6) into (5) yields: (7) Now the energy loss on the resistance charging circuit can be calculated as follows:

at the

(8) Substituting (2) into (8) yields: (9) during a cycle Now the total energy loss on the resistance of charging and discharging will be (from (4) and (8)): (10) When the energy loss is normalized by the transferred energy to the load , the following expression is obtained: (11) Given that power losses can be written as:

the normalized energy and (12)

In (12) the two terms on the right side are representing the normalized conduction losses and the normalized voltage drop losses. Namely, in this scenario. It is evident from (12) that for high frequency, (13) and therefore (12) becomes: (14)

Fig. 3. Power losses as a function of the switching frequency.

From the above analysis it is evident that the voltage drop is inversely proportional to the switching frequency and also to the capacitor size C as in (2). Therefore this loss is high at low switching frequencies and it decreases as the switching frequency becomes high. This also applies in the case of capacitor size C; the power losses owed to the voltage drop are high at small sizes of the capacitor and decrease as the size increases. Regarding It is also noticeable from (12)–(14) that at high frequencies the conduction losses are more dominant than the losses associated with the voltage drop. At high switching frequencies, the switching loss mechanism dominates the total losses. It is proportional to the semiconductor (of the switch) cross-section and to the switching frequency: (15) It is clear from (15) that this power loss increases as the switching frequency increases; thus the converter efficiency decreases rapidly as the switching frequency becomes high. C. Summary of Loss Mechanisms Summary of (12) and (15), for the various switching process power loss mechanisms the power losses for a given output power as a function of the switching frequency are as shown in the sketched diagram in Fig. 3: The mid-range frequency is considered as the frequency range in which the sum of the losses is minimal. It appears that choosing the switching frequency in the mid-range would minimize the total losses; with a switching frequency which is low enough, the switching losses are negligible. On the other hand, it would be desirable to choose a switching frequency which is high enough to allow only partial discharging of the switched capacitor in the discharging state circuit and yet is not too high to allow nearly complete charging of the switched capacitor in the charging state circuit. This would reduce the voltage drop across the switched capacitor, and consequently would minimize the voltage drop-related losses. Therefore, choosing the appropriate midrange switching frequency will result in negligible second order voltage drop losses and switching losses and therefore the paper will deal with only the conduction losses under the assumption of proper frequency choice. In the analysis of a single capacitor the off resistance of the switch was neglected since its value is much greater than the . However, as will be shown, this resistance signifivalue of cantly influences the losses and efficiency in SC converters with an increased number of voltage ratios. This will be discussed in detail.

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III. LOSS ANALYSIS IN CONVERTERS WITH MULTITUDE VOLTAGE TRANSFER RATIOS A. Analysis of Loss in Complex SC Converters Complex SC converters are referred here to converters with numerous input/output DC/DC voltage ratios. These converters require a switching network to enable all possible configurations of the converter. In these multitude voltage transfer ratio converters, the loss function is assumed to be dependent on the following: 1) the topology parameters which include the number of cells and the transfer ratio of the converter, which is dependent on the interconnections of the topology at the charging and the discharging state circuits of the converter. 2) The physical parameters of the converters which are the ESR of capacitors, the on and off resistances of the switches and the resistance of the load. Therefore, normalizing the loss function by the load power we attain:

Fig. 4. GTSP topology. (a) Charging state circuit. (b) Discharging state circuit.

(16) is a dimensionless function of the topology and is where an normalized function of the physical parameters (for example the on resistance of the switch divided by the load resistance). Further analysis of the topology loss mechanisms and the attempt to present the losses elegantly as shown in (16) indicates that the presentation is slightly more complex and has the general following form (as will be shown ahead): (17) is a vector of the normalized (by the load power) where is the matrix losses at the on and off states of the switches, is a normalized of the interconnections of topologies, and resistances vector as shown in (18). (18) In the above expression there is a separation between the losses associated with the on-resistance (it should be mentioned that the ESR of the capacitors are included in ) and the off-resistance of the switches. Equation (18) emphasizes the relation of the normalized on and the off parameters of the switches. It is obparametersvious from (18) that the behavior of the topology functions and have a crucial influence on the normalized losses and . In the following sections we and for complex SC converter. will first calculate Then, it will be shown that in low conversion ratios values (0.1 function is more dominant than up to about 0.7) the , and as the conversion ratio value increases the roles rein high conversion ratio values verse and the influence of becomes negligible. B. GTSP Converter Overview There are various types of SC converters which can produce multitude voltage ratios. In Fig. 4, a GTSP topology is presented [17]. The figure shows a general configuration with columns. capacitors where , In each column there are where and are integer finite numbers. The operation of the converter is based on charging the columns of capacitors as shown in Fig. 4(a) (note that in each column any number of capacitors can be applied, this is presented in dotted lines). In each capacitors. Then, in the discharge stage the column there are

Fig. 5. Four switch dual circuit configuration in the general case.

capacitors are connected in series connection in rows. In each capacitors. The transition between the charging row there are and the discharging circuit transposes the topology (from series connection of parallel branches to parallel connection of series branches) and this transformation resembles a topology change through a gyrator [19]. It was shown in [18] that the DC/DC input/output voltage conversion ratio of this converter is: (19) The GTSP topology as in Fig. 4 is connected to the input at the charging state circuit and to the output at the discharging state circuit. Thus, there is discontinuity in the input and output voltages and currents. To avoid this discontinuity, capacitors must be connected at the input and output terminals of the circuit. When integration is considered, such capacitors will have to be connected externally. To eliminate these external capacitors the following dual circuit concept is suggested. As was previously presented in Fig. 2 the concept of dual circuits is extended to the general case as shown in Fig. 5. In this case the circuit consists of two identical complimentary circuits (not only one capacitor), which connect to the source and to the load in each state of the circuit as was explained earlier. On the charging state circuit the switches are turned on and the are switched off. In this situation the upper converter is connected to the source (in its charging state circuit configuration such as in Fig. 4(a)) the lower converter is connected to the load (in its discharging state circuit configuration such as in Fig. 4(b) and noted as the complimentary circuit in the figure). This situation is reversed when the switches are turned off and the switches are turned off. It should be mentioned here that all circuits presented in the paper are assumed to work in this manner and the experimental prototype was realizes in this dual circuit concept as well. C. The Basic Cell To achieve practical connection of this topology a network of switches must be implemented. The network must enable series

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Fig. 6. A basic cell in GTSP topology.

as well as parallel connection of each capacitor. In [22] the minimum number of switches required for implementation of this topology was proven to be five. For modularity a suggested cell was introduced as shown in Fig. 6. The basic cell consists of six terminals, as shown in Fig. 6. terminal is connected to the positive terminal of the The terminal is connected to the negative terminal source. The and terminals are the input of the voltage source. The and output terminals of the cell accordingly. The cell consists to . of a capacitor and five supporting peripheral switches, These switches enable all the required connections of the capacitor to the voltage source terminal, the load and the next or prior cell. and enable connection to and terminals, and enable parallel connection of the capacitors and enables series connection of two successive capacitors. The state of each switch in each cell is assigned by a control function. Even though there are five switches in each cell, it is interesting to note that for each assigned voltage ratio, only a maximum of three switches will be switched on and off in the high switching frequency. The other two switches will enable other topologies when the voltage ratio is changed. Furthermore, the ability of this cell structure to connect the capacitor in series or parallel to any other capacitor in the converter suggests that this topology is a more general case to other known SC topologies such as series-parallel (SP), ladder, and so on. Therefore, the loss analysis of this converter can directly imply the losses and efficiency of other topologies. In Section II the ESR of the capacitor and the on resistance of the switches were taken into account in the loss calculations. Since the cell of Fig. 6 is part of a more complex converter it will be shown next that the above-mentioned resistances are not the only loss-affecting mechanisms. When the converter is implemented with, off the shelf state of the art switches, with finite off resistance, it will be shown that because the multiple switches are connected in parallel the leakage current through the off resistance of the switches is not necessarily negligible and in some operating states they are even the dominant loss mechanism. When a capacitor is connected in parallel to the input termiand are switched on while all the others nals and , are switched off. When a switch is switched on namely and when the switch is switched the effective resistance is . The question is what the loss off the effective resistance is dissipation is on the turned-off switches. It is obvious that the loss can be calculated from the equation: (20) is the linkage current through the resistance , is the voltage drop over the depending on the topology of the connection, as will be considered next.

where

Fig. 7. A GTSP configuration with switches on resistance and ESR. (a) Charging circuit. (b) Discharging circuit.

D. Losses Due to the on Resistance of the Switches and the Capacitors' ESR First, the losses owed to the net sum of the on resistance of the , and the capacitor's ESR are considered. Since they switch, are in series the term is used and is evaluated as . In Fig. 6 a GTSP with arbitrary voltage is considered. In this topology the switches and capacitor parasitic resistance are . Note that Fig. 7(a) describes combined and are denoted as the charging circuit and Fig. 7(b) is the discharging circuit of the configuration. Since the converter is assumed to work in the mid-range frequency in which the losses owed to the voltage drop from input , it is sufficient to calcuto output are small, namely, late the power losses at the discharge state circuit only (since the current owed to this mechanism is negligible in the input). The power loss in the parasitic resistances at the discharging state circuit is:

(21) Then the ratio between the power losses on the parasitic and switch resistors and the output power (assuming constant power on the load) can be written as: (22) Comparing this with (18) yields: (23) E. Losses Due to the Off-Resistance of Switches Now, considering the contribution to the losses of the off resistances of the switches in a general case of GTSP converters, it is important to note that these losses must be calculated both for the charging state circuit and for the discharging state circuit. This is because the off switches are under a voltage drop (which can be as high as the input voltage) in both states of operation. In Fig. 8 the charging state circuit of a GTSP converter is shown. In this circuit the on resistances of the switches are replaced by a short circuit (since their contribution was already calculated) and the off resistance of each relevant switch is noted

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Fig. 8. A GTSP configuration in the charging state circuit with the relevant off switches' resistances.

as . The dotted lines in the figure represent the possibility of extension of each column to any number of capacitors. the voltage drop in the th row, is On each horizontal and therefore the power loss on each resistor in the ith column is: (24) There are horizontal resistors and therefore the total : loss of all off resistors is the net sum of all columns, , so (25) Now the voltage at each junction on the top of each capacis: itor in column

Now the net sum of all losses associated with the charging state circuit and the off resistance of the switches is the sum of (25), (28), (30), and (31):

(32) The above expression was obtained using the voltage transfer as in (19). ratio of the converter The normalized form will then be:

(33)

(26) The voltage drop on each connected between the voltage source positive terminal and the junction at the top of the capacitors is:

Using the terms as in (18) yields part of that part of the is: topology function

(27) The total loss of the top off resistors in the charging state will be: circuit (28) The voltage drop on the bottom resistor is the junction voltage : (29) The power loss on all resistors connected to the junction at the bottom of the capacitors and the ground terminal will be: (30) The last power loss in the charging state circuit is on the resistor connected to the output. This loss can be calculated as: (31)

(34) The same procedure is repeated for calculating the power losses owed to the off resistances in the discharging state circuit. The GTSP configuration in the discharging state circuit with the relevant off resistances of the switches is shown in Fig. 9. The loss on the input of resistance will be: (35) The power loss of all resistors connected between the bottom of the capacitors and the negative terminal of the voltage source is: (36) The total power loss on the resistors connected between the top of the capacitors and the positive terminal of the voltage source is: (37)

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Fig. 9. A GTSP configuration in the discharging state circuit with the relevant off switches' resistances.

The power loss on the diagonal resistances which connect each cell in series to the successive cell is: (38) The total power loss in the discharging state circuit will then be the sum of (35)–(38) and after normalization:

(39) Presenting (39) in terms of (18) yields the second element of as:

Fig. 10. The 10-cell dual converter prototype.

SP topology can be seen in only one column of GTSP topology. Repeating the above procedure of this topology yields a loss function in the on state of the switches, as in (22) and (23) ; where M is the conversion ratio. namely The expression regarding the off resistance in the charging state circuit is:

(40) The total loss at the off state of the switches is the sum of the in (18)is losses in (33) and (39). The topology function now the sum of (34) and (40) and therefore: (41) Now, taking into account all loss mechanisms and assuming that the converter is working at the mid-range frequency (namely the switching losses are negligible) the total normalvector ized loss of the converter will be the net sum of the of (17). This can be explicitly written from (18) as:

(42) It should be mentioned here that an ideal switch which imand will result in negligible losses plies will tend to zero. since all expressions of F. Analysis of Loss in SP Topology As mentioned above, the GTSP converter can be considered as a generalized case of other converters such as SP converters.

(43) It is easy to show that the expression in (43) is exactly equal . Namely, the loss functions are equal to a to (34) when GTSP converter with one column which is an SP converter. As in (43) the reduced expression for SP converters can be written as: (44) IV. EXPERIMENTAL RESULTS For verification of the results a unique 10-cell GTSP converter was implemented as seen in Fig. 10. The converter consists of two dual circuits consisting of 10 cells each. Namely, there are two dual 10 cell converters that work in a complimentary manner as was explained and shown in Fig. 5. The converter has a 138 voltage conversion ratios as is expected by the sum of partition functions of 10 [17]. The prototype parameters are listed in Table I. It should be mentioned here that the on-resistance in Table I was taken from the datasheet of the switch and the off-resistance

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TABLE I THE 10 CELL GTSP CONVERTER PROTOTYPE PARAMETERS

Fig. 12. Efficiency of the GTSP prototype vs. voltage conversion ratio for 1 V input and a 100 load.

Fig. 13. The various normalized losses for the theoretical results.

Fig. 11. Efficiency calculated and measured for various SP converter voltage ratios.

was assessed and measured and due to the nature of leakage currents this parameter is only a good assessment. The prototype is operating under open loop conditions and controlled by a program on Altera Cyclone III hardware which enables the selection of any desired voltage transfer ratio by applying a lookup table for all possible conversion ratios. The experiments were carried out with an Agilent B2902A Precision Source/Measure Unit (SMU). This test device has excellent precision (with minimum 10 fA/100 nV sourcing and measuring resolution), and automation capabilities. Next, the experimental results for GTSP as well as SP converters are shown and compared to the theoretical model that was developed in the previous section. All expressions in Section III were developed for the normalized losses, namely, for .The efficiencies are then calculated by: (45) In Fig. 11 the results of the efficiency of a converter of five capacitors are presented. The converter has the following voltage ratios (1/10, 1/9,1/6,1/5, 1/4, 1/3, 1/2, 1,2,3,4,5). The experimental results are shown along with the theory in Section III. It can be seen that the theoretical model predicts the experimental results with good agreement. Next, the results were generalized with a full 10-cell GTSP converter. The converter was programmed to scan all possible

138 conversion ratios and in Fig. 12 the experimental results are shown along with the theoretical calculation as presented in (42). Next, Fig. 13 shows the normalized power losses of the on and off resistances as was developed in (42) separately. This yields a better understanding of the contribution of each mechanism to the total loss of the converter. It is evident from Fig. 13 that the loss at the low DC/DC voltage ratio values is dominated by the off-resistance contri, resulted by the increase in that range. bution This is due to the large amount of parallel switches which are involved in achieving these voltage ratios. At higher converinfluence is increased and sion ratios (0.5 and above) the influence becomes negligible, therefore, the losses the in these voltage ratios are dominated by the on parameters of . The results shown in Fig. 13 the converters component graphically explain the theoretical results of (23), (34), and (40). In (23) the loss mechanism associated with the on-resistance is linearly increases as the conversion ratio. This is demonstrated by the star dotted graph above. The result of (34) and (40) for the influence of the off-resistance is nonlinearly decaying as the square dotted graph shows. Then, the circle dotted graph is the sum of the contributions as predicted by (42). It vividly shows the transition point between the domination of the off-resistance on the total loss in the lower transfer ratios, to the right side of the graph where the influence (at 0.7 transfer ratio) of the on-resistance is taking over and dominated the behavior of the total loss. Finally, the control was programmed in such a way that the output power was a constant of 100 mW with input voltage of

BECK et al.: ON LOSS MECHANISMS OF COMPLEX SWITCHED CAPACITOR CONVERTERS

Fig. 14. Efficiency of the GTSP prototype vs. voltage conversion ratio for constant 100 mW output power with 1 V input voltage.

1 V. The results are shown in Fig. 14 with the theoretical prediction as well. Yet again, good agreement is presented between the theory and the experimental measurements. V. CONCLUSIONS AND DISCUSSION In this paper the loss mechanisms of multitude voltage conversion ratio converters are analyzed. The analysis includes analytical expressions which are constructed from the converters parameters function multiplied by a topology function. The analysis and the results shown in this paper offer some practical conclusions on the design as well as the desired improvements which are necessary in order to improve the efficiency of such converters. The paper reviews the various loss mechanisms which influence the efficiency of switched capacitor converters. The operation frequency of the converter was in the range where the losses are minimized, as shown in Fig. 3 and [17], and therefore switching losses and voltage drop losses are reduced and not addressed here. At first glance the conduction losses seem to be influenced by the net sum of series resistance of both the on state .A resistance and the capacitor ESR which is referred to as closer look at multitudinous voltage conversion ratio converters (SP topology and GTSP topology), reveals the fact that there are states of the converter in which many capacitors are connected in parallel, such as in the low voltage ratios values. When these capacitors are disconnected (from the main power or the load) the associated switches are turned off and the topology function associated with their off resistance is becoming a dominant parameter. The off resistances are now in parallel due to the multiple paralleled switches and therefore the total off resistance is now reduced dramatically. The result is a leakage current which is not negligible and produces some power loss. The analysis of these off resistances are shown in the paper and the losses owed to this mechanism along with the on resistance and the voltage drop losses are verified by comparing the theory and the experiment, as shown in Figs. 11–14. The results show that the developed theory is in good agreement with the experimental results. It can be seen in Fig. 11 and Fig. 14 that for a wide range of voltage transfer ratios (0.7 to around 3.0) this converter was operated at efficiencies of over 80% with peak efficiency of 93%, which is a very promising efficiency even though it is only a prototype. The results suggest that in order to improve the converter efficiency in a wider range of transfer functions a low on resistance is required. Moreover, usually the off resistance of a switch is considered to be high enough and therefore not considered as

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a substantial loss mechanism. The results, which are supported by the experiments as well as the theory as summarized in (18), show that the losses are strongly associated with a topology function (as in the center matrix of (18)). Therefore, the improvement of switches also requires making sure that when a switch is disconnected it has a very high resistance. In summery when a step-down SC converter with low converpasion ratio (less than around 0.7) is to be achieved, the rameter of the switch is essential. It is obviously desired for the ultimate converter to use switches with very low on-resistance and very high off-resistance. These two quantities are unfortunately contradicting each other since low on resistance require larger cross section area of the switch which in return imply a lower off-resistance as well. The practical conclusion is therefore, to either limit the operation mode of the converter to the region of high efficiency (around 0.7–3 in the prototype presented in this paper). This operation is probably the best way to work with this converter. A second strategy might be to split the operation mode of the converter into two. Namely, use a dual set of switches with the appropriate characteristics, assigned by the control according to the desired transfer ratio. When a low transfer ratio is required some compromise regarding the on-resistance can be made as long as the switches will have a considerably high off-resistance and vice versa regarding the higher conversion ratios. In a way this solution might not be the best practice since there is over design of hardware and the power density will reduce due to the fact that there are many switches which are in idle state. So probably this solution is possible but it is more theoretical. The last scenario can be the design of separate converters for the various regions in order to properly meet the efficiency requirements. In the case when a large range of conversion ratios are required, it is important to understand that implementing it by a single converter will cost in efficiency. In this case the theory presented here can also be used as a tool for predetermine the efficiency loss at the outer regions of the conversion ratios operating modes. REFERENCES [1] O.-C. Mak, Y.-C. Wong, and A. Ioinovici, “Step-up DC power supply based on a switched-capacitor circuit,” IEEE Trans. Ind. Electron., vol. 42, no. 1, pp. 90–97, 1995. [2] D. Maksimovic and S. Dhar, “Switched-capacitor DC-DC converters for low-power on-chip applications,” in Proc. IEEE 30th Annu. PESC 1999, Aug. 1999, vol. 1, pp. 54–59. [3] T. Siew-Chong, S. Bronstein, M. Nur, Y. M. Lai, A. Ioinovici, and C. K. Tse, “Variable structure modeling and design of switched-capacitor converters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 9, pp. 2132, 2142, Sep. 2009. [4] C. Y.-F. Ho, B. W.-K. Ling, Y.-Q. Liu, P. K.-S. Tam, and K.-L. Teo, “Optimal PWM control of switched-capacitor DC-DC power converters via model transformation and enhancing control techniques,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 5, pp. 1382, 1391, Jun. 2008. [5] C. Jun and A. Ioinovici, “Switching-mode DC-DC converter with switched-capacitor-based resonant circuit,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 43, no. 11, pp. 933, 938, Nov. 1996. [6] P. Favrat, P. Deval, and M. J. Declercq, “A high-efficiency CMOS voltage doubler,” IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 410–416, Mar. 1998. [7] M. D. Seeman and S. R. Sanders, “Analysis and optimization of switched-capacitor DC-DC converters,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 841–851, Mar. 2008. [8] A. A. Fardoun and E. H. Ismail, “Ultra step-up DC-DC converter with reduced switch stress,” IEEE Trans. Ind. Appl., vol. 46, no. 5, pp. 2025–2034, Oct. 2010. [9] W. Qian, D. Cao, J. G. Cintron-Rivera, M. Gebben, D. Wey, and F. Z. Peng, “A switched-capacitor DC-DC converter with high voltage gain and reduced component rating and count,” IEEE Trans. Ind. Appl., vol. 48, no. 4, pp. 1397–1406, Aug. 2012.

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[10] M. S Makowski and D. Maksimovic, “Perfomance limits of switchedcapacitor DC-DC Converters,” in Proc. IEEE 26th Annu. PESC 1995, Jun. 1995, vol. 2, pp. 1215–1221. [11] C. K. Tse, S. C. Wong, and M. H. L. Chow, “On lossless switchedcapacitor power converters,” IEEE Trans. Power Electron., vol. 10, no. 3, pp. 286–291, May 1995. [12] S. Ben-Yaakov and M. Evzelman, “Generic and unified model of switched capacitor converters,” in Proc. IEEE Energy Convers. Congr. Expo., Sep. 2009, pp. 3501–3508. [13] S. V. Cheong, H. Chung, and A. Ioinovici, “Inductorless DC-to-DC converter with high power density,” IEEE Trans. Ind. Electron., vol. 41, no. 2, pp. 208–215, Apr. 1994. [14] K. D. T. Ngo and R. Webster, “Steady-state analysis and design of switched-capacitor DC-DC converter,” IEEE Trans. Aerosp. Electron. Syst., vol. 30, no. 1, pp. 92–101, Jan. 1994. [15] S. Ben-Yaakov, “On the influence of switch resistances on switchedcapacitor converter losses,” IEEE Trans. Ind. Electron., vol. 59, no. 1, pp. 638–640, Jan. 2012. [16] H.-K. Cheung, S.-C. Tan, C. K. Tse, and A. Ioinovici, “On energy efficiency of switched-capacitor converters,” IEEE Trans. Power Electron., vol. 28, no. 2, pp. 862, 876, Feb. 2013. [17] Y. Beck and S. Singer, “Capacitive transposed series-parallel topology with fine tuning capabilities,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 1, pp. 51–61, Jan. 2011. [18] Y. Beck and S. Singer, “Capacitive matrix converters,” in Proc. 11th IEEE Workshop Control Model. Power Elect. (COMPEL 2008), Aug. 2008, pp. 1–6. [19] M. Ehsani and M. O. Bilgic, “Power converters as natural gyrators,” IEEE Trans. Circuits Syst., vol. 40, no. 12, pp. 946–949, Dec. 1993. [20] A. Cid-Pastor, L. M. Salamero, C. Alonso, G. Schweitz, and R. Leyva, “DC power gyrator versus DC power transformer for impedance matching of a PV array,” in Proc. 12th Int. Power Electron. Motion Control Conf. (EPE-PEMC 2006). [21] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd ed. New York: Springer, 2001. [22] Y. Beck, S. Singer, and L. M. Salamero, “Modular realization of capacitive converters based on general transposed series-parallel and derived topologies,” IEEE Trans. Ind. Electron., vol. 61, no. 3, pp. 1622–1631, Mar. 2014. Yuval Beck (M’05) was born in Tel Aviv, Israel, on November 30, 1969. He received the B.Sc degree in electronics and electrical engineering in 1996, the M.Sc. degree in 2001, and the Ph.D. degree on the subject of ground currents due to lightning strokes in 2007 from Tel Aviv University. Since 1998, he has been with the Interdisciplinary Department, the Faculty of Engineering, Tel Aviv University. In 2008 joined HIT-Holon Institute of Technology, Holon, Israel, as a Lecturer and from 2010 is acting as the head of Energy and Power Systems department at the faculty of engineering. His research interests include smart grid technologies, lightning discharge phenomena; lightning protection systems; power electronics, and photovoltaic systems. Dr. Beck is the secretary of the Israeli section of the IEEE. Nir Eden received his B.Sc degree in electronics and electrical engineering from Ort Braude Collage, Carmiel, Israel, in 2003, and his M.Sc. degree in 2014 from Tel-Aviv University, Israel. His research interests are in the area of power electronics: switched capacitor-based converters and simulation of switched-mode circuits, switches controls and power analysis. He is currently the hardware and system manager at Controlrad systems in Israel.

Shira Sandbank was born in Tel Aviv, Israel, on April 6, 1983. She received her B.Sc degree in electronics and electrical engineering and her M.Sc degree on the subject of switched capacitive converters from Tel Aviv University in 2009 and December 2012, respectively. She worked as a R&D engineer in SolarEdge in power electronics for photovoltaic systems and currently she is a 4th year medical student, Tel Aviv University.

Sigmund Singer (M’80) received the B.Sc. and D.Sc. degrees from the Technion, Haifa, Israel, in 1967 and 1973, respectively. In 1978, he joined the staff of The Faculty of Engineering, Tel Aviv University, Tel Aviv, Israel, where he is currently a Professor. He has been the Department Head of Interdisciplinary Studies in 2000–2004. His areas of research are general circuits and systems theory; power electronics and energy conversion. Dr. Singer’s paper “Realization of loss free resistive elements” was awarded in 1990 the Best Paper of the Year Award by the IEEE CAS Society. He was the chairman of the Israeli Chapter of the IEEE 2005–2010. Keyue Ma Smedley (S’87–M’90–SM’97–F’08) received her B.S. and M.S. degrees in electrical engineering from Zhejiang University, Hangzhou, China, in 1982 and 1985, respectively, and the M.S. and Ph.D. degrees in electrical engineering from the California Institute of Technology, Pasadena, CA, USA, in 1987 and 1991, respectively. She is currently a Professor in the Department of Electrical Engineering and Computer Science at the University of California at Irvine, CA, USA, the Director of the UCI Power Electronics Laboratory, and a cofounder of One-Cycle Control, Inc. Dr. Smedley’s research interest includes high-efficiency dc-dc converters, high-fidelity class-D power amplifiers, fourquadrant three-phase and single-phase converters (covering PFC rectifiers, active power filters, inverters, VAR generation), switching capacitor converters, and utility-scale fault current limiters. Her technology has been integrated into commercial products spanning from audio amplifiers to V/VAR control, power grid dynamic voltage control, power quality control, renewable generation, energy storage system, mobile power, microgrid, etc. Her soft switching and regenerative clamping circuits are widely used in industry. Her current research activities include power grid modeling for high penetration renewables, solar power integration, power quality control, etc. Dr. Smedley’s work has resulted in more than 150 technical publications, more than ten US/international patents, two start-up companies, and numerous commercial applications. Dr. Smedley is a recipient of UCI Innovation Award 2005. She was selected to be a IEEE Fellow in 2008 for her contributions in high-performance switching power conversion. Her work with One-Cycle Control, Inc., won Department of the Army Achievement Award in the Pentagon in 2010.