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Jan 21, 2005 - Post-Correction of Analog-to-Digital Converters ... A mathematical analysis tool is derived, enabling the allocation of index bits to be analyzed.

Optimal Index-Bit Allocation for Dynamic Post-Correction of Analog-to-Digital Converters Henrik Lundin, Mikael Skoglund and Peter Ha¨ ndel 2005-01-21 IR–S3–SB–0503 c 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish

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ROYAL INSTITUTE OF TECHNOLOGY Department of Signals, Sensors & Systems Signal Processing S-100 44 STOCKHOLM

KUNGL TEKNISKA HÖGSKOLAN Institutionen för Signaler, Sensorer & System Signalbehandling 100 44 STOCKHOLM



Optimal Index-Bit Allocation for Dynamic Post-Correction of Analog-to-Digital Converters Henrik Lundin, Student Member, IEEE, Mikael Skoglund, Senior Member, IEEE, and Peter Händel, Senior Member, IEEE

Abstract—Signal processing methods for digital post-correction of analog-to-digital converters (ADCs) are considered. ADC errors are in general signal dependent, and in addition, they often exhibit dynamic dependence. A novel dynamic post-correction scheme based on look-up tables is proposed. In order to reduce the table size and, thus, the hardware requirements, bit-masking is introduced. This is to limit the length of the table index by deselecting index bits. At this point, the problem of which bits to use arises. A mathematical analysis tool is derived, enabling the allocation of index bits to be analyzed. This analysis tool is applied in two optimization problems, optimizing the total harmonic distortion and the signal-to-noise and distortion ratio, respectively, of a corrected ADC. The correction scheme and the optimization problems are illustrated and exemplified using experimental ADC data. The results show that the proposed correction scheme improves the performance of the ADC. They also indicate that the allocation of index bits has a significant impact on the ADC performance, motivating the analysis tool. Finally, the optimization results show that performance improvements compared with static look-up table correction can be achieved, even at a comparable table size. Index Terms—Analog-to-digital converter, calibration, dynamic correction, Hadamard transform, optimization.



HIS paper studies the problem of digital post-correction of analog-to-digital converters (ADCs). Today, ADCs are widely used in many different applications. Analog-to-digital conversion in radio receivers, for instance, impose special demands on the converter, and a trend in receiver design has been to move the digitization closer to the receiving antenna. Meanwhile, the carrier frequency as well as the bandwidth are increasing, calling for higher sampling rates and increasing analog input bandwidth. The linearity of the ADC is also a key characteristic, and the specifications of the system of which the ADC is a part, e.g., required signal-to-noise ratio, impose requirements on linearity of the converter (see, for example, [1]). Currently, the performance of all-digital receivers, also known as software radio receivers, is limited by the distortion produced by the ADC, and typical dynamic range requirements cannot be met with present commercially available converters [2], motivating the use of digital post-correction. Another rationale for applying post-correction is that in some applications it can be Manuscript received November 18, 2003; revised March 8, 2004. The associate editor coordinating the review of this paper and approving it for publication was Dr. Kenneth E. Barner. The authors are with the KTH Signals, Sensors, and Systems, Royal Institute of Technology, SE-100 44 Stockholm, Sweden (e-mail: [email protected]; [email protected]; [email protected]). Digital Object Identifier 10.1109/TSP.2004.840817

beneficial, or even unavoidable, to use a converter with inferior characteristics (e.g., a less expensive ADC). Digital post-correction can then be used to compensate for the shortcomings of the selected converter. In the ideal ADC, linearity and dynamic range is limited only by quantization noise. In practical ADCs, however, linearity errors and dynamic range deteriorations are introduced by numerous sources, such as component mismatch (e.g., nonuniform resistance ladder), aperture uncertainty (timing jitter), analog signal path distortion, charge injection [3], and comparator thermal storage of signal history [4]. Some of these result in signal dependent errors that change with the dynamic properties of the signal. Hence, the errors of the ADC are in most cases dynamic. As a natural consequence, recent research has been focused on finding means of diminishing these dynamic errors. Digital post-correction comprises signal processing methods operating on the digital side of the ADC to correct the output signal. Several methods concerning how to post-correct an ADC have been proposed [2], [5]–[10]. These methods have in common that the ADC to be corrected is treated as a closed entity, i.e., internal signals and states of the ADC are not available, and the calibration and correction methods must operate outside of the converter. In this paper, we focus on look-up table correction and related problems. In Section II, the state-of-the-art for look-up table correction is briefly reviewed, and a generalized structure for dynamic post-correction of ADCs is proposed. This novel form comprises bit masks to reduce the memory requirements by selecting fewer indexing, or addressing, bits. In the context of this correction structure, the problem of selecting indexing bits arises; in Section III, a mathematical tool for analyzing different bit allocations is derived. In Section IV, the analysis tool is employed in two examples. A post-correction system is optimized in the first example with respect to total harmonic distortion (THD) and in the second example with respect to signal-to-noise and distortion ratio (SINAD). The conclusions are drawn in Section V. II. GENERALIZED DYNAMIC POST-CORRECTION In this section, the proposed correction scheme is presented. First, however, the characteristics of an ideal ADC is briefly discussed, and some basic definitions and notations are introduced. A. Ideal ADC An ideal ADC involves two operations, sampling, and amplitude quantization, as depicted in Fig. 1. The input signal is

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Fig. 1. Model for an ideal ADC, consisting of a sampler and a quantizer.

sampled at a constant rate [in Hertz] to produce the samples , which are quantized into -bit representations . The ideal quantization mapping is defined by partitioning the real line into disjoint quantization regions so that if , then the th output is presented at the output. In a signal model of an ADC, the value will typically be set equal to the centroid of the region (often named reconstruction levels), whereas in a practical ADC, is usually a binary coded word. B. Correction Methods Different kinds of look-up table correction methods for ADCs have been proposed [5]–[10]. The basic assumption behind these is that the quantization performed in the ADC is inaccurate in the sense that the quantization regions deviate from the ideal regions. In a uniform quantizer, this corresponds to quantization regions failing to be of equal size. A look-up table correction scheme would then map every possible into a corrected state, or replacement value , output state through the use of a -size table. An alternative equivalent structure is to let the table contain correction values , . This is also which are added to the output to form a more practical way to implement a correction table since the word length of the table can be used more efficiently, under the assumption that the most significant bits need no correction. It is obvious that this scheme will produce the same corrected value for a given ADC output regardless of the signal dynamics (e.g., regardless of signal history, slope, etc.). The correction method will therefore be referred to as “static.” This is the method proposed, for example, in [5], where it was also demonstrated that static correction may improve performance for some signal frequencies, while deteriorating it for other frequencies. One way to introduce dynamics into the correction scheme is to adopt a state-space structure. The look-up table is then extended to two dimensions. At time , the current sample and the previous sample are used to address the table so that the ADC operation becomes (1) This method is referred to as state-space correction and is proposed in, for example, [7] and [9]. The correction is undoubtedly dependent on signal dynamics, since the corrected value for a sample is potentially different for different values of the previous sample .

Fig. 2. Dynamic post-correction system outline. Since the ADC errors sought to mitigate are dependent on signal history, the correction is also history dependent through the use of K delay elements. In order to reduce the index size (and thereby the memory requirements), a subset of samples are selected to address the correction table. The bit mask vector q is a mathematical construct included to facilitate the performance analysis.

As an alternative to state-space correction, the phase-plane correction, described in, for example, [8], can be used. Similar to the state-space case, the correction is in this case based on a two-dimensional (2-D) correction table, but now, it is addressed and (an estimate of) the derivative with the present sample . Addressing with higher order derivaof the ADC output tives has also been reported [10]. In [6], the method of frequency-selective tables was introduced for use with narrowband signals. The proposed method comprised a 2-D correction table addressed with the current in conjunction with a frequency region estimate sample so that the correction was dependent on the center frequency of the source signal. C. Generalized Approach The method presented in the present paper is a generalization of the look-up table correction methods listed above. The correction system is outlined in Fig. 2. In the state-space method above, the present and one-step delayed samples are used to adis used together dress a 2-D table. Here, the present sample delayed samples through to adwith dress a -dimensional table. This is illustrated in Fig. 2 address samples being concatenated together with the bits so that to form the integer index of size . With more table dimensions, a better estimate of the present error, which is assumed to be of a dynamic nature, can be produced. One major drawback, on the other hand, is that the size of the table, equating to , quickly grows out of hand with increasing . The proposed countermeasure is to reduce the address space by using only a subset of the available bits in each sample. One way to accomplish this is to apply further quantization to the delayed samples, i.e., discard the least significant bits, so that the samples are represented with less than bits resolution (similar to the method used in [10] in the context of phase-plane correction). Here, this approach is generalized to say that a number less (for than or equal to bits are used from the sample ). However, these are not necessarily the most



significant bits but can be selected from all bits of . are masked That is, some of the bits in the sample away, and the remaining bits are used for table addressing. This is illustrated in Fig. 2 with the -bit concatenated index being bit-masked into a -bit index , where is an integer less than . (or, in the trivial case, equal to) so that In the bit-masking process, the (column) vector is introduced. It has exactly ones, and the remaining entries are zero. A“1” in the th position, denoted , dictates that the th bit of should be propagated to the reduced-size index , whereas a “0” implies that the corresponding bit should be masked out. This is illustrated in Fig. 2 with “on/off” in the will be used to denote bit mask block. The notation the mapping from to through the bit mask . The proposed method reduces the memory size by using only a subset of the available bits for addressing but still takes information from up to delayed samples into account. The production of the concatenate index can be described in a framework similar to that of vector quantization (e.g., [11]). Assume that the ADC is ideal (although not necessarily uniform), thus operating as described in Fig. 1. Define the -dimensional vector of input samples (2) Now, the production of the index in Fig. 2 can be described using a partition of the -dimensional real space into disjoint sets . The partition is such that the index is produced if . This description is a straightforward extension into higher dimension of the first step in the quantizer of Fig. 1. In the light of this framework, the bit-masking is simply the result of merging the sets into larger, and obviously fewer, sets and assigning them new indices . Selecting a “good” bit mask for a given delay and a fixed is a nontrivial problem, indeed. A solution to this table size problem is one of the main contributions in this paper and is derived in Section III. Two different measures of “good,” viz. total harmonic distortion and SINAD, are employed in the application example presented in Section IV. It should be made clear at this point that the bit mask vector is a mathematical construct included to facilitate the performance analysis. In the subsequent sections, we propose analysis tools and optimization methods that are suitable to use in the design process of an ADC post-correction system. After deciding on a beneficial configuration, it is likely that in a typical implementation of the correction structure (e.g., in a digital receiver front end), the address bit selection would be hardwired. D. Calibration Prior to first use, the correction table must be calibrated. In order to be able to calibrate the table, a reference signal must be available. This reference signal is in the ideal case a perfect, infinite-resolution, sampled version of the signal applied to the ADC under test. In a practical situation, the reference signal must be estimated in some way. This is, however, not in the scope of the present paper, and several different strategies can be found in the literature [5], [9], [12], [13].

Fig. 3. Outline of calibration system. The table is built by feeding with a calibration signal and comparing a reference measurement or an estimate of the calibration signal to the ADC s (n) with the output x(n).

Optimal correction values for minimizing the mean-square error after correction have been derived in is the expected value operator taken with respect to [14] ( ). Assume that the sampled value is drawn from a stationary stochastic process with a probability density function . Then, the optimal replacement value in the mean(PDF) squared error sense is [14] (3) is a quantization region. That is, the optimal reconwhere struction value for each region is the “center of mass” of the region. A table of correction values, instead of replacement values, is obtained by subtracting the nominal output value from , with , as in every table entry so that the th entry is (3). A natural approximation to the optimal correction values (3) is to let the th table entry equal the mean of all errors produced when ; the extension to the multidimensional case is described in Section III-B. E. Experimental Results In order to facilitate the understanding of the forthcoming analysis, we illustrate the performance of the correction system with a few exemplary results. The proposed correction method has been evaluated using experimental ADC data from an Analog Devices AD876 10-bit, pipelined flash converter that is designed to operate at a sample rate of 20 million samples/s. (In the test setup used to acquire the data, the sample frequency was set to 19 972 069 Hz in order to agree with the requirements for coherent sampling [15].) The vast amount of different possible configurations when and the bit mask varying the number of delay elements makes it virtually impossible to do an exhaustive evaluation. Therefore, only a few configurations have been evaluated. For each configuration, the correction table has been calibrated according to the structure in Fig. 3, using several full-scale ( 0.45



dBFS1) sine-wave calibration signals at different frequencies. Then, the performance was evaluated at several different frequencies, separate from those used for calibration. Three performance measures have been used: spurious free dynamic range (SFDR), SINAD, and THD (all measures where evaluated according to IEEE Standard 1241 [15] using 0.45 dBFS single tones). The results are presented in Table I. The first configuration is a standard static table, using all 10 and no delay elements. The second configuration bits in is a state-space table, i.e., one delay element and 20 index bits. Configurations 3 and 4 also utilize one delay element but select and . Finally, only 10 out of the 20 available bits in configurations 5 and 6 are higher order tables with four delay elements and 10 and 18 index bits, respectively. When considering the 10-bit tables (configurations 1, 3, 4, and 5), we see that the best performance—among the considered configurations—with respect to the different measures occur at three different configurations (underlined in the table); the SFDR is maximized using configuration 5, the SINAD is maximized using configuration 4, and the THD is minimized when configuration 3 is employed. However, configuration 6 is outstanding in all three measures. In through this configuration, the 18 bits are distributed over , selecting all 10 bits from and the two most significant bits from the delayed samples. Another observation is that the improvement in SINAD is less than the improvement in SFDR and THD. This is likely an effect of the SINAD being more dependent on stochastic errors (noise) than the SFDR and THD since the latter two measure harmonic distortion and spurs often resulting from deterministic errors. From the results in Table I, we can conclude that the configuration employed has a significant impact on the performance of the corrected ADC and that the allocation of bits in the bit mask is a nontrivial problem (even though one skilled in the art may have a partial intuition on the topic). In Section III, an analysis tool for the bit allocation problem is derived. In Section IV-A, a method for calculating the optimal bit mask with respect to THD is derived. In fact, configuration 3 in Table I is the optimal bit allocation for THD at a signal frequency of 3.01 MHz for the specific ADC used, which will be shown in Section IV. Results 1Amplitude

in decibels relative to the full-scale amplitude of the ADC.


using optimization with respect to SINAD are also presented in Section IV-B. III. INDEX-BIT ALLOCATION ANALYSIS It is clear from the results presented in Section II that the choice of bit mask configuration, i.e., the allocation of ones and zeros in , has a significant effect on the corrected ADC performance. In this section, we will derive a mathematical analysis tool, based on the Hadamard transform, for the bit allocation problem. The analysis tool can, given a calibrated table indexed with bits, predict any smaller table, say , indexed with a subset of the bits and calibrated using the same calibration samples as . (In the sequel, we will use the notations for a table indexed with a “full” index and for a table indexed with and entries, respeca reduced index . The tables have tively.) This implies that the allocation analysis and the forthcoming optimization requires more memory (i.e., larger vectors) than the final reduced-size calibration and correction scheme. The analysis tool, as it is presented here, is aimed for the design process of post-correction schemes, where (of course) low memory usage is less important than in the target application. Calibration of a correction table is often time-consuming since the number of calibration samples typically is large. One of the benefits of the analysis tool is that it enables us to try and evaluate different index-bit allocation without recalibrating a new table for every configuration. The section starts out with an introduction to the Hadamard transform. This transform is subsequently used in the bit-allocais derived. Fition analysis, where a reduction matrix nally, this matrix is shown to be the key to comparing different bit-allocations. A. Hadamard Representation of a Table We begin this section by reviewing the Hadamard transform of a vector. The transform is useful because it provides an efficient means of analyzing the significance of a single bit in the vector index. Assume that is a correction table (static or multidimen(all tables sional, or more general, a vector) of size are henceforth represented as column vectors). The Hadamard transform of is defined as (4) Here, is a Sylvester-type Hadamard matrix [16] of order which is defined through

, (5) (6)

where is the Kronecker matrix product. The Kronecker , product of two matrices , of size -by- with elements -by- matrix defined through and , of size -by- , is an (see, e.g., [17]) .. .



.. .




Accordingly, the matrix is -by- square and symmetric, consisting of only 1. Furthermore, any two columns and , are orthogonal, i.e., the inner product , where denotes the transpose, and . This implies that that so that , where denotes the matrix inverse. Hence, upon premultiplying the transform , we get the vector back, or breaking it down to a (4) with single table element, we have (8) One useful feature of the Sylvester-type Hadamard matrix can be explicitly calculated from the is that each column column index . Let the natural binary representation of the inbe , with teger logical “zero” represented by 1 and logical “one” represented by 1. This is nothing but a remapping of the standard 0/1 binary representation to a 1/ 1 representation. It can then be shown that (9) Bit is the most significant bit (msb), and is the least significant bit (lsb). Thus, if we represent the table index with the , special binary representation above, we can write as in (9). This is, in fact, , written as a (nonlinear) with function of the bits in . Note that the element indices of and start at zero.

description of quantization introduced in Section II-C, it is possible to express the optimal value for the correction table entry . Equation (3) gives us the optimal replacement values in the one-dimensional case. It is straightforward to extend this exbe the joint pression to the multidimensional case. Let -dimensional vector probability density function for the . It is here assumed that the underlying signal is such that the joint PDF is independent of . Since the aim is to find the correction value, as opposed to the replacement values obtained from (3) (Section II-B explains the (from to ) is introduced. difference), the function The function is the error , which is produced by the ADC for a specific input vector or history . Ideally, this error is only the quantization error, but in a practical ADC, it is more involved. These extensions to (3) result in the equation (11) for the optimal table entries. Moving on to find the optimal value for —the th entry of a reduced size table —we can express this in a similar fashion as (11) if the range of integration is extended from to the such that . The fact that all sets union of all sets are disjoint will be used. Thus, we have


B. Deselecting Index Bits We will now use the Hadamard representation above to derive a mathematical tool for analyzing the effects of bit-masking. Let ), the table be calibrated with a transparent bit mask (all using a specific set of calibration samples. Furthermore, assume that the calibration signal applied is such that the calibration samples are distributed over all possible indices according . Thus, we to some probability mass function (PMF), say, can say that the probability of the index being equal to is . A straightforward estimate of is based on counting the number of occurrences of each index during calibration (we will see later that scaling is unimportant). of indices is defined in order to simplify the Next, a set notation in the forthcoming derivations: Definition 1: Let be a bit mask, consisting of the elements , . The bit mask defines a mapping such that consists of bits from , viz., those for which . Then, define the set (10) that is, the set of all indices that map to the same through the bit mask defined by . Each choice of defines different sets. members and It is easy to see that all sets will have exactly that all sets are disjoint. The aim is now to find a good correction value, given that . The the bit masked index is a specific integer starting point is Lloyd’s optimal value for the reconstruction values (Section II-D). By incorporating the multidimensional

Rearranging (11), we have (13) Note that , i.e., the probability of the index , and use (12) and (13) to obtain (14) provided that the denominator is nonzero; if not, the probability . We of the index being produced is zero, and we let now have, in (14), a relation between the entries of and the entries of . For notational simplicity, the explicit dependence of the set on is omitted. Under the special assumption that is constant for all , (14) reduces to (15) That is, the value for is the arithmetic mean of all for which when all have equal probability. We are now interested in comparing the original correction table (of size ) with the reduced-size table (of size ) resulting from (14). However, these two tables, represented as vec), tors, are of different sizes (except for the trivial case of so a direct, one-to-one comparison is not possible. Instead, we would like to construct a new table, say , of the same size as


, but with the special property that if . It will become clear in Section III-C why this property is desirable. In order to facilitate the bit-allocation analysis, the table should have an explicit relationship to and the bit mask . First, however, a special vector and a matrix must be introduced: Definition 2: Let be a vector consisting of the elements , . We define the vector (16)

is the element-wise division of the vectors The vector diag and (factors cancel), except where the denominator has a zero element, in which case, the corresponding element in is set to zero. This can be written using the Moore-Penrose pseudoinverse (see, e.g., [18]), here , where is a diagonal matrix, is simply the denoted , since nonzero elements replaced by their reciprocals. The following lemma concludes this discussion. ): With the assumpLemma 2 (Reduction Matrix , the vector tions of Lemma 1 and with

, and the matrix

of length




of size -by- . diag is used to denote that is a The notation diagonal matrix with the elements of the vector on the main diagonal. Now, an expression for the table (vector) as a function of and is to be derived, first in the case of equal probability, but later generalizing to arbitrary probabilities. In the equal-probawith as in (15), when . bility case, we have that The following lemma provides an explicit relationship between and in this case. Lemma 1 (Projection Matrix ): Define the column of length , where is vector be represented a positive integer. Let the integer . Let using a -bit binary representation be an integer resulting from selecting bits from , where . Denote this operation , and define the set as in (10). Then, the vector (18) is of length

, with the th entry (19)

if the




is (20)

The matrix is defined in (17). The proof is provided in the Appendix. , the Moving on to the case of arbitrary probabilities entry should be set equal to of (14). Collect all probabilities , and in the column vector note that is the th element of the vector diag . The numerator of (14) can then, by using (18) and (19), be written diag diag


and the denominator can be written in a similar fashion as (22)

is of length

, with the th entry (

) (24)

otherwise if the


matrix diag

is diag


The proof is in the discussion above. Note that the matrix does not change when the vector is scaled with a constant, i.e., we can scale the vector arbitrarily. We conclude that the matrix in (25) provides a linear relation between and , although the matrix itself is dependent on in a nonlinear way. C. Comparing Bit Masks can now be used to evaluate The reduction matrix the effects of a specific bit allocation in the bit mask of Fig. 2. Sustain the assumptions on the table being calibrated using the structure of Fig. 3, employing delay elements and a transbits. Still, is of parent bit mask, i.e., selecting all and is indexed with a -bit index . The table has size been calibrated with a specific set of calibration samples applied . to the ADC under test, with the PMF defined in Lemma 2 is a table of The vector size . However, through the averaging operation of the matrix , the table has a -fold redundancy, i.e., has unique entries. The unique entries are exactly those of only a -size table , calibrated using the same set of calibration samples but with a bit mask employed. Since every index addresses an entry in that is equal to the weighted average of all entries such that , we have from (14) and (24) that (26) In other words, and share the same address space, but addressed with yields the same values as addressed with if . Fig. 4 illustrates this relationship in a signal flowchart. The observation above can now be used to evaluate the outcome of different bit mask settings without re-calibrating a new correction table. For example, if a state-space table (that is, and ) has been calibrated, we can now mimic a static table simply by setting the bits in corresponding to the “previous sample” to zero in (25) and (26). In fact,



is the discrete Fourier transform (DFT) of the where vector , evaluated at the th harmonic of the fundamental frequency . In order to avoid spectral leakage in the DFT, should be selected to coincide with a bin frequency , . Normally, the lowest nine harmonics , and the aliased counterpart of those are considered are added in (27); explicit equations for calculating the aliased harmonics are found in [15]. The THD can be expressed in a matrix notation. Let the row be vector (28) and form a matrix

as (29)

~. Fig. 4. Relationship between the 2 -size table f and the 2 -size table e

we can mimic any table by using (26), as long as is indexed with a subset of the bits used to index . In the next section, we will give two examples of how to use the reduction matrix in order to optimize the bit mask.

where write

denotes complex conjugate transpose. Then, we can

(30) and on inserting (30) and (29) in (27), we get



IV. APPLICATIONS OF THE BIT ALLOCATION ANALYSIS The bit reduction matrix is used to compare the impact of different bit masks . Since different choices of bit masks can be effected simply by altering the vector in (25), it is possible to pose optimization problems where some performance criterion is optimized with respect to . Two such examples are given in the following subsections; in the first example, the THD is the criterion, and in the second example, the SINAD is employed instead. In both cases, we constrain the set of feasible solutions to bit masks having a certain number of ones, viz. ones. This constraint is relevant due to the aforementioned problem of memory size growing exponentially with the index length. Through the optimization problems derived below, we can give an answer to the question: Given a maximum index length or memory size , which index bits should be selected? A. Optimizing the THD The THD is defined in [15, Sec.]. The ADC under test should be exercised with a spectrally pure, large amplitude , with (near full-scale) sine wave, and chosen so that the signal is centered within and spans a major part of the ADCs analog input range. The fundamental , and the initial phase is arbitrary. frequency is in A record of successive samples are collected in a vector . The THD is defined as


This is the THD of the uncorrected ADC at the frequency . Assume now that a correction table has been calibrated as described in Section III-C, i.e., employing delay elements and a transparent bit mask. The correction sequence for the recorded output can also be described in a matrix notation. Assign a of size by . Each row of corselection matrix responds to a sample time index , and each column corre(row and column indices sponds to a correction table entry start at 0); if the table address for the time index is , of is set to one, and the remaining entries then the element in the same row are zero. That is, the matrix selects the appropriate correction term for each time . The correction for the . entire sequence can thus be written In order to obtain a description for the sample vector conforming with the selection matrix notation above, a column vector of size is introduced. Since the employed bit mask is transparent, each index is uniquely decodable to an ADC output level . Thus, if the index corresponds to the output level , then let so that the vector can be written . An example is appropriate here. If is a static table, , then is just the vector of all possible ADC output i.e., to , without repetitions. In the state-space levels, from case, when , then is still composed of all ADC output levels, but this time with each level repeated times; therefore, for all indices corresponding to the “present sample” being . equal to , it holds that Now, we can write the corrected ADC output corresponding to the record in a new vector as

(27) (32)



and, inserting (32) into (31), the expression THD (33) for the resulting THD after correction is obtained. Having established a matrix expression for the THD after cor-dimensional, full-size indexed correcrection with a tion table , we are now interested in how the THD is affected when a nontransparent bit mask is employed. Using the results of Section III, the vector in (33) should be replaced with in order to evaluate the effect of rethe vector ducing the address space. That is, the THD after correction with a table calibrated with the same set of calibration signals as , but this time with a specific bit mask (see Figs. 2 and 3), is THD

Fig. 5. Exemplary optimization results for THD. Each row corresponds to a specific choice of , and the dots indicates which positions in the bit mask q should be set to “1.” The results are obtained for f = 3:01 MHz.

(34) For example, we can evaluate the resulting THD after correction with a state-space table versus that of a static table, simply by setting the appropriate bit mask in (34). The reduction matrix provides us with an explicit relationship between the original and a reduced table. Without this knowledge, we would have to resort to recalibrating a new correction table and re-evaluate the THD for each bit mask configuration we would like to test; in many situations, this would be a very laborious task because of the large amount of calibration samples. The function in (34) is the cost function to minimize. The zeros is the only constraint is that a bit mask of ones and allowed solution. The optimization problem for minimizing the THD becomes

Fig. 6. Resulting THD after correction, optimized for and evaluated at f =

3:01 MHz, as a function of table index size .




where the square root, being a monotonically increasing function, and the scaling have been omitted for simplicity. 1) Exemplary Results for THD: The optimization problem (35) has been solved and evaluated for an exemplary scenario. The same experimental data as in Section II-E has been used. A state-space table is considered in this example. The table, which is denoted , is indexed using an index building structure with ) and a transparent bit mask, so one delay element (i.e., that the index is bits long, and hence, consists of entries. The table is calibrated with a large number of different signals, all near full-scale ( 0.45 ). dBFS) sinewaves but each with a unique frequency in (0, The vector represents the number of times each entry in was updated during the calibration. is selected, and a 0.45 Next, an optimization frequency samples is taken; in dBFS sine-wave record of the results below, the frequency is chosen. and are formed, and the optimization The matrices (the solutions problem (35) is solved for all integers and are trivial, viz. set to all zeros and all for ones, respectively). Fig. 5 illustrates the optimal bit masks for

different choices of ; each row corresponds to a specific , and the dots indicate which of the positions in the bit mask should be set to “1” or which of the original 20 bits to use in a -bit index . For example, if a 10-bit index is desired, Fig. 5 suggests that the six most significant bits from the present , i.e., bits 10 through 5, with 10 being the msb, sample should be selected, together with bits 8, 7, 5, and 4 from the . These 10 bits form the index used previous sample entries. Note that to address the table of size Fig. 5 illustrates the results for a specific ADC at a specific frequency and should not be taken to be optimal in general. In Fig. 6, the resulting THD after correction with a -bit table, indexed with the optimal choice of index bits as suggested in Fig. 5, is plotted. The THD is evaluated at the frequency , i.e., the same frequency as the one for which the index was optimized. Somewhat surprisingly, the THD is not minimal at bits but, rather, at 15 bits. This phenomenon is due to the fact that in our experiment, the amount of calibration data is constant so that a smaller table will have more calibration data per table entry. For example, a table indexed with 15 bits, thus entries, will have 32 times more calibration data per having entry compared with a table of size . The conclusion is that




Fig. 7. THD for the uncorrected ADC (“ ”), THD after correction with a static 10-bit table (o), and THD after correction with a 10-bit table optimized : MHz (solid, no marker). for the frequency f

= 3 01

given the fixed amount of calibration data, Fig. 6 suggests that MHz improves the performance in terms of THD at when is reduced from 20 to 15 but then deteriorates as is further reduced. In Fig. 7, the evaluation frequency is altered. The three curves show THD for the uncorrected ADC, THD after correction with a static 10-bit table, and THD after correction with a 10-bit table MHz. Although the static optimized for the frequency table performs equally well as, or even better than the THD optimized table at many frequencies, this does not refute the allocation analysis and the optimization methods. Remember that our optimization goal was to optimize the THD at the frequency 3.01 MHz. We see that near that frequency, the optimized table outperforms the static table. Thus, by clever selection of the index bits, we can gain a few decibels in THD without increasing the table size. B. Optimizing the SINAD In [19] and [20], another criterion was used in conjunction with the bit allocation analysis derived above, namely, the SINAD. It was shown that choosing the optimal bit allocation with respect to the SINAD is equivalent to solving the problem



diag depends on The diagonal weighting matrix the distribution of the signal for which the bit mask should be equal the distribution over the table optimized. By letting of one or several full-scale sinusoids, we obtain the optimal bit mask with respect to the SINAD evaluated using the selected sinusoids. 1) Exemplary Results for SINAD: The optimization problem (36) has also been solved and evaluated for a scenario with experimental ADC data. The ADC data is the same as in the results presented in the previous sections. A state-space delay element and a table , addressed as before with transparent bit mask, is calibrated using several 0.45 dBFS

Fig. 8. Exemplary optimization results for SINAD. Each row corresponds to a specific choice of , and the dots indicates which positions in the bit mask q should be set to “1.”

Fig. 9. Resulting SINAD after correction, evaluated at f function of table index size .

= 3:01 MHz, as a

sine-waves at different frequencies; the vector is the coris set equal responding distribution vector. The weighting to so that the SINAD is optimized over all frequencies for which the table was calibrated. The purpose of this is to achieve an optimization valid in a wide frequency range. The optimization problem (36) is solved for all integers (as before, the solutions for and are trivial). The optimal bit masks are illustrated in Fig. 8. The plot should be interpreted the same way as Fig. 5; each row corresponds to a specific choice of , and the dots indicate which bits to use in a -bit index . A basic observation is that the results in Fig. 5 and Fig. 8 are similar but not equal. Hence, the optimal bit allocations are different, depending on which optimality criterion is applied. MHz The SINAD was evaluated at the frequency for different values of . In Fig. 9, we see that the performance only deteriorates slightly when is reduced as low as 3. However, this can again be an effect of the constant number of calibration samples, as discussed in Section IV-A1. Finally, Fig. 10 shows the SINAD after correction with an optimized 10-bit table, compared with the SINAD after correction with a 10-bit static table and the uncorrected SINAD. It is clear



trary, this is one purpose of the analysis tool. Second, the analysis framework can be used to construct suboptimal design algorithms based on, e.g., recursive extension to higher dimensions or approximations of the full-size table . Third, the theory presented in the present paper constitutes a basis for understanding the behavior of post-correction look-up tables. APPENDIX PROOF OF LEMMA 1 In order to simplify the notation, define the iterated Kronecker products (37)


Fig. 10. SINAD for the uncorrected ADC (“ ”), SINAD after correction with (o) a static 10-bit table and SINAD after correction with (solid, no marker) a 10-bit optimized table.

from the results that in the higher frequencies, the optimized table performs better than the static table, and the difference is significant (approximately 2 dB). In the lower frequencies, on the other hand, the static table actually outperforms the 10-bit optimized table, but the difference is small (less than 1 dB). V. CONCLUSIONS A generalized digital post-correction for ADCs based on look-up tables has been proposed and evaluated. The correction scheme comprises a bit mask that is used to select specific index bits to address the correction table. Selecting a good bit mask was pointed out to be a crucial and nontrivial problem. A mathematical analysis tool, based on the Hadamard transform, for analyzing the effect of different bit mask choices was introduced and is one of the main contributions of the present paper. Two applications of the analysis tool were presented employing two different optimality criteria: THD and SINAD. We saw that the optimal solutions differed for the two criteria and that a mix of index bits from the present sample and the one-step delayed sample was beneficial for the specific converter considered. We believe that the analysis tool introduced here can be applied in other cost functions using other criteria. For instance, by modifying the in (36), we can achieve optimization with weighting matrix respect to other signal distributions so that the bit-allocation is optimized for a certain type or family of input signals. Optimizing with respect to SFDR is another possible application. Furthermore, the addressing structure of Fig. 2 can be altered to include phase-plane correction simply by letting fixed-point derivative estimates append the concatenate index . It was pointed out that the full-size table was needed to optimize the bit mask for a reduced size table . This fact makes the optimization methods, as they are presented here, unsuitable for implementationinanapplicationwherethememoryisscarce.The derived analysis tool can, however, be very useful in other situations.First,theoptimizationmethodsderivedaboveareapplicable in the design stage, where a larger memory is available. The large memory requirements of the optimization methods, of course, do not prevent the results of the optimization, i.e., the optimized bit mask, from being used in a low-memory application. On the con-

through of suitable dimensions. of the matrices Note that the Kronecker product is not commutative, e.g., in general. Assume now that one bit, say the th bit, is deselected in the -bit index , using a bit mask (cf. Fig. 2), i.e., otherwise.


Let be a vector of size with a Hadamard transform . With bits, different indices exist, but with one bit deselected, the indices will be partitioned into pairs; both indices in one pair are indistinguishable when the th bit is masked, that is, one pair consists of the two indices such that . Denote one such pair . Furthermore, be the 1-representation (cf Section III) of . Then, the let and is average of the two table entries

(39) where we get




The last equality in (40) holds because the only difference between and lies in the bit masked away by . Now, by using Definition 2 and inserting (40) in (39), we have (41) and, thus, for the entire table, i.e., for all we obtain


[7] F. H. Irons, D. M. Hummels, and S. P. Kennedy, “Improved compensation for analog-to-digital converters,” IEEE Trans. Circuits Syst., vol. 38, no. 8, pp. 958–961, Aug. 1991. [8] D. Moulin, “Real-time equalization of A/D converter nonlinearities,” in Proc. IEEE Int. Symp. Circuits Syst., Portland, OR, 1989, pp. 262–267. [9] J. Tsimbinos and K. V. Lever, “Improved error-table compensation of A/D converters,” Proc. Inst. Elect. Eng.—Circuits, Devices Syst., vol. 144, no. 6, pp. 343–349, Dec. 1997. [10] J. P. Deyst, J. J. Vytal, P. R. Blasche, and W. M. Siebert, “Wideband distortion compensation for bipolar flash analog-to-digital converters,” in Proc. 9th IEEE Instrum. Measurement Technol. Conf., New York, 1992, pp. 290–294. [11] A. Gersho and R. M. Gray, Vector Quantization and Signal Compression. Boston, MA: Kluwer, 1992. [12] J. Elbornsson, “Analysis, Estimation and Compensation of Mismatch Effects in A/D Converters,” Ph.D. dissertation, Linköping Univ., Linköping, Sweden, Apr. 2003. [13] H. Lundin, M. Skoglund, and P. Händel, “On external calibration of analog-to-digital converters,” in Proc. IEEE Workshop Statist. Signal Process., Singapore, Aug. 2001, pp. 377–380. [14] S. P. Lloyd, “Least squares quantization in PCM,” IEEE Trans. Inf. Theory, vol. IT-28, no. 2, pp. 129–137, Mar. 1982. [15] IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters, IEEE Std. 1241, 2000. [16] R. K. Yarlagadda and J. E. Hershey, Hadamard Matrix Analysis and Synthesis. Boston, MA: Kluwer, 1997. [17] R. A. Horn and C. R. Johnson, Topics in Matrix Analysis. Cambridge, U.K.: Cambridge Univ. Press, 1991. [18] G. H. Golub and C. F. Van Loan, Matrix Computations, 3rd ed. Baltimore, MD: Johns Hopkins Univ. Press, 1996. [19] H. Lundin, “Post-Correction of Analog-to-Digital Converters,” Licentiate thesis TRITA-S3-SB-0324, Royal Inst. Technol. (KTH), Stockholm, Sweden, May 2003. [20] H. Lundin, M. Skoglund, and P. Händel, “A criterion for optimizing bitreduced post-correction of AD converters,” IEEE Trans. Instrum. Meas., vol. 43, no. 4, pp. 1159–1166, Aug. 2004.

(42) This result is easily generalized to a bit mask where bits have been deselected. Through repeated use of (42) with bit masks deselecting one bit each, and utilizing the fact that , it can be shown that (42) holds for bit masks deselecting an arbitrary number of bits . is in fact an orthogonal projection matrix, The matrix and . since

Henrik Lundin (S’01) was born in Stockholm, Sweden, in 1976. He received the M.Sc. degree in electrical engineering from the Royal Institute of Technology (KTH), Stockholm, in 2000. In 2001, he joined the Department of Signals, Sensors, and Systems, KTH, from which he received the Lic.Eng. degree in 2003 and where he is currently pursuing the Ph.D. degree in signal processing. His research interests include signal processing and analog-to-digital conversion.

REFERENCES [1] A. K. Salkintzis, H. Nie, and P. T. Mathiopoulos, “ADC and DSP challenges in the development of software radio base stations,” IEEE Pers. Commun. Mag., vol. 6, no. 4, pp. 47–55, Aug. 1999. [2] D. Hummels, “Performance improvement of all-digital wide-bandwidth receivers by linearization of ADCs and DACs,” Measurement, vol. 31, no. 1, pp. 35–45, Jan. 2002. [3] P. G. A. Jespers, Integrated Converters. Oxford, U.K.: Oxford Univ. Press, 2001. [4] C. E. Woodward, K. H. Konkle, and M. L. Naiman, “A monolithic voltage-comparator array for A/D converters,” IEEE J. Solid-State Circuits, vol. SC-10, no. 6, pp. 392–399, Dec. 1975. [5] P. Händel, M. Skoglund, and M. Pettersson, “A calibration scheme for imperfect quantizers,” IEEE Trans. Instrum. Meas., vol. 49, pp. 1063–1068, Oct. 2000. [6] H. Lundin, T. Andersson, M. Skoglund, and P. Händel, “Analog-todigital converter error correction using frequency selective tables,” in RadioVetenskap och Kommunikation (RVK), Stockholm, Sweden, June 2002, pp. 487–490.

Mikael Skoglund (S’93–M’97–SM’04) received the Ph.D. degree in 1997 from Chalmers University of Technology, Göteborg, Sweden. In 1997, he joined the Department of Signals, Sensors, and Systems, the Royal Institute of Technology (KTH), Stockholm, Sweden. At KTH, he held various positions until he was appointed Professor of communication theory in October 2003. His research interests are in information theory, communications, and detection and estimation. He has worked on problems in vector quantization, combined source-channel coding, coding for wireless communications, space-time coding, and statistical signal processing, and he has authored some 60 (journal and conference) papers in these areas. Dr. Skoglund presently serves as an Associate Editor for source/channel coding for the IEEE TRANSACTIONS ON COMMUNICATIONS.


Peter Händel (S’88–M’94–SM’98) received the M.Sc. degree in engineering physics and the Lic.Eng. and Ph.D. degrees in automatic control, all from the Department of Technology, Uppsala University, Uppsala, Sweden, in 1987, 1991, and 1993, respectively. From 1987 to 1988, he was a Research Assistant at The Svedberg Laboratory, Uppsala University. Between 1988 and 1993, he was a Teaching and Research Assistant at the Systems and Control Group, Uppsala University. In 1996, he was appointed to the position of Docent at Uppsala University. From 1993 to 1997, he was with the Research and Development Division, Ericsson Radio Systems AB, Kista, Sweden. From 1996 to 1997, he was a Visiting Scholar at the Signal Processing Laboratory, Tampere University of Technology, Tampere, Finland, where, in 1998, he was appointed to the position of Docent. Since August 1997, he has been an Associate Professor with the Department of Signals, Sensors, and Systems, Royal Institute of Technology (KTH), Stockholm, Sweden, where he also is Vice Head of Department and Acting Head of the Signal Processing Group. He is the Director of the Electrical Engineering Program. He has conducted research in a wide area including design and analysis of digital filters and adaptive filters, measurement and estimation theory (especially spatial and temporal frequency estimation), system identification, speech processing, and analog-todigital conversion. Dr. Händel is a former President of the IEEE Finland joint Signal Processing and Circuits and Systems Chapter and has been Vice President of the IEEE Sweden Signal Processing Chapter since 2001. He is a registered engineer (EUR ING) and has published some 30 journal articles, 40 conference papers, and holds ten patents. He currently serves as an Associate Editor for the IEEE TRANSACTIONS ON SIGNAL PROCESSING and is an editorial board member for the EURASIP Journal on Applied Signal Processing.


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