Optimization of Au-Free Ohmic Contact Based on the ... - IEEE Xplore

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 2, FEBRUARY 2018

Optimization of Au-Free Ohmic Contact Based on the Gate-First Double-Metal AlGaN/GaN MIS-HEMTs and SBDs Process Hui Sun , Meihua Liu, Peng Liu, Xinnan Lin, Member, IEEE , Jianguo Chen, Maojun Wang , Member, IEEE , and Dongmin Chen

Abstract — The compatibility of Au-free (Ti/Al/Ti/TiN) ohmic contacts in the gate-first double-metal (GFDM) process for AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) and Schottky barrier diodes (SBDs) on the same 150-mm wafer was investigated and discussed for the first time, including contact pretreatments, Al diffusion in dielectric layers, and vias (contact windows between two metal layers) etching conditions. All of these steps are crucial to ohmic contacts as well as overall AlGaN/GaN device fabrication process. With the optimized ohmic contacts steps, not only an extremely low ohmic contact resistance (RC ) value of 1.07 · mm but also an excellent uniformity on the 150-mm wafer was obtained. The performance and uniformity of the MIS-HEMTs and SBDs based on the optimized GFDM process were also discussed. Index Terms — Au free, gate-first double metal (GFDM), high-electron-mobility transistors (HEMTs), ohmic contact, Schottky barrier diodes (SBDs), Si compatibility.

I. I NTRODUCTION HE excellent material properties of GaN, such as wide bandgap, large critical electric field, and outstanding thermal conductivity, enable GaN devices to operate under extreme conditions with high power density, and enhanced power efficiency exceeding the theoretical limit of similar

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Manuscript received September 30, 2017; revised November 16, 2017; accepted November 23, 2017. Date of publication December 12, 2017; date of current version January 22, 2018. This work was supported in part by the Collaborative Innovation Program between the School of Innovation and Entrepreneurship, Peking University and the Founder Group, in part by the Shenzhen Key Lab Project under Grant ZDSYS20170303140513705, and in part by the National Natural Science Foundation of China under Grant 61774002 and Grant 11634002. The review of this paper was arranged by Editor K. J. Chen. (Corresponding author: Maojun Wang.) H. Sun, P. Liu, and D. Chen are with the Academy for Advanced Interdisciplinary Studies, Peking University, Beijing 100871, China (e-mail: [email protected]). M. Liu and X. Lin are with the Key Laboratory of Advanced Electron Device and Integration, School of Electronic and Computer Engineering, Peking University Shenzhen Graduate School, Shenzhen 518055, China (e-mail: [email protected]). J. Chen is with the Founder Microelectronics International Corporation, Ltd., Shenzhen 518116, China. M. Wang is with the Institute of Microelectronics, Peking University, Beijing 100871, China (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2017.2778072

Si devices [1]. GaN power devices also help reduce conduction and switching losses, thereby providing higher efficiency in electronic systems [2]. At present, the dominant platform for developing commercial GaN power electronic devices is based on lateral heterojunctions (e.g., AlGaN/GaN) grown on large-size, low-cost silicon substrates. The ability to manufacture GaN-on-Si power devices in existing fully depreciated 6- or 8-in silicon fabrication facilities offers further cost competitiveness to the GaN-on-Si power technology [3]–[5]. Low-resistance ohmic contacts are essential for the efficient operation of high-power electronic devices, in particular to achieve high current densities, high extrinsic gain, and low Joule heating loss to allow high-temperature operation [6]. In recent years, different Au-based [6], [7] and Au-free [8]–[10] ohmic contact metal stacks have been investigated systematically, including contact windows pretreatments, metal thickness, annealing conditions, to lower the RC on AlGaN/GaN heterostructures. However, the research for now only focus on the ohmic contacts itself, ignoring the compatibility to the overall process of AlGaN/GaN HEMTs and Schottky barrier diodes (SBDs), especially for multilayermetal devices. In this paper, we proposed a gate-first-double-metal (GFDM) process, which allowed AlGaN/GaN SBDs and MIS-HEMTs to be fabricated together on the same wafer and enabled multidevices integration. Based on the process, the compatibility of Au-free (Ti/Al/Ti/TiN) ohmic contacts was investigated systematically by analyzing contacts pretreatments, Al diffusion in dielectric layers, and vias etching conditions. II. E XPERIMENTAL D ETAILS The AlGaN/GaN heterostructure used in this paper was grown by the metal–organic chemical vapor deposition on 150mm silicon (111) substrate. The reported devices were a GaN HEMT with insulated gate structure and a GaN SBD fabricated in a 6-in silicon foundry, as shown in Fig. 1(a) and (b). The commercial AlGaN/GaN epilayer consisted of a 4-μm GaN buffer layer, a 300-nm GaN channel layer, a 25-nm Al0.25 Ga0.75 N barrier layer, and a 2-nm GaN cap layer for improving surface morphology. The device fabrication started with the deposition of a 30-nm-thick Si3 N4 layer using low-pressure chemical vapor

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SUN et al.: OPTIMIZATION OF Au-FREE OHMIC CONTACT

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Fig. 1. Schematic cross sections of (a) AlGaN/GaN MIS-HEMTs and (b) AlGaN/GaN SBDs on the 150-mm Si substrate.

deposition (LPCVD). The Si3 N4 layer acts simultaneously as the surface passivation layer [11] and the gate insulator. Then, the mesa structure was formed by Cl2 /BCl3 plasma etching at a depth of 300 nm. After mesa isolation, a 500-nm SiO2 layer was deposited by plasma-enhanced chemical vapor deposition (PECVD), which was used for isolation passivation and planarization. The gate windows were opened by SF6 plasma dry etching and buffered HF wet etching, successively. The SiO2 layer was etched to 50 nm by SF6 plasma before shifting the wafer to the buffered HF solution. The dry etching was controlled by time with about ±10% deviation, and the buffered HF wet etching was self-terminated at the LPCVDgrown Si3 N4 surface. After that, the Si3 N4 , GaN cap, and partial AlGaN layer (16 nm) in the SBDs anodes areas were etched with a second photolithography, and the window is slightly smaller than the one for SiO2 etching. And then, TiN for gate in MIS-HEMTs and Schottky metal in SBDs was deposited by physical vapor deposition method. The source and drain contact areas were recess etched by Cl2 /BCl3 , SF6 , and Cl2 /BCl3 plasma chronologically, followed by wet clean treatment and metallization using a gold-free metal scheme. The sources, drains, gates, and anodes metals were patterned by Cl2 /BCl3 plasma etching with the one mask. Ohmic contacts were formed by rapid thermal annealing at 850 °C for 45 s in a nitrogen atmosphere. Finally, the devices were passivated by PECVD-grown SiO2 /Si3 N4 /SiO2 stacks [12] and connected to the pad metal though vias etched by CHF3 -based plasma.

Fig. 2. Schematic (a) overview of TLM structure and (b) cross section of two adjacent pads. TABLE I Si CMOS C OMPATIBLE C ONTACT P RETREATMENTS

III. R ESULTS AND D ISCUSSION As described above, the fabrication of ohmic contacts is related to several steps in the overall MIS-HEMTs and SBDs process. Thus, it is necessary to take all the steps into account during optimizing the ohmic contacts. The RC is assessed by the typical transfer length method (TLM) [13]. Fig. 2(a) and (b) shows the TLM structure fabricated together with the MIS-HEMTs and SBDs on the same wafer.

A. Contact Pretreatments Generally, prior to metal deposition, one or more treatments can be carried out on the AlGaN/GaN heterostructures to clean the contact areas [8], [9], [14]. To ascertain the influence of pretreatments on the ohmic contacts and the GFDM process, several groups of experiments on pretreatments based on the Si CMOS compatible solutions and methods were performed, as shown in Table I. I –V characteristics of adjacent two

Fig. 3. I–V characteristics of adjacent two pads in TLM structures with different pretreatments.

pads in TLM structures with different pretreatments are shown in Fig. 3. It is clearly that the samples cleaned by HCl, HF, and SC2 (H2 O:H2 O2 :HCl = 6:1:1) solutions show better performance than that with the other treatments. However, HCl and HF are unfriendly to gate (anode) metal (TiN), which cause plenty of pinholes on the TiN surface, as shown in Fig. 4(a) and (b). The pinholes have negative impacts on the adhesiveness between TiN and upper metals (Ti/Al/Ti/TiN), thus, deteriorating the gate control capacity and anode current conduction in MIS-HEMTs and SBDs, respectively.

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Fig. 4. SEM photogrpahs of TiN surface (a) without any treatment or cleaned by SC2 and (b) cleaned by HCl or HF solution.

Fig. 6. Schematic ohmic contacts (a) as opened, (b) treated by HF solution for 20 s, (c) treated by HF solution for 20 s and SC1 solution for 300 s, and (d) treated by HF solution for 20 s, SC1 solution for 300 s, and SC2 solution for 300 s in succession.

Fig. 5. I–V characteristics of ohmic contacts between PAD1 and PAD2 treated by HCl and HF/SC1/SC2 solutions. Inset shows the SEM picture of the TiN surface treated by HF/SC1/SC2 solutions.

Although SC2 solution is damage free to TiN, the current of the ohmic contact treated by SC2 is 20% lower than that treated by HCl, which meant almost 20% higher for RC . In order to overcome the contradiction between the lower RC and free damage on the TiN surface, a novel treatment method using HF, SC1, and SC2 solutions in sequence was proposed, which referenced Si CMOS cleaning technology, as shown in Table I. Because of shorter HF treatment time as well as lower concentration of SC1 (NH4 OH 12.5%) and SC2 (HCl 14.3%) solutions, the TiN is only slightly damaged, as shown in Fig. 5. Meanwhile, it is obvious that the contact treated by the novel method is better than that by HCl solution. The reason for such optimization in ohmic contacts can be assumed, as shown in Fig. 6. There is a mass of pollutants on the surface of contact after the ohmic window is opened, including metal particles (Al, Ti etc., coming from etching equipment), organics (coming from photoresist), and oxide particles (created during photoresist removing by oxygen plasma and other oxidation processes). After treated by HF for 20 s, the oxide particles could be removed as well as metal particles partly. Afterward, with the treatments by SC1 and SC2 solutions orderly, the organics and metal particles would be cleaned up completely [15]. Finally, an excellent contact surface condition would be obtained. Of course, the assumptions need to be verified by deeper research and appropriate experiments.

B. Al Diffusion Through the Dielectric/Passivation Layers At present, the influences of Al thickness and Ti/Al ratio on ohmic contacts have been investigated adequately in

Ti/Al-based ohmic metal systems [8], [16], [17]. However, metal Al with melting point of 660 °C is easy to diffuse through dielectric layers and interfaces of dielectric/bulk and dielectric/dielectric, which may cause leakage current and even short out in devices. Although, the problems of Al diffusion in silicon devices have been studied systematically [18], [19], the research related to the issues in GaN devices and processes is still absent. In this paper, the Al diffusion problem was first proposed and discussed in GaN devices and processes using the GFDM process as an example. In the GFDM process, the Si3 N4 and SiO2 layers are deposited before ohmic annealing. The PECVD-grown SiO2 layer with excellent ductility is used to fill the etched isolation areas, which is useful to planarize the high steps as discussed in the experimental section. Therefore, when it comes to the Al diffusion in the GFDM process, attention should be paid to the Al diffusion though the SiO2 layer, Si3 N4 layer, and the interfaces of Si3 N4 /SiO2 and Si3 N4 /(Al)GaN. It is the common sense that the Si3 N4 dielectric material is compacted enough, especially for LPCVD-grown Si3 N4 . Thus, the metal Al diffusion in Si3 N4 layer is much slighter than that in SiO2 layer. Therefore, in this paper, the Al diffusion problem was focused on the Al diffusion in the SiO2 layer and the interface of Si3 N4 /SiO2 , which were defined as diffusion through SiO2 layer in general. Fig. 7 shows the SEM photographs of the devices’ surface morphology with metal Ti (25 nm) and metal Al (120 nm) annealing at 850 °C for 90 s. It is obvious that the metal Al diffuses in the SiO2 layer seriously (for better observation, Ti, and TiN at the top of the metal scheme were not deposited). The largest diffusion distance is 5.8 μm and maximum diffusion coefficient is 6.44 × 10−8 cm2 · s−1 , as shown in Fig. 7(b). This is very dangerous for AlGaN/GaN MIS-HEMTs, because the sizes between gates and sources are usually less than 5 μm. For better understanding the Al diffusion behaviors in SiO2 layer, samples with different L GS were fabricated by the


Fig. 7. SEM photographs of Al diffusion through SiO2 layers in different viewpoints. Note that photographs (b)–(d) were enlarged from red circle line marked in (a).

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process (data not shown here). Therefore, the annealing time should be controlled appropriately no more than 45 s when design MIS-HEMTs based on the GFDM process. However, L GS = 5 μm is a large value for MIS-HEMT design since it can degrade the ON-resistance (RON ). Therefore, effective methods ought to be proposed to realize a small L GS in MIS-HEMTs based on the GFDM process. Now, barrier recessed ohmic contacts (low annealing temperature) [8], [9], cap-gate structure (with Si3 N4 sidewall between gate and source) [20], and densification of the PECVD-grown SiO2 are verified useful to help reduce the demission of L GS . Of course, the Al diffusion would be mitigated and avoided when the SiO2 layer is replaced by other dielectric layers, such as PECVD-grown Si3 N4 . However, as described above, SiO2 layer is the best choice to planarize the high steps at isolation areas for the non-implantation process. Furthermore, the results of this paper reveal us a latent problem in GaN devices and process design, which is usually neglected by researchers.

C. Vias Etching

Fig. 8. Breakdown performance between gates and sources of the samples annealing at different conditions.

GFDM process using the same Ti/Al/Ti/TiN (25 nm/120 nm/ 20 nm/20 nm) ohmic metal scheme. The samples were annealed at different temperature and time conditions, respectively. The Al diffusion characteristics are assessed by breakdown performance between gates and sources in the samples. As shown in Fig. 8, the samples with the L GS of 5 and 10 μm behave the same breakdown performance after annealing at 850° for 45 s, which means that the size of L GS = 5 μm is enough for the MIS-HEMTs to avoid Al diffusing punch through the area between gates and sources under such annealing condition, and the 35.5 V (defined at current of 100 μA) is the breakdown voltage of the 30-nm LPCVD-grown Si3 N4 . The samples with L GS of 5-μm annealing at 850 °C for 90 s and 900 °C for 45 s show the same breakdown voltage of 11.5 V, which is far less than 35.5 V. This suggests that high-temperature and long-time annealing are both hazardous for GaN MIS-HEMTs with L GS of 5 μm. And it is clearly shown in Fig. 8 that when annealing at the temperature of 850 °C, 60 s begins to be a dangerous time for GaN MIS-HEMTs. As is well known, 850 °C is the most widely used annealing temperature for nonrecessed Ti/Al-based ohmic contacts on AlGaN/GaN heterostructures [17]. And it has also been verified to be the best annealing temperature in our

Vias are the necessities for interconnections. To date, almost all of the attentions are paid to the steps before the first metal patterned. However, for future multidevice integration, steps after the first metal patterned should also be investigated and optimized carefully, especially, the step of vias etching process, which is directly related to ohmic metal and gates (anodes) metal. In the Ti/Al/Ti/TiN-based ohmic metal systems, the care should be taken for TiN layer on the top of the ohmic metal scheme during vias etching. Typically, Ti/Al/Ti have reactions between each other, forming alloy of Ti/Al3 , thus decreasing the sheet resistance of the metal stacks. However, TiN does not take part in the alloy reaction and stand still there independently [21]. Therefore, there is a phase boundary between TiAl3 alloy and TiN, which causes a high contact resistance between TiAl3 and TiN. In order to destroy the phase boundary, the TiN should better be removed during the vias etching. Moreover, vias are usually etched by plasma in inductively coupled plasma (ICP) or reactive ion etching (RIE) equipment systems, in which the plasma etching could not stop automatically at the surface of TiN. Therefore, the TiN would be bombarded by the high energy plasma more or less, resulting in a quite rough morphology of vias, as shown in Fig. 9. Fig. 9(a) shows the SEM morphology of the vias after dry etching and cleaning. The TiN thickness was typical 60 nm under the vias. Although, longer etching time and cleaning time were adopted, the morphology is still unsatisfactory with many particles, as shown in Fig. 9(b). Given these results, the thickness of the TiN layer was scaled down to 20 nm, so that the TiN could be fully removed by physical bombarding of plasma and air exhausting in the ICP or RIE equipment. The etching morphology of the vias with 20-nm TiN is smooth enough for the interconnection metal (pad metal) deposition, as shown in Fig. 9(c). To explain the impacts of the vias’ morphologies on ohmic contacts, the RC after vias etched and pad metal patterned was investigated as well. Three samples were fabricated by the GFDM process with the TiN thickness of 20, 40, and 60 nm, respectively.

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Fig. 9. SEM photographs of vias’ etching morphology with (a) TiN 60 nm, (b) TiN 60 nm etched and cleaned for longer time, and (c) TiN 20 nm.

Fig. 11. I–V characteristics of AlGaN/GaN MIS-HEMTs (LGS = 5 µm, LGD = 20 µm, LG = 1.5 µm, and W = 1 mm) and SBDs (LSC = 25 µm, LAC = 10 µm, LT = 1.5 µm, and W = 1 mm). (a) Transfer curves of the MIS-HEMTs on different wafer positions. (b) Output curves of the MIS-HEMT on the center of the wafer. (c) Forward current curves of the SBDs on different wafer positions. (d) Reverse characteristics of the SBDs on different wafer positions.

Fig. 10. TLM curves of ohmic contacts with different TiN thicknesses. TABLE II PARAMETERS OF THE O HMIC C ONTACTS E XTRACTED BY THE TLM

value of the drain saturation current (380 mA/mm) comes from the large size of the distance between the gate and the source (L GS = 5 μm), which can be verified by theoretical calculation [23]. According to the simplified transportation theory in 2D electron gas (2DEG), the drain saturation current (IDSMAX ) depends primarily on the L G , L GS and W of the device, which is given by IDSMAX =

β (VGT − R S IDSMAX )2 2

(1)

where W με1 d LG = VG − VTH

β =

(3) L GS (4) R S = RC + RSH W 1 (5) RSH = μn s e where μ and n s are the mobility and 2DEG density, with the value of 1750 cm2 /V · s and 1013 cm−3 , respectively. ε1 = 8.9 ε0 is the corresponding dielectric constant, and d is the thickness of the AlGaN barrier layer, with the value of 25 nm. All other parameters have their usual meanings. Finally, the sheet resistance (RSH ) and the drain saturation current (IDSMAX ) are calculated to be 357 / and 494 mA/mm, respectively. The calculated RSH values are very similar to the measured data of 350 /. The small difference between the calculated and measured results of IDSMAX may come from the limitation of the transportation theory [24]–[26], measure precision, and self-heating effects (especially for HEMTs with large gate width). Fig. 11(c) and (d) shows the characteristics VGT

The other parameters and process steps were same and had been optimized as discussed above. The resistances are extracted by TLM method, as shown in Fig. 10 and Table II. It is evident that the RC is greatly reduced with the improvement of the vias’ morphology. Finally, the optimal RC value of 1.07 · mm is obtained. To our best knowledge, this is one of the best values in Ti/Al/Ti/TiN-based Au-free nonrecessed ohmic contacts [22]. The performance of the MIS-HEMTs and the SBDs fabricated together on the 150-mm wafer using the optimized GFDM process were also studied in detail. As shown in Fig. 11(a) and (b), the threshold voltage of the MIS-HEMT is about −9 V with the lowest gate leakage of 20 nA. The RON is 13.4 · mm extracted from Fig. 11(b). The ON/ OFF ratio of the device with 1-mm gate width is almost in the order of 7 decades, which is comparable with other reports. The low

(2)


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R EFERENCES

Fig. 12. Uniformity of the epitaxial wafer and devices on the 150-mm wafer. Inset shows the distribution of RC on the wafer.

of the SBDs on the same wafer. The VF is 0.8 V, which is similar to that in previous report by the IMEC using the same Schottky metal of TiN [27]. The leakage current is 20 nA/mm and 1 μA/mm at a reverse voltage of 200 and 535 V, respectively. The ideal factor n and the barrier height b are calculated to be 1.08 and 0.89 eV, which indicates excellent property of the Schottky contact, even though it was annealed with high temperature during ohmic contacts fabrication. The uniformity of the epitaxial wafer quality and devices properties are shown in Fig. 12, from which a good wafer homogeneity, excellent device uniformity as well as outstanding RC yield with 80% of it lower than 2 · mm can be seen. IV. C ONCLUSION In summary, a GFDM AlGaN/GaN devices fabrication process was proposed and optimized in this paper. For the contact pretreatments, HF (2%, 20 s), SC1 (300 s), and SC2 (300 s) solutions were put forward to treat contacts successively before metal deposition to clean the surface of contacts and prevent TiN being damaged. For the Al diffusion problem during ohmic metal annealing, the calculated maximum diffusion coefficient is 6.39 × 10−8 cm2 · s−1 in SiO2 layer at 850 °C. Therefore, the ohmic annealing temperature and time were fixed at 850 °C and 45 s, respectively, to guarantee the safety of the MIS-HEMTs. Of course, this is not the ultimate method to avoid the Al diffusion problem and further research will be done to eliminate it thoroughly. Finally, for vias etching conditions, better morphology and lower RC have been demonstrated by reducing the thickness of TiN (above Ti/Al/Ti) to 20 nm. With all of these modifications, the MIS-HEMTs, SBDs, and TLM structures fabricated together on the same 150-mm wafer show an outstanding performance and uniformity. Our works contribute to the development of GaN-based power devices ready for integration in large-scale production Si CMOS facilities. ACKNOWLEDGMENT The authors would like to thank all the engineers at the Founder Microelectronics International Corporation, Ltd., Shenzhen, China, for the fabrication and measurement supports in this paper.

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[22] B. De Jaeger et al., “Au-free CMOS-compatible AlGaN/GaN HEMT processing on 200 mm Si substrates,” in Proc. Int. Symp. Power Semiconductor Devices ICs, Jun. 2012, pp. 49–52, doi: 10.1109/ISPSD. 2012.6229020. [23] M. Delagebeaudeuf and N. T. Linh, “Metal-(n) AlGaAs-GaAs twodimensional electron gas FET,” IEEE Trans. Electron Devices, vol. 29, no. 6, pp. 955–960, Jun. 1982, doi: 10.1109/T-ED.1982.20813. [24] P. Roblin, S. C. Kang, and H. Morkoc, “Analytic solution of the velocitysaturated MOSFET/MODFET wave equation and its application to the prediction of the microwave characteristics of MODFETs,” IEEE Trans. Electron Devices, vol. 37, no. 7, pp. 1608–1622, Jul. 1990, doi: 10.1109/ 16.55746. [25] P. P. Ruden, “Heterostructure FET model including gate leakage,” IEEE Trans. Electron Devices, vol. 37, no. 10, pp. 2267–2270, Oct. 1990, doi: 10.1109/16.59919. [26] J. D. Albrecht, P. P. Ruden, S. C. Binari, and M. G. Ancona, “AlGaN/GaN heterostructure field-effect transistor model including thermal effects,” IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2031–2036, Nov. 2000, doi: 10.1109/16.877163. [27] J. Hu et al., “Performance optimization of Au-free lateral AlGaN/GaN Schottky barrier diode with gated edge termination on 200-mm silicon substrate,” IEEE Trans. Electron Devices, vol. 63, no. 3, pp. 997–1004, Mar. 2016, doi: 10.1109/TED.2016.2515566. Hui Sun received the B.S. degree from Jilin University, Changchun, China. He is currently pursuing the Ph.D. degree with the Academy for Advanced Interdisciplinary Studies, Peking University, Beijing, China. His current research interests include the development of GaN power devices manufacturing technologies.

Meihua Liu received the M.S. degree from the Key Laboratory of Integrated Microsystems, School of Computer and Information Engineering, Peking University Shenzhen Graduate School, Shenzhen, China. Her current research interests include the modeling and fabrication of GaN power devices.

Peng Liu received the B.S. degree from the University of Science and Technology of China, Hefei, China, the M.S. degree from the Institute of Physics, Chinese Academy of Sciences, Beijing, China, and the Ph.D. degree from Joseph Fourier University, Grenoble, France. His current research interests include the development of GaN power devices manufacturing technologies.

Xinnan Lin (M’10) received the Ph.D. degree from The Hong Kong University of Science and Technology, Hong Kong, in 2007. Since 2010, he has been an Associate Professor with the Peking University Shenzhen Graduate School, Shenzhen, China.

Jianguo Chen received the B.S. degree from the University of Electronic Science and Technology of China, Chengdu, China. He is currently the Manager with the Product Development Division, Design Service Department, Founder Microelectronics International Corporation, Ltd., Shenzhen, China.

Maojun Wang (M’14) received the B.S. degree from Nanjing University, Nanjing, China, and the Ph.D. degree from the Peking University, Beijing, China. Since 2013, he has been an Associate Professor with Peking University.

Dongmin Chen received the B.S. degree from Shandong University, Shandong, China, and the Ph.D. degree from the City University of New York, New York, NY, USA. He is currently a Professor with the School of Advanced Interdisciplinary Studies, Peking University, Beijing, China.