Packaging and Reliability of Power Modules

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Tilo Poller (TU Chemnitz), Uwe Scheuermann (Semikron ... [1] J. Lutz, H. Schlangenotto, U. Scheuermann, R. De. Doncker ... tuberlin/files/4112/goehre_jens.pdf.

CIPS 2014, February, 25 – 27, 2014, Nuremberg/Germany

Packaging and Reliability of Power Modules Prof. Dr. Josef Lutz, Chemnitz University of Technology, Germany

Abstract Power cycling capability is the main reliability criterion for power modules. Weak points and fatigue processes are pointed-out. Power cycling tests are described, and are discussed regarding the influence of the test method to the results. Existing models for power cycling lifetime prediction are discussed regarding their usability and limits. Going from Si to SiC will be more challenging for the packaging technology. New technologies promise a large progress. Even the potential for modules with specification of the power cycling up to a junction temperature T vjmax = 200°C is visible.

1. Introduction For the IGBT, the power module is the main housing in the application. IGBT-Modules came up in the early 90ies. The used internal configuration is shown in Fig. 1a.


b Figure 1 Standard modules a) with base plate b) without base plate As ceramics, Al2O3 and for high power modules AlN is common. For the base plate, Cu is usual; some special high power modules use AlSiC. Due to standards of ceramics- and base-plate suppliers, even different manufacturers have similar layer thicknesses, details are given in [1]. The housing without base plate (Fig 1b) soon came up due to cost reasons. The module in Fig 1a using Al2O3 ceramics and Cu base plate is denoted as “standard module” in the following to have a base for evaluation of improvements.

2. Fatigue processes in power modules Due to heat generation by power losses, the power device housing is exposed to temperature swings, also passive temperature swings occur due to temperature changes of the environment. These temperature swings expose interfaces between interconnected layers to mechanical load

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due to different coefficients of thermal expansion of different materials and temperature gradients. The selection of materials is done in respect to a low difference in the coefficient of thermal expansion, however, trade-offs have to be made. Main failure mechanisms are described in [2]. Bond wire lift-off is caused by thermal mismatch between Si and Al bond wire. A long time, the bond wires were discussed as the main weak component. Manufacturers improved the bond wire process significantly. With improved bond wire technology, limits of solder layers become more and more visible [2]. There is a chip solder layer (Fig. 1) and a solder layer between substrate and base plate (Fig. 1a). Using large area silicon dies (>0.5 cm²) the hottest spot is below the center of the device. The starting point of degradation of the chip solder therefore depends on power density and cooling conditions. For small lateral temperature gradients, the singularity at the edge is dominant and the solder fatigue starts at the corners. However, when the power density increases, the thermal mismatch in the center is exposed to the highest stress and the fatigue starts in the center of the device and not at the edges. Similar effects were found for the base-plate solder: its degradation is at the position where the heat generating devices are placed – in contrast to passive temperature cycles, were the crack propagation starts at the edge. If solder layers are improved, higher power cycling capability is achieved, and now the substrate is found to be the next reliability limiting factor. Delamination of the Culayer form the ceramics is observed, which is usually found in passive temperature cycles only (see sections 6.2 and 6.5). This shows that DCB substrate technology must also be improved. Finally, also the layer of thermal grease is a weak point. Sometimes, partial no connection is found after removing module from the heatsink. Even if the mounting process is perfect, the layer of thermal grease has a worse thermal conductivity. Especially it forms a kind of thermal contact resistance as described in [3]. A bimodal system with different particle size, maximum particle size of 5 μm, significantly reduces the thermal contact resistance. Some new technologies for water cooled modules like pin-fin or shower-power [4] avoid a layer of thermal grease. Such

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systems allow a higher heat flux density [5]. On the other hand, this may trigger different failure modes in the layers in the thermal path.

3. Power cycling test The power cycling test is the most important reliability test for power modules. At the first glance, it seems easy to apply repetitive power. At the second glance, it is quite challenging to monitor all necessary informations on the ageing-sensitive parameters.

ules with many chips in parallel are given. Due to heat spreading, the different positions have different thermal conditions, and Tvj will deviate even more from Tj of the individual chips. It remains, that the hotter dies are of stronger influence determining T vj. Figure 3 shows the measurement instants of VCE. At the start of the cycle, VCE is monitored at Tvjmin. Before turning off Iload, VCE is measured again, the losses at this point in time are determined by Pv = ICE . VCE . Immediately after turn-off of Iload (delay time td 200 ... 500µs), T vjmax is determined by VCE(Isense), and with help of the calibration function Tvj = f(VCE) the value of Tvjmax is found. If the system is in a stationary state, the thermal resistance is determined with

Rth( j h)  Figure 2 Schematic of a power cycling test Fig. 2 shows the basic schematic. A DC current Iload heats up the device. A sense current Isense in the range of 1/1000 Iload is flowing continuously (Fig. 3). With Isense, the virtual junction temperature Tvj as a characteristic temperature of the silicon device results [1]. T vj is defined by the measured voltage drop over a pn-junction for a small sense current. The forward voltage drop of a pn-junction at very small current depends strongly on temperature and is always decreasing with temperature. A calibration function Tvj = f(VCE) is to be determined before.

Tvj max  Th Pv

T jh



At the cooling down, VCE(Isense) will increase. The resulting evolution of Tvj(t) can be used to determine the transient thermal impedance Zth(t). This method can give informations on the location of the position of weakened layers in the thermal path [7]. During the delay time td, the temperature has decreased. The square-root-t method may improve the measurement accuracy [8]. The solution for one-dimensional heat conduction predicts that for a short period of time, where the active area in the heat path and temperature dependent material parameters are assumed constant, cooling down of the junction follows proportionally to the square root of time [9]:

Tvj (t )  Tvj (0) 


2 P

      cspec 2  A 1

t 2


In Eq. (2), ρ is the specific density and λ is the specific thermal conductivity. After determination of the course of Tvj(t), one can calculate back to the point T vj(0) = Tvjmax. The shape of Tvj(t) was found to be linear with t½ up to a time of several ms, as shown in [8]. An example of the development of [email protected] and Rthjh over the number of power cycles is given in Fig. 4. [email protected] indicates bond wire lift off, to be seen starting at 9500 cycles. Rth,(j-h) indicates solder layer ageing, to be seen starting already at 6000 cycles.

Figure 3: Profile of Iload, Isense, measured VCE and calculated Tvj during one cycle of a power cycling test, and measurement instants It is to be pointed out that the maximal virtual temperature Tvjmax differs from the real temperature T jmax. Tvjmax gives a kind of weighted average temperature [6], while Tjmax for an IGBT with 12 mm x 12 mm area can be between 10 K and 20 K above Tvjmax. It will be even more if mod-

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Fig. 4: Behavior of on-state voltage drop VCE and thermal resistance Rthjh at a power cycling test with Tj = 123 K

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4. Empirical model for lifetime prediction The best available model for standard modules, derived as best fit of a lot of power cycling data, is given by [10]:

N f  K  ΔT j


 ß2    t on ß 3  I ß 4  V  exp  T  low 


 D ß 6 (3)

The CIPS 08 model was given for standard modules with Al2O3 substrates. As parameter K the value 9.30.1014 is suitable, the other parameters ß2 ... ß6 are given in table 1 [10]. Eq. (3), denoted as CIPS 08 model, contains additionally the dependence of the heat-up time ton in s, of the current per bond stitch on the chip I in A, the voltage range of the device V in V/100 (reflecting the impact of the semiconductor die thickness), and of the bond wire diameter D in µm. The given model parameters for V are valid for power devices with thin wafer technology and shallow implanted emitters as used in the 4th generation of the Infineon IGBT. The applicability to devices of other suppliers must be done with care, the die thickness must be known. Roughly, the parameter V in equation (3) can be assumed as device thickness d/10, if d is given in µm. Eq. (3) was derived for d between 60 µm and 160 µm [1]. ß1












Fig. 5: Power cycling of devices with different voltage rating in the same housing. End-of-Life for all samples: Rth-increase. Root cause: fatigue of chip solder Comparing different power cycling results it is essential to know the used control method and test strategy. There are different possibilities, described in [12] and summarized in table 2. All use the same temperature swing ΔT.

Table 1 Parameters for calculation of power cycling capability with Eq. (3)

Table 2 Different possibilities of control method resp. test strategy and their influence to the test result [12]

Eq. (3) was a result of purely statistical analysis and is not a result of physics-based models. The parameters are not physically independent, which was pointed out and discussed by the authors themselves [10]. For low Tj for example, a short heating time will be typical. It was objected that Eq. (3) contains so many parameters. However, the experiments showed an influence of all these parameters. Following work confirmed the prediction of the CIPS 08 model [11]. It was shown that the power cycling capability depends on the voltage range and corresponding semiconductor thickness, see Fig. 5. The results confirm the calculations according to (3) given in the dashed lines. Equation (3), initially given for the IGBT 4 module generation of Infineon, was found to give also reasonable predictions for Al2O3 based standard modules of other professional suppliers. Even for systems without base plate (Fig. 1b), an orientation for the expected lifetime can be calculated. It is not valid for high power modules with AlN ceramics and AlSiC base plate. These systems exhibit a higher power cycling capability.

Strategy 1 is to adjust the power cycling test for required parameters and then to repeat the cycles with constant heating times ton and cooling times toff. ΔT is defined at test start, Tvjmax, Tvjmin and ΔT may vary during test duration. This is the method closest to application. All ageing effects will increase ΔT. It is the most severe method. Strategy 2 is to control the heatsink temperature (variant 1) or the case temperature (variant 2). Since a possible degradation of the thermal interface between module and heatsink would be compensated, this strategy is less severe than strategy 1. Strategy 3 keeps the power density P V constant. An increase of the voltage drop VCE is compensated for example by an increased VGE. This test strategy avoids same acceleration effect of different failure modes to each other and results in a significant increased number of cycles to failure. Strategy 4 supervises Tvjmin and Tvjmax and reduces ton or Iload to keep these parameters constant. This compensates all degradation effects and leads to the highest lifetime. In [12] a difference up to 320% of the different control methods was found. It is therefore essential to know the

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  

control strategy, if power cycling tests are compared. All tests on which Eq. (3) is based were executed with strategy 1 or 2. Eq. (3) does not predict which failure mode occurs. In fact, there is an interaction between the different modes. For example, increased thermal resistance will lead to higher temperature swing and accelerate the failure mechanisms for the bond wire in a positive feedback loop. It is possible to adjust test conditions to address special failure modes. In Fig. 6 an example is given where short ton times with high power density were applied to keep the temperature swing in the same range (Fig. 6a ΔT = 130 K, Tvjmax = 153°C; Fig. 6b ΔT = 136 K, T vjmax = 157°C). For the high power density, an IR camera measurement showed that the corner of the device is more than 100 K colder than the center of the device.

The weak points are known There is an empirical model for lifetime prediction New evaluation tools, e.g. thermal impedance spectroscopy [7] have been shown. However, there is a lot of challenge to theory. There are models describing crack propagation from edge towards center, however this is only a part of what happens, see Fig’s. 6 and 7. We need a model  which is physics based,  which predicts the different failure mechanisms quantitatively,  which considers the feedback of different failure mechanisms to each other,  which is calibrated with experimental data. We need a model for each individual failure mode. There is work to isolate specific failure mechanism and to build a model [14] which calculates the crack origination and crack propagation in each layer and makes a new thermal model for the aged system. However, this model is still in a very initial state.


5. Some Aspects on SiC

b Fig. 6 Scanning Acoustic Microscopy (SAM) images of chip solder fatigue after power cycling with high heat flux density. a) 355W/cm2 ton = 2s b) 646W/cm2 ton =0.2s In Fig. 6 it is obvious that the failure mechanism starts in the center of the device. The microscopic failure mechanism is the evolution of cracks at the grain boundaries in the solder layer, starting from the device center. A cross section image is given in Fig. 7.

Table 3 shows thermal-mechanical material parameters of Si and SiC in comparison. While specific heat and CTE are similar, the thermal conductivity of SiC is three times higher. Also Young’s modulus, which represents the stiffness of the material, is about three times higher. A SiC device will induce a higher stress level into the package as a Si device. Si

4H SiC





CTE [ppm/K]



Young’s modulus E [GPa]



Thermal Conductivity [W/(m*K)] Specific heat [J/(kg*K)]

Table 3 Thermal-mechanical parameters of Si and SiC. Anisotropic effects in SiC are neglected.

Fig. 7 SnAg solder layer, below the center of a die, 75.000 cycles, ΔT = 120K (30/150°C). Fig. from J. Göhre [13] The base plate solder layer can be stressed by power cycles with high ton and at conditions, where the base plate is exposed to a significant temperature swing. This is often given for an air-cooled system. At such conditions, the base plate solder was found to be the first layer which cracks. Summarizing lifetime prediction, there is on the one hand significant progress:

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Numerical simulations predicted that the same packages with SiC dies will have a lower lifetime as with Si devices [15]. This was meanwhile confirmed by experiment: SiC chips in the same housing and similar test conditions reached 32% of the power cycling capability of a 1200V IGBT [16]. A typical plot as observed in the tests is shown in Fig. 8. Using SiC instead of Si therefore requires advanced packaging technologies. It must be noted that the conditions in Fig. 8 are within the usual junction temperatures for Si devices and far away from the high-temperature capability of SiC which, from the semiconductor characteristics, could be operated above 200°C. This would increase the challenge to packaging technology even more.

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The quality of a silver sinter layer depends on its porosity, which depends on process parameters pressure (typ. 30MPa), temperature (around 230°C) and process time. One can get very stable layers. However, the reliability is not unlimited, as shown by [18]. After 2,000 cycles - 55 … +150°C, perimeter fracturing reached 11% to 21% (Fig. 10). This is far above the temperature cycling capability of usual Sn-Ag solder layers.A further alternative is diffusion soldering. Intermetallic compounds Cu3Sn and Cu6Sn5 have much higher melting points and higher mechanical strengths than the Sn-based soft solder base materials [17].

Fig. 8 Plot of the relative thermal resistance during power cycling. 600V SiC Schottky diode, normalized to cycles achieved in test on 1200V IGBT, ΔT j = 81K +/-3K and Tjmax =145 °C +/-5K

6. Improved technologies and future trends in power modules 6.1 Die attach It has been shown that the weakest point is the die attach. One alternative is silver sintering.

Fig. 9 Cross section of a silver sinter joint with optimized process parameters. Porosity < 10%. Fig. from [17]

Fig. 11 Cross-section images of a diffusion bonded layer. Fig. from [17] Both diffusion soldering and silver sintering do not longer limit the power cycling capability. If one of these technologies is used, one can really find the lifetime of bond wires. Using silver sintering as die attach and modules without base plate, in [19] the real lifetime of the bond wires without ageing effects of layers in the thermal path was determined. The given model for bond wires results at most conditions in a higher lifetime, e.g. approx. 25%, as predicted by the CIPS 08 model, given in Eq. (3). In [11], also a significant improvement of the power cycling capability was achieved when replacing the standard solder layer by diffusion soldering. On the other hand, if only the bond wire technology was improved with the standard chip solder layer, no improvement was found. This points out that the main weak point, especially at high temperature swings, was the die attach and not the bond wire. The bond wire limit is found if the die attach is improved.

6.2 Bond wires

Fig. 10 Cracks in a silver sinter layer after a large No of passive temperature cycles. Fig. from [18]

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Power module manufacturers have spent more than 20 years of work in improving the ultrasonic Al bond wire process. Usually the process is part of the protected technology and not published. A published scientific evaluation of some process parameters is done in [13]. The parameters pressure and ultrasonic power are to be adjusted carefully. Nevertheless, Al bond wires come to a limit. Cu bond wires were introduced in [20]. They need a new die metallization with a thick Cu layer as top layer (Fig. 12).

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Cu bond wires in combination with silver sintering or diffusion soldering (Infineon “XT technology”) lead to lifetime, increased by a factor of 30, as shown in [17]. This is a strong progress. Both interconnections are hard to destroy. However, now the substrate was found to become the lifetime-limiting factor [17].

Fig. 13 Skin-technology. All interconnections are done by silver sintering The bond buffer technology [24] applies a thin Cu plate (“bond buffer”), attached on the topside of the die with silver sintering. This layer absorbs the high mechanical load during Cu wire bonding and prevents the die from damage. The technology leads to a homogeneous current distribution across the die.

Fig. 12 Cu bond wire (top) and Cu metallization. Fig. from [20] A possible alternative to Cu wires are Al-coated Cu wires. The Cu core of 230-250µm is coated with an Al layer of 25-35 µm. An improvement by a factor of four and more was found, depending on the used Cu characteristic (hard or soft) and on the conditions [21].

6.3 Alternatives to bond wires Replacement of bond wires by soldered metal layers lead to flat modules with the possibility of low-inductance design. However, in the view of the results of section 6.1, this promises no significant progress in power cycling capability. Some early work, which replaced the bond wires by silver stripes attached with silver sintering, reached an enormous high power cycling capability [22]. Now the substrate was the limiting factor. The construction in [22] however, was far away from a technology for mass production. With the SKiN technology [23], bond wires are replaced by a flexible PCB whose bottom is connected to the topside chip metallization. All interconnections are executed with silver sintering. Additional, the weak point thermal grease layer is eliminated by sintering the module on the base plate. The system is shown in Fig. 13. All weak points are addressed, and the system reaches an extreme large power cycling capability [23].

Fig. 14 Bond buffer technology (Danfoss) The further interconnections from die to substrate and from substrate to base plate are executed with silver sintering. The technology promises also a very high lifetime.

6.4 Substrate to base plate interconnection As mentioned already in section 6.3, the base plate solder layer can be replaced by a silver sinter layer, see Fig.’s 13 and 14. Also, a new solder process substrate to base plate was developed containing vertical intermetallic phases [20]. They counteract crack propagation. In combination with diffusion soldered die attach and improved bond wires, this layer also showed a very large power cycling capability [11].

Fig. 15 Solder layer with vertical intermetallic phases. Fig. from [20].

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6.5 Improved substrates

7. Conclusion

With diffusion soldering [17] as well as with silver sintering [22], finally the substrate becomes the lifetime limiting factor. However, also in substrates a large progress is visible. Table 4 compares some available ceramic materials. thermal conductivity [W/mm/K]

thermal expansion -6 [10 /K]

tensile strength [MPa]

















Table 4 Technical data of ceramic materials used for power electronics substrates The HPS substrate introduced by Curamik [25] consists of Al2O3 with 9% ZrO2, standard thickness is 0.32mm. It offers a higher tensile strength compared to Al2O3 and AlN. However, the highest tensile strength is achieved with Si3N4. Fig. 16 compares the temperature cycling capability [26]. The progress is related to the tensile strength of the used material. For Si3N4, in [26] a special coated material is presented which allows a Direct-Cu-Bonding (DCB) Process. The progress to other substrates is more than a factor of 10.

Improved bond wires alone give no longer lifetime, considering the used conditions. An improved die attach layer (silver sintering or diffusion soldering) leads to a significant progress. Then improved bond wires and improved metallization leads to a significant longer power cycling lifetime. This can be achieved by Cu wire bonds, in combination with a Cu metallization, or by alternative technologies based on silver sintering. Additional improved technologies for the substrate solder layer are available. Experimental results show the potential of the increase in power cycling capability in the range of a factor of 100 [11, 23]. This is a large progress. The reached power cycling capability shows potential for use of power modules with a specification of T jmax = 200°C. This can strongly increase the power density in a power electronic system, and enables to use the higher temperature capability of wide-bandgap semiconductor materials up to some extent. There is a large progress in the recent years. The experience, that press packs are more reliable, must no longer be valid. Manufacturers work on the introduction of the new technologies. Which system finally will be on the market, will always be a compromise between requirements and costs. Therefore, further work in models for the failure mechanism is necessary.

Acknowledgement Mathias Baumann, Marco Bohlländer, Christian Herold, Tilo Poller (TU Chemnitz), Uwe Scheuermann (Semikron Elektronik), Karsten Guth (Infineon Technologies AG), Jens Göhre (Fraunhofer IZM, Berlin) and Martin Becker (Kiel Univ. of appl. science) are acknowledged for figures and technical discussion.


Fig. 16 Temperature cycling -55/+150°C with different substrates. Fig. derived from [26] Note that for Si3N4 active metal brazing (AMB) substrates [27] no failures occurred up to 5000 cycles, were the test was stopped.

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[1] J. Lutz, H. Schlangenotto, U. Scheuermann, R. De Doncker, Semiconductor Power Devices – Physics, Characteristics, Reliability, Springer 2011 [2] J. Lutz, T. Herrmann, M. Feller, R. Bayerer, T. Licht, R. Amro, „Power cycling induced failure mechanisms in the viewpoint of rough temperature environment”, Proceedings of the CIPS 2008 [3] Martin Schulz, “Improved Thermal Transfer for Power Modules”, Power Electronics Europe 03/2013 [4] K. Olesen, R. Bredtmann, R. Eisele, “ShowerPower” New Cooling Concept for Automotive Applications International Conference AUTOMOTIVE POWER ELECTRONICS, Paris (2006) [5] M. Baumann, J. Lutz, W. Wondrak, „Liquid Cooling methods for power electronics in an automotive environment”, Proceedings EPE 2013 [6] Scheuermann U, Schmidt R: “Investigations on the VCE(T) Method to Determine the Junction Temperature by Using the Chip Itself as Sensor”, Proceedings PCIM, Nuremberg (2009)

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[7] A. Hensler, D. Wingert, C. Herold, J. Lutz, M. Thoben, „Thermal Impedance Spectroscopy of Power Modules”, Microelectronics Reliability 51. 2011, pp 1679 - 1683 [8] C. Herold, M. Beier, J. Lutz, A. Hensler, „Improving the Accuracy of Junction Temperature Measurement with the Square-Root-t Method”, Proceedings Therminic 2013, pp 92 - 94 [9] D. Blackburn and F. F. Oettinger, "Transient Thermal Response Measurements of Power Transistors," in IEEE Transactions on Industrial Electronics and Control Instrumentation, 1975 [10] R. Bayerer, T. Licht, T. Herrmann, J. Lutz, M. Feller: “Model for Power Cycling lifetime of IGBT Modules – various factors influencing lifetime”, Proceedings of the 5th International Conference on Integrated Power Electronic Systems, pp 37-42 (2008) [11] C. Herold, A. Hensler, J. Lutz, M. Thoben ,T. Gutt: “Power Cycling Capability of New Technologies in Power Modules for Hybrid Electric Vehicles” Proceedings of the PCIM, Nuremberg, 2012, pp. 486-493 [12] S.Schuler, U. Scheuermann, “Impact of Test Control Strategy on Power Cycling Lifetime”, Proceedings PCIM Nuremberg 2010, pp 355-360 [13] J. Goehre, PhD thesis, Berlin 2013, published online at [14] P. Steinhorst, T. Poller, J. Lutz, „Approach of a physically based lifetime model for solder layers in power modules”, Microelectronics Reliability 53 (2013) 1199–1202 [15] Poller T, Lutz J: „Comparison of the Mechanical Load in Solder Joints Using SiC and Si Chips”, Proceedings ISPS Prague (2010) [16] C. Herold, M. Schäfer, F. Sauerland, T. Poller, J. Lutz, O. Schilling, “Power cycling capability of Modules with SiC-Diodes”, Proceedings CIPS 2014 [17] K. Guth, N. Oeschler, L. Boewer, R. Speckels, G. Strotmann, N. Heuck, S. Krasel, A. Ciliox, „New assembly and interconnect technologies for power modules”, Proceedings CIPS 2012, paper 10.1 [18] S. Narumanchi, “Performance and Reliability of Interface Materials for Automotive Power Electronics”, APEC 2013 Long Beach, Industrial Session [19] U.Scheuermann, R.Schmidt: A New Lifetime Model for Advanced Power Modules with Sintered Chips and Optimized Al Wire Bonds, Proc. PCIM Europe 2013, 810-817. [20] K. Guth, F. Hille, F. Umbach, D. Siepe, and J. Görlich, "New assembly and interconnects beyond sintering methods," Proceedings of the PCIM, Nuremberg, 2010, pp. 232-237 [21] R. Schmidt, U. Scheuermann und E. Milke, „Al-Clad Cu Wire Bonds Multiply Power Cycling Lifetime of Advanced Power Modules,“ Proceedings PCIM, 2012. [22] Amro, R.; Lutz, J.; Rudzki, J.; Thoben, M.; Lindemann, A.; Double-sided low temperature technique for power cycling capability at high temperature; Proceedings EPE 2005 p.10

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[23] U. Scheuermann, “A Technology Platform for Advanced Power Electronics Systems,” Power Electronics Europe, Issue 3, 2012 [24] J. Rudzki, F. Osterwald, M. Becker, R. Eisele, “Novel Cu-bond contacts on sintered metal buffer for power module with extended capabilities”, Proceedings PCIM 2012 [25] Technical data sheet curamik® Ceramic Substrates, 2012 [26] M. Goetz, B. Lehmeier, N. Kuhn, A. Meyer, Silicon Nitride Substrates for Power Electronics, Proceedings PCIM Europe 2012, pp 672-679 [27] Kyocera, Copper-Bonded Silicon Nitride Packages for Power Modules, ndex.html

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