Low Power VLSI Circuit Design with Efficient HDL Coding Bishwajeet Pandey, Manisha Pattanaik VLSI Design Lab, Atal Bihari Vajpayee-Indian Institute of Information Technology, Gwalior Gwalior, India
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Abstract— in this paper, four-bit unsigned up counter with an asynchronous clear and a clock enable is designed in Xilinx ISE 14.2 and implemented on high performance Virtex-6 FPGA, XC6VLX240T device, -1 speed grade, FFG1156 package and ML605 board. User constraints file (ucf) and net list constraints design (ncd) file are taken into consideration with XPower 14.2 for power consumption analysis. We take two codes. Our first code maps the clock enable signal to LUTs then the power consumption is 3.423 Watt. Our second code maps the clock enable signal to control ports then the power consumption is 3.625 Watt. By changing mapping style, we reduce 6% power reduction and also reduce number of LUT and D flip-flop used in implementation leads to area efficient design. By efficiently mapping, we reduce power consumption in multiple of power reduction with single statements. The experimental result shows the power analysis of both HDL mapping code.
Keywords— Clock Enable, LUTs, VLSI, Dynamic Power, Leakage Power, Control Port, Native Generic Circuit, Low Power, Power Analyser
I.
INTRODUCTION
Energy efficient computing and similar green computing accelerates the demands of low power VLSI circuit design. Peoples are ready to give secondary preferences to performance when power saving for durable battery life is required for mobile and portable application and human obligation of environment friendly appliances. Counter is a fundamental digital circuit that performs counting and use as sub circuit in implementation of VLSI circuit design. Low power design is possible with HDL because mapping the Clock Enable always affect the power consumption of ALU because it also changes the Primitive and Black Box usage of native generic circuit (ngc) file. Here, mapping means optimizing one line code from behavioral to data flow HDL coding style. If we map the CE to LUTs (i.e. behavioral coding) it uses 1 inverter, 2 Flip-Flops, 3 LUTs as per technology schematic and power consumption is 3.625W as calculated by Xilinx XPower 14.2. If we map the CE(i.e. dataflow coding) to Control port then it uses 1 GND, 1 FlipFlop, 1 LUT as per technology schematic and power consumption is 3.423W as calculated by XPower14.2. Therefore, we see significant power reduction as compare to quantity of work we done to optimize code. A Statement of the problem: For low power design, low fanout CE is necessary. Using global switches to turn off every CEs don’t serve our purpose
of Low Power design. Therefore, we use synthesis attributes to control the use of control signals at the signal or module level for low power design. Or, we may use alternative coding methods for low fanout CE to reduce dynamic power consumption. II.
RELATED WORK
Ref [1] focuses on the necessity of Intellectual Properties (IP) reuse to shorten the design time and the power consumption of design. An efficient bus protocol for the core communication between IP block is OCP. Open Core Protocol (OCP) defines the only non-proprietary, openly licensed, core centric protocol with high-performance, bus-independent interface between IP cores that reduces design time, design risk, and manufacturing costs and promote IP core reusability for SOC designs. In the paper[2], a new tool CHESS, is designed and developed for control and data-flow graph (CDFG) extraction and the high level synthesis of low power designs from behavioral level VHDL descriptions. The tool optimizes latency, area and power during the different phases of synthesis and provides several solutions to evaluate the tradeoffs during design. Reference paper [3] provides a detailed performance analysis of low power and high speed Look up Table (LUT) by using a circuit technique. In Ref [5] we got the idea of low power design that is applicable on available virtex-6 FPGA. III.
METHODOLOGY
Low fanout CE is necessary for low power design. There are two methods for low fanout CEs. First to use synthesis attributes to control the use of control signals at the signal or module level for low power design. Second is coding (behavioral HDL or dataflow HDL) for low-fanout CE. In this paper, we use coding in place of synthesized attribute to reduce power consumption. A Map the clock enable to the control port Verilog coding to map the clock enable to the control port of counter are as following: if (ce) tmp
