SF3: A Scalabe and Flexible FPGA-Framework for Education and Rapid Prototyping Jan Dürre
Holger Blume
Institute of Microelectronic Systems Leibniz Universität Hannover Hanover, Germany
[email protected]
Institute of Microelectronic Systems Leibniz Universität Hannover Hanover, Germany
[email protected]
Abstract—Field Programmable Gate Arrays (FPGA) are becoming increasingly important in many digital systems due to their high performance and flexibility. The efficient utilization of programmable logic is still complex and requires in-depth knowledge. Therefore, understanding the basic principles of such devices and hardware description languages is of vital importance not only for students of electrical engineering. At best, even schoolchildren should have the opportunity to learn something about FPGAs early on in their education. To enable an easier access to programmable logic, many development kits are available. There are still many obstacles to working with such kits, especially for beginners. Therefore, a new flexible VHDL framework with cross-platform toolchain for simulation and synthesis is presented in this paper. The new system allows a simple and intuitive method to implement FPGA applications, while maintaining the characteristics of logic design. By this means the complexity of implementation-tasks for beginners becomes scalable. The framework is already successfully used in a national logic design contest for schoolchildren. It is easy to use and offers a large range of functionality. The new system is therefore also suitable for rapid prototyping in research projects. Keywords—FPGA; framework; teaching; rapid prototyping
I. INTRODUCTION Field Programmable Gate Arrays are a valuable compromise of performance and flexibility, filling the design gap between dedicated logic circuits and software programmable processors [1]. Hence, FPGAs are an important technology driver in the field of microelectronics. Despite much effort in research regarding high-level synthesis (HLS), teaching the highly specialized expertise in the structure and functionality of FPGAs and hardware description languages (HDL) are important for future engineers [2]. Furthermore, it would be beneficial if even schoolchildren could learn about programmable logic. Because of its complexity, the introduction to this field can be frustrating for university students, much more for schoolchildren. As a starting point for inexperienced users many manufacturers provide development kits, preassembled printed circuit boards with FPGAs, programming interfaces and common peripheral elements such as memory or network interfaces. Such kits often include basic software to allow synthesis and simulation of HDL code as well as tools to program a device. Still, implementing even small applications with such kits requires a significant investment of time and effort, especially for a child, to achieve a successful outcome.
This is mainly due to two reasons. First the concepts of hardware description languages are often very difficult to capture for beginners. Since the design of digital circuits is happening on a lower level, many details are important for a design to actually work. Secondly, the overall design flow for FPGAs is more complex than for many other systems. This leads to frustrating entrance barriers, making it very difficult for learners to succeed even in small tasks. To address those challenges, we propose a new flexible and scalable VHDL framework with cross-platform toolchain for simulation and synthesis. This lowers the obstacles for implementations considerably through abstraction and simplification of the design process. Moreover, the framework is built in a way that the specific characteristics of all subjects and components are maintained, to make sure that beginners can learn all important concepts. The new framework is already used in the German circuit design competition for schoolchildren Invent a Chip [3]. Here, FPGAs are used to emulate logic circuits. Each year about 25 schoolchildren with almost no pre-knowledge in logic design, hardware description, or FPGAs take part in the contest successfully. The paper is organized as follows. Section II gives a more detailed overview about the challenges in the design process. Related work is presented in section III. The new framework is described in detail in section IV. Section V presents a case study. Finally, chapter VI concludes this work. II. CHALLENGES IN THE DESIGN PROCESS Because of its basic properties, logic circuit design is much less abstract than implementations with softwareprogrammable processors. One of the main concepts of processors, being a particular logic circuit, is to be able to describe an algorithm on a higher level of abstraction. Thus, implementing applications with FPGAs can be very challenging for beginners, even after an introduction to the fundamentals of logic design. Examining a typical FPGA implementation can help to further understand those challenges. Generally, most FPGA designs can be disassembled into a universal structure, as shown in Figure 1. A design can be partitioned into three classes. First, a logic circuit to describe the application specific functionality of an implementation. This part of the design can be connected to sometimes reoccurring, general-purpose submodules. Examples for such submodules can be counters, FIFOs, or
even complex circuits like FFT-calculators. These more universal modules can be seen as the second class of implementation parts. Finally, units for communication with peripheral elements, e.g. to transfer data or control a display, are the third segment of many designs. Typically, many peripheral elements are a combination of an integrated digital control circuits and an analog device. The communication with the control circuits is usually device specific, and a large variety of protocols exist. Some knowledge about the electronics of the peripheral elements, as well as detailed information about their functionality, is essential for the implementation of an interface to such systems. FPGA Toplevel-Entity Peripheral Element
Application functionality
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Peripheral Element Submodule
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IP-developers offer similar libraries [6]. In the area of communication-interfaces for high-speed data-transfers between a Host-PC and a FPGA, e.g. PCIe or Ethernet, many more advanced approaches are available [7] [8] [9]. These solutions offer a set of hardware-interface and software-API, and are primarily suited for the implementation of high-end FPGA-accelerators. Those approaches still require a certain amount of special knowledge. Furthermore, with regards to the simulation, verification, synthesis, and utilization of software-tools, the design flow is not simplified, but often even more complex due to additional tools or design steps. Overall, the implementation obstacles cannot be lowered significantly to reach an appropriate level for schoolchildren. In the field of design entry, many approaches are available to simplify the process. The goal of high-level synthesis is to abstract the design entry in a way, that the developer does not need much knowledge about the FPGA architecture or the logic circuit [10]. HLS is useful for developers, who want to utilize the advantages of FPGAs in a simple way. But, this approach is not reasonable when teaching the fundamentals of digital circuit design, HDLs and FPGAs to beginners. IV. NEW SCALABLE AND FLEXIBLE FRAMEWORK
Figure 1: Most FPGA designs can be disassembled into this modular structure
Of course, some general knowledge about Boolean logic, asynchronous and synchronous logic circuits with basic elements, such as flip-flops, the concept and structure of FPGAs, timing, and hardware description with HDLs are also required, even for small FPGA designs. Additionally, the developer has to be familiar with the nontrivial design flow, consisting of iterations of simulation, verification and synthesis, and the respective software tools. The expertise, required to implement the different components of a typical application is summarized as follows. Asynchronous and synchronous logic circuit design (Boolean logic, Multiplexers, FFs, Clock, etc.) Design entry (HDL description) Electronics (peripheral elements) Design flow (simulation, verification, synthesis, tools) Due to the variety of topics, and their complexity, the obstacles for beginners with little pre-knowledge and experience are often too high. Extensive support is required to lower these obstacles to an accessible level. III. RELATED WORK Several research and commercial approaches to simplify the FPGA design process can be found in literature. Most of those approaches address professional developers. Many solutions are available, in particular for the utilization of peripheral elements. This is due to the fact that the interfaces for such components are often reusable in different applications. Thus, it is reasonable to use already existing interface modules, to save effort at implementation. For this purpose many FPGA manufacturers offer libraries or system-builders with standard IP-components [4] [5]. The utilization of such IP-modules is typically reserved for their particular products. Additionally, many commercial
To lower the difficulties for beginners and schoolchildren, this work presents a new flexible VHDL framework with simplified cross-platform design flow. This new system combines different approaches to address the design experience as a whole, while sustaining all important features and characteristics of circuit design with FPGAs. The framework consists of three parts. A predefined and configurable infrastructure to support the circuit design and simplify the utilization of peripheral elements, a model-based testbench to support the verification, and a cross-platform toolchain to assist the design process. Because of its flexibility and ease of use, the system is not only suitable for schoolchildren, but also for many rapid prototyping solutions in research projects. A. Configurable infrastructure An overview of the configurable infrastructure is given in figure 2. The main part being a predefined toplevel-entity. It contains a user module, called application, interfacemodules to allow communication with peripheral elements, and a communication network-link. Furthermore, the system includes a module library. The application module itself is a template with predefined entity. The other sections of the infrastructure are connected in parallel to this entity. This creates a new user toplevel-entity very similar to the actual toplevel-entity. While the toplevel-entity represents the highest hierarchy level connected to the FPGA pins, the application can be seen as an abstraction layer toplevel-entity with pre-wired interface modules. Because of the similarities of the two entities, this system helps beginners understand the general structure of a FPGA design. At the same time, a lot of reoccurring work, like the wiring, is done by the framework. Interfaces The interfaces serve to simplify the communication with peripheral elements. In order to minimize the effort required to understand their utilization, each interface is designed using the same concept with unified signals (see Fig. 2).
FPGA Toplevel-Entity Interface
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chipselect address wr_en data_in data_out interrupt
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external unit, e.g. a host-PC, and the peripheral interfaces or the user toplevel-entity. To make such advanced features accessible for schoolchildren, the network-link is also designed in a specific way. Therefore, the main focus lies in its easiness of use, simplicity and understandability, not necessarily performance. To ease the integration into a typical network infrastructure, the network-link is based on a standard UDP/IP protocol. Embedded in the UDP/IP protocol is an application layer protocol, particularly designed for a communication with the peripheral interfaces. It additionally includes a combination of sequence numbers and ACK-packets to guarantee data-transfers. The sub-protocol is specifically designed to match the register-based concept, and to make it very easy to understand. A Software-API for easy access is available in the user-friendly and cross-platform languages Matlab / Octave and Python. On this API-level the same writeand read-accesses to the peripheral interfaces are possible as from the user application. The same register-based concept is used for data transfer with the user application. Therefore, the user can define own addresses for different functionalities.
Figure 2: Overview of the proposed VHDL framework
The interface concept is register-based, specifically very similar to the design of many peripheral element ICs. To change a specific property of a peripheral element, the user has to execute a write-access through setting chipselect, address, wr_en and data_in. A read-access operates correspondingly. Each access, write or read, is synchronous and takes a single clock-cycle. Individual interrupt signals are available to display events, e.g. the arrival of a new sample. The count of available addresses and the size of the data signals are specific for a peripheral element. But, these properties are not always directly derived from the peripheral element. Instead, the interfaces are used to simplify, abstract and combine functionality. Each address can represent one or multiple functionalities of a peripheral element. Furthermore, communication protocols are abstracted. Many peripherals elements require multiple levels of protocols to control. Lowlevel protocols are dedicated communication protocols, such as I2C or SPI. High-level protocols are sequences, such as a specific series of I2C transfers interrupted by particular pauses. This makes the utilization of peripheral elements for schoolchildren significantly easier, while being able to maintain the basic principle of communication. Additionally, the interfaces lower the overall amount of code to implement in general for any application. Module library The module library contains a growing amount of verified general-purpose components such as counters, FIFOs, or LFSRs. Those components are free to use, and can help to decrease overall the amount of code required to implement any application. Additionally, the library offers the possibility to scale implementation tasks by advisors, by defining what parts of an application should be predetermined or newly implemented by the learner. Communication network-link To broaden the field of applications to more complex network based implementations, the framework also includes a network-link. This link enables transferring data between an
B. Model-based testbench An important step in the design flow is the verification. For most applications, it is reasonable to only perform a functional simulation. But, this requires at least some input data or stimuli. The implementation of a testbench, capable of providing stimuli is challenging, and therefore often skipped or only partially done. This often leads to frustrating trial and error runs for beginners in FPGA design. To support and drastically simplify the verification, the proposed framework includes a predefined model-based testbench. The testbench contains models for each peripheral element, wired to the frameworks toplevel-entity and interfaces. Each peripheral model has its own stimuli- and / or result-textfile. For example, for a peripheral model of an audio-codec, the user can simply write decimal values into the stimuli-textfile. Those will be transferred consecutively to the audio-interface, and are then accessible as audio-samples. Another example would be a SRAM-model. Here, the memory can be preloaded through a stimuli-file. When the simulation is finished, the memory content will be written to a result-textfile. Furthermore, a C-implementation of an UDPclient/server, linked through a foreign function interface (FFI) to the testbench, allows the simulation of the network-link. Thus, data transfers through the network API are also possible with the simulated application. C. Toolchain The third and final part of the new system is a script-based toolchain to automate the simulation and synthesis procedure. The toolchain is available for different operating systems since many schoolchildren are only used to one or the other. Via configuration-file the user can define which interface to utilize, and if the network-link should be used. Based on the configuration, the system automatically wires and builds the toplevel-entity and testbench, and creates simulation and synthesis-projects with pin-mapping and timing constraints. Afterwards the user can utilize the script to automatically run a simulation or synthesis, or alternatively use the created projects to run the procedures by hand.
This toolchain allows some scaling of the level of userinvolvement in the process from full automation to manual utilization of the simulation- and synthesis-software. This enables teachers to individually customize the procedure for a specific implementation task. V. CASE STUDY: STUDENT CONTEST The presented new VHDL framework is currently used in the German student contest Invent a Chip. In this contest, schoolchildren of age 14 to 18 design logic circuits to implement their own applications based on an annually changing theme. The main goal of the competition is to recruit schoolchildren for career choices in electrical engineering. The competition is carried out in two parts. At first, in a 3-days workshop the participants learn the basics of Boolean logic, logic circuits, FPGAs, and hardware description. In the second phase, the schoolchildren work for about four months at home to implement their applications autonomous. During this phase, the students are supported by experts via an online-forum. The utilization of the new framework enables most students, after only a 3-days basic workshop, to succeed in the autonomous practice phase.
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(1) Temperature & humidity (Inner side)
LCD
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(3) Micropore
UV (Outer side)
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Temperature & humidity (Outer side)
(4) Stepper motor
(1) (2) (3) (4)
An exemplary student implementation in the competition is the project Smart Wear. In this implementation, smart clothing is equipped with inside-sensors for temperature and humidity, and with outside-sensors for temperature and humidity and UV-radiation. Based on the sensor measurements, the logic circuit regulates the air flow through a stepper-motor controllable micropore to sustain a pleasant climate. Furthermore, the user can provide his skin tone and eye color through a Laptop with UART-interface to get recommendations for sun retention time, based on the current UV-radiation. Measurements and recommendations are displayed on a LC-display. Figure 3 shows a simplified structure of this project. For many peripheral elements (laptop, LC-display, UV-sensor) a framework-interface (UART, LCD, ADC) is available. Other elements (temperature and humidity sensors, stepper-motor) required custom control through GPIOs. The implementation of such control modules is supported with library modules (e.g. I2C-master). The framework enabled a schoolchild of age 17 to successfully build this complex system autonomously. VI. CONCLUSION In this paper a new scalable and flexible VHDL framework was presented. It is designed to address the challenge of making digital logic design and hardware description with FPGAs approachable for inexperienced users. The system consists of a predefined infrastructure with unified interfaces for peripheral elements, a module library, and an easy to use network-link with Matlab / Octave and python API. The design flow is supported by a flexible model-based testbench and a cross-platform toolchain for simulation and synthesis. This enables scaling the abstraction and simplification of the design process individually. Because of its flexibility the new framework is suitable for the education of schoolchildren, as well as for rapid prototyping in research projects. Finally, a case study of a logic design contest for schoolchildren shows the frameworks usability.
Laptop
REFERENCES
FPGA Toplevel-Entity (3) (1,2,4)
(5) (6)
ADC
IF
GPIO
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LCD
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UART
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Application Motor control Sensor control
I2C-Master
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Main control
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Figure 3: Example project: Smart Wear
Terasic DE2-115 development boards [11] with Altera/Intel Cyclone IV FPGA are utilized in the contest. The framework is preconfigured for the competition regarding the interfaces available (GPIO, ADC, DAC, audio-codec, infrared-sensor, LCD, 7-segment-display, SRAM, UART). In terms of the design flow, the toolchain scripts are used to initially generate simulation and synthesis projects for Modeltech ModelSim and Altera/Intel Quartus, which are then used by the participants.
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