Paper Title (use style: paper title)

GaN Based Switched Capacitor Three-Level Buck Converter with Cascaded Synchronous Bootstrap Gate Drive Scheme Suvankar Biswas and David Reusch Efficient Power Conversion Corporation El Segundo, CA, USA Abstract— With the power architecture transition from a 12 V to 48 V rack in modern data centers there is an increased interest in improving 48 V power conversion efficiency and power density. A three-level GaN based converter provides a high density and high efficiency solution. In this paper, we will introduce a high performance GaN based switched capacitor three level buck converter for 48 V applications. To fully utilize GaN technology in multilevel topologies, an improved cascaded synchronous bootstrapping technique is also proposed. The proposed gate driving technique is smaller and simpler than the previous gate driving techniques employed in GaN based multilevel topologies and offers tight gate voltage regulation. For experimental verification, a three-level switched capacitor buck converter with the improved gate drive scheme and closed loop flying capacitor balancing is compared against a traditional buck converter. In order to demonstrate a possible further application of the gatedrive scheme, a higher voltage (400 V) prototype is built, with improved experimental results over a regular half-bridge prototype. A simple startup protection scheme using Zener diodes is also verified, which removes the need for full voltage rated switches altogether. Finally, an improved 48 V to 12 V three-level prototype is discussed which combines the benefit of using lower rated GaN devices along with inductor size reduction.

𝑉𝑖𝑛 (0.5 − 𝐷)𝐷 , 𝐷 < 0.5 … . (2) Δ𝐼𝐿 𝑓𝑠𝑤 𝑉𝑖𝑛 (𝐷 − 0.5)(1 − 𝐷) 𝐿3−𝑙𝑒𝑣𝑒𝑙 = , 𝐷 > 0.5 … . (3) Δ𝐼𝐿 𝑓𝑠𝑤 where 𝑉𝑖𝑛 is input voltage, 𝐷 is duty ratio, 𝑓𝑠𝑤 is switching frequency, Δ𝐼𝐿 is peak-to-peak inductor current ripple. These equations are plotted in Figure 2, which clearly shows the size reduction gained with a three-level topology over the entire range of duty ratio, with 50% duty being the operating condition of a conventional switched capacitor circuit. Beyond inductance reduction, multi-level topologies also reduce the effective voltage stress. Using lower voltage rated devices in a three-level topology offers greater advantage in terms of semiconductor losses, since lower voltage rated devices have lower Figures of merit (FOM). This advantage is further multiplied when using GaN transistors compared to silicon [21]. This is illustrated in Figure 3. 𝐿3−𝑙𝑒𝑣𝑒𝑙 =

I. INTRODUCTION For higher performance in 48 V applications [1-3], there have been many different topological approaches ranging from hard-switching [4-6,8] to highly resonant [7,9-12], fully regulated to unregulated, and fully isolated to non-isolated. With the significant reduction in board space occupied by the smaller GaN transistors, topologies that require a greater number of active devices have become attractive, as a tradeoff for reduced passive component size which is the main barrier to higher power density. Switched capacitor circuits are good examples of topologies that can effectively reduce or eliminate passive components [12-18]. Following along the same lines, switched resonant tank converters have also become popular [19,20]. In this paper, a three-level buck converter (circuit and timing diagrams in Figure 1) is implemented with GaN transistors as the main design example. Quantitatively, the inductor size reduction is due to an effectively doubled switching frequency and half the input voltage compared to a buck. This is evident in (1)-(3): 𝑉𝑖𝑛 (1 − 𝐷)𝐷 𝐿𝐵𝑢𝑐𝑘 = … . (1) Δ𝐼𝐿 𝑓𝑠𝑤

(a)

(b) Figure 1: Circuit schematic and timing diagram for three level buck converter

cascading bootstrap diode drops and can also overcharge at load due to dead-time conduction of the GaN body diodes, which have high forward drops [28]. These problems will magnify as the number of levels in the converter increases, since the diode drops add in series.

Figure 2 : Inductor size reduction in a 3-level buck

(a)

Figure 3 : Figure of merit (FOM) comparison of GaN and Si devices for voltages from 30 V to 200 V

II.

CASCADED SYNCHRONOUS BOOTSTRAP GATE DRIVE SCHEME

In multilevel converters, the majority of the switches are not ground-referenced and several solutions have been previously proposed to drive GaN devices in multilevel topologies [22-27]. For the majority of the proposed solutions [22-26], bulky onchip isolated DC-DC converters are used to provide power to floating switches. In [27], the isolators have been replaced by complicated charge pumps and LDO circuitry. In all of the previous implementations, the complicated drive circuitry limits the density of the system and increases the part count. In this paper, we will evaluate simpler methods for driving GaN transistors in multilevel topologies and propose an experimentally verified solution which provides a simpler alternative than previous works [22-27] with tight gate voltage regulation. A cascaded diode conventional bootstrapped circuit is shown in Figure 4(a) along with the charging paths for the bootstrap capacitors. In the depicted generic N-level case, blue denotes the bootstrap capacitor CB1 charging path for the uppermost device S1, red denotes the charging path for any intermediate bootstrap capacitor CB(N-2), and green denotes the charging path of the lowest bootstrap capacitor CB(N-1). Each higher-level bootstrap capacitor charges off the bootstrap capacitor at its immediate lower level, i.e, CB4 charges off CB3, CB3 charges off CB2 and so on. The higher-level bootstrap capacitors suffer from an undercharging problem due to the

(b) Figure 4: (a) Conventional and (b) proposed bootstrapping methods

In order to counter the issues of the cascaded diode approach in multilevel converters, a cascaded synchronous bootstrapping method is proposed. This is shown in Figure 4(b). This method avoids the extraneous voltage regulators compared to [27], does not utilize power circuitry for charging the bootstrap capacitors and is independent of the switching sequence of the converter. This scheme aims to improve upon the cascaded diode scheme, by replacing the bootstrap diode with a much lower dropout synchronous GaN FET (QBST) and by preventing overcharging of the bootstrap capacitors during dead-time conduction periods. This scheme works as follows: when GN is low, CBST(N1) charges to VDR-VBST(N-1) ≈ 3.5-4.0 V. When GN is high, the gate of QBST(N-1) is pushed to VDR + VCBST(N-1) while its source is

at VDR (5 V). This reverse biases DBST(N-1) and keeps QBST(N-1) turned on. With the low dropout of QBST(N-1), CB(N-1) charges to a value very close to VDR through the charging path shown in green. This also results in low losses in the charging circuit since the GaN FET QBST(N-1) (high voltage, low current) is devoid of reverse recovery losses [28]. In a similar way, CB(N-2) charges off CB(N-1), CB(N-3) charges off CB(N-2) and so on. To experimentally compare the approaches, a three-level buck converter is built with the gate drive configurable to both the conventional cascaded diode bootstrap and the proposed synchronous bootstrap approach. The gate drive waveforms for the conventional diode approach (refer Figure 4(a)) are shown in Figure 5(a) and the corresponding drive voltages are shown in the table of Figure 5(b), at no load and no power. It is seen that the gate drive voltages decrease with the higher levels as expected, with Vgs2 = 3.51 V (drive voltage for S2 with reference to Figure 1), which is well below the desired GaN drive voltage [21], while Vgs1 (drive voltage for S1) is a diode drop below Vgs2, which triggers the undervoltage lockout (UVLO) function in the topmost gate driver, rendering the converter inoperable. Hence this scheme is invalid for three and higher level GaN based converters.

and that the technique can be used for a converter with a higher number of levels.

(a)

(b) Figure 6: (a) Gate drive waveforms for cascaded synchronous bootstrap and (b) variation over load current

(a) Vgs4 5.04 V

Vgs3 4.29 V

Vgs2 3.51 V

Vgs1 2.80 V (UVLO)

(b) Figure 5: (a) Gate drive waveforms for cascaded diode bootstrap and (b) drive voltages

The results with the synchronous bootstrapped approach, are shown in Figure 6, with the schematic shown in Figure 4(b). The topmost (S1) and bottommost (S4) gate voltage waveforms are shown at no load in Figure 6(a), which represents the worstcase condition for gate voltage variation. The difference is around 0.5 V, which is well within the target drive voltage range for the GaN transistors [21]. For the cases with load, the gate voltages are plotted in Figure 6(b). The region in green represents a variation of 0.5 V from 5 V. There is very little drop between all of the GaN transistors for all operating conditions. The low voltage difference between the devices demonstrates that there is little voltage drop-out in this scheme

The cascaded synchronous bootstrap technique ensures the minimal electrical loop and minimal inductance path for charging the bootstrap capacitor at a certain level by using only the single power transistor immediately below it. For example, CBX charges through power transistor SX+1. This ensures that none but the lowest bootstrap capacitor (CB(N-1)) charges through the power ground. This provides the most consistent electrical charging path. The cascaded technique can be used for any stacked or hybrid stacked topology, since the bootstrap capacitor only needs the power transistor immediately below it to turn on in order to charge itself. III.

CONTROL SCHEME FOR THE MULTILEVEL CONVERTER

Flying capacitor voltage balancing is an integral part of a multilevel converter [29-31]. For the prototypes in this work, we have chosen a proportional (P) controller to implement the flying capacitor balancing for CFLY and a proportional-integral (PI) controller to regulate the output feedback loop to 12 V. The scheme is shown in Figure 7(a) with R-C filters being used for measuring the flying capacitor nodes. The switch node waveforms are shown in Figure 7(b) with and without capacitor

voltage balancing, which underlines the need for the closed loop system. In the unbalanced open-loop case, there is a mismatch of +/- 8 V (33%) with respect to the target voltage of 0.5VIN= 24 V. The control was implemented using a dsPIC33 digital controller from Microchip®. The Analog-to-Digital Converters (ADCs) on this controller have a sample rate of 3.25 MSPS. The control circuit parameters are listed in Table I.

IV.

EFFICIENCY COMPARISON WITH TRADITIONAL CONVERTER

The three-level buck converter, whose schematic and timings are shown in Figure 1, and experimental hardware shown in Figure 8(b), uses a flying capacitor to double the effective switching frequency and reduces the voltage stress by a factor of two. This offers significant reductions in required inductor size and switching losses in the power devices [32]. Figure 8(a) compares the efficiency of the conventional buck converter with the three-level buck converter shown in Figure 8(b). The three-level converter is operated at 320 kHz, an effective switching frequency of 640 kHz, and uses a 50% smaller volume 1.5 µH inductor than the conventional buck. The conventional buck converter operates at 500 kHz and uses a 3.3 µH inductor, where the inductor optimization is discussed in [33]. The three-level converter provides a 25% reduction in power loss at full load over a conventional buck and over a 1% improvement in peak efficiency. The first prototypes use 100 V EPC2045 eGaN FETs for both two and three level versions. The driver used is LM5113 from Texas Instruments [34]. Because of the inherent ability to reduce device stress, the three-level converter can use 50% lower rated devices to further improve efficiency. This will be expanded upon in Section VI.

(a)

(a)

(b) Figure 7: (a) Multilevel Converter Control Scheme and (b) Flying Capacitor balancing waveforms TABLE I: CONTROL CIRCUIT PARAMETERS Parameter Sense Resistors Riu ,Rpu, Rnu Sense Resistor Rol, Rol, Rpl, Rnl Sense Resistor Rou Filter Capacitors Cfi, Cfp, Cfn, Cfo Fixed Increment Proportional Gain KP (for CFLY balancing) Proportional Gain Kp (for Vo regulation) Proportional Gain Ki (for Vo regulation)

Value 20 kΩ 1 kΩ 4.99 kΩ 10 nF 1e-4 0.01 0.015

(b) Figure 8: (a) Experimental efficiency comparison between two (traditional) and three level buck converters and (b) three-level hardware prototype

V.

EXPANSION TO HIGH VOLTAGE

To further expand the possible applicability of the gate drive scheme introduced in this paper, we have also built a higher voltage (400 V) prototype, catered for PFC type applications such as a TV adapter [35], where significant gains can be obtained from a reduction in size of the choke and subsequently of the EMI filter [36] of the PFC circuit. The prototype is shown in Figure 9(a) and (b). The gate driver used is the LMG1210 from Texas Instruments. The GaN FET used for the switches S1 to S4 is the 350 V EPC2050.

Figure 11: High voltage 3-level prototype efficiency comparison against conventional 2-level buck

Figure 9: (a) Experimental prototype (2" x 2" PCB) for 400 V DC Bus type application, top view and (b) bottom view.

The capacitor balancing was implemented on this prototype similar to Section III. The balanced switch node is shown in Figure 10. The peak voltage with overshoot is observed to be 218 V which is very much below the peak voltage rating of the transistor (350 V).

A. Startup and Protection When starting the converter for the first time, CFLY has no charge initially and then the capacitor balancing algorithm will eventually bring it to VIN/2. This is detrimental because it will cause overvoltage to S1 when it is blocking if the capacitor is charged to less than VIN/2. This is shown in Figure 12, when S4 is on for the first time and S1 is overvoltaged. In order to prevent this, a Zener clamp Dz1 is used across S1 along with a series resistor of Rz1. The choice of Rz1 is a tradeoff between the power dissipation in Dz1 and the clamping speed of Dz1. The higher Rz1 is, the lower the power dissipation in Dz1, but the longer the clamping time to the rated value of Dz1. For this experimental prototype, we have selected Rz1 = 25 , and a 300 V Zener clamp which yields sufficient clamping without dissipating excessive power in the diode Dz1. The startup waveforms are shown in Figure 13. The voltage across S1 is clamped to 302 V, while CFLY ramps up slowly from a low duty ratio to its eventual value of VIN/2 = 200 V. This test is also done at no load, which represents the worst-case condition for capacitor balancing. The Tektronix IsoVu TIVH08 [37] has a bandwidth of 800 MHz and is used to make the high voltage floating node measurements, i.e., Vds, S1 and Vcfly.

Figure 10: Flying Capacitor balancing waveforms for the HV Prototype

The efficiency of the 400 V three-level prototype is then compared against a conventional buck converter using 650 V rated GaN HEMTs. This is shown in Figure 11. The inductor used is 235 µH. The lower Figure-of-merit (FOM) 350 V device shows a clear advantage in a three-level converter, with a peak efficiency improvement of greater than 2%. The three-level converter achieves a power density of 1884 W/in3 for a 100 W system, not including the inductor and protection circuit. Figure 12: Startup sequence and Protection for first CFLY discharging cycle

Figure 13: Startup protection for the 350 V EPC2050 top switch (S1)

In prior art such as [38], the practice of using a full voltage rated top switch (which in this case would be 650 V) has been utilized, which limits the device voltage advantage of the multilevel converter to some extent. VI.

HIGHER CURRENT 48 V PROTOTYPE

In order to further improve upon the three-level prototype introduced in Section IV, lower voltage rated EPC2015C GaN FETs (40 V) are used as an additional benefit to the passive size reduction already obtained in the three-level converter of Section IV. The power stage of the improved, fully regulated 48 V to 12 V prototype is shown in Figure 14. The efficiency comparison to the single-phase, 700 kHz conventional buck (EPC9205) developed in [32] is shown in Figure 15. It shows better performance for the higher current three-level prototype, a greater than 0.5% efficiency improvement observed at 10 A. The efficiency also shows an increase compared to our earlier three-level prototype in Section IV at higher load currents, i.e., 8 A and above, while the efficiency is the same below 8 A.

Figure 15: Efficiency comparison between improved three-level prototype and conventional buck [32]

VI.

CONCLUSIONS

Focusing on improving efficiency and power density for 48 V to 12 V power conversion, a GaN based three-level buck converter is proposed, in an effort to further decrease the inductor size, which dominates real estate in a corresponding two-level design and approximately 80% of the total volume. The three-level design demonstrates significant improvements in converter efficiency and reductions in inductor volume. The three-level design also introduces a novel cascaded synchronous bootstrapped gate driving scheme, which significantly simplifies the driving scheme for GaN based multilevel converters, and also incorporates a simple flying capacitor balancing scheme. A higher voltage prototype, which also offers a peak efficiency improvement of 2% over a two-level prototype, is also designed in order to demonstrate a possible further application of the gate drive scheme, most notably in PFC circuits. A startup protection scheme which protects the GaN FETs from initial overvoltage is also verified. In order to fully utilize the benefits of multilevel converters, lower voltage rated devices are used in conjunction with reduced inductor size in building an improved version of the three-level 48 V to 12 V prototype. Significant efficiency and power density improvements are demonstrated over the conventional two-level EPC9205 developed in [32]. ACKNOWLEDGEMENTS The authors would like to give special thanks to Andrew Ferencz of Ferencz Consulting for his support in the development of the digital controller. We would also like to thank Michael J. Mende of Tektronix Inc. for his assistance with the TIVH08 isolated probe.

Figure 14: Power Stage of improved three-level prototype with EPC2015C and 1.5 H inductor (Vishay IHLP-4040-DZ-01 series)

With 20 A of load current, this prototype can achieve a power density approaching 2000 W/inch3. The conventional two-level buck [32] had a power density of 1400 W/inch3.

REFERENCES [1] X. Li and S. Jiang, “Google 48V Power Architecture,” 2017 IEEE Applied Power Electronics Conference and Exposition (APEC), Plenary. http://apecconf.org/Portals/0/APEC%202017%20Files/Plenary/APEC%20Plenary%20G oogle.pdf?ver=2017-04-24-091315-930×tamp=1495563027516 [2] L. Tung, “Google, Facebook pause rivalries: Here's their 48V power-saving rack spec for Open Compute Project,” ZDNET, August 2016.

http://www.zdnet.com/article/google-facebook-pause-rivalries-heres-their48v-power-saving-rack-spec-for-open-compute-project/ [3] S Taranovich, “Data center next generation power supply solutions for improved efficiency,” EDN network, April, 2016. [4] Ericsson PKB 4204B PI datasheet. [Online] www.ericsson.com [5] General Electric EBDW025A0B datasheet. [Online] www.geindustrial.com [6] Ericsson BMR457 datasheet. [Online] www.ericsson.com [7] Delta Electronics E54SJ12040 datasheet. [Online] www.deltaww.com [8] J. Glaser, J. Strydom, and D. Reusch, “High Power Fully Regulated Eighthbrick DC-DC Converter with GaN FETs,” International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management (PCIM Europe), 2015, pp. 406–413. [9] Vicor PI3546-00-LGIZ evaluation board. www.vicorpower.com [10] D. Reusch, "High Frequency, High Power Density Integrated Point of Load and Bus Converters", PhD Dissertation, Virginia Tech, 2012. [11] Vicor BCM48Bx120y300A00 datasheet. www.vicorpower.com [12] T. A. Meynard and H. Foch, "Multi-level conversion: high voltage choppers and voltage-source inverters," Power Electronics Specialists Conference, 1992. PESC '92 Record., 23rd Annual IEEE, Toledo, pp. 397-403, 1992, vol.1 [13] Y. Lei, C. Barth, S. Qin, W.-C. Liu, I. Moon, A. Stillwell, D. Chou, T. Foulkes, Z. Ye, Z. Liao and R.C.N. Pilawa-Podgurski, “A 2 kW, Single-Phase, 7-Level, GaN Inverter with an Active Energy Buffer Achieving 216 W/in^3 Power Density and 97.6% Peak Efficiency”, IEEE Applied Power Electronics Conference, Long Beach, CA, 2016. [14] V. Yousefzadeh, E. Alarcon, and D. Maksimovic, “Three-level buck converter for envelope tracking applications,” IEEE Transactions on Power Electronics, vol. 21, no. 2, pp. 549–552, March 2006. [15] D. Reusch, F. C. Lee, and M. Xu, “Three level buck converter with control and soft startup,” in 2009 IEEE Energy Conversion Congress and Exposition, Sept 2009, pp. 31–35. [16] J. S. Rentmeister and J. T. Stauth, "A 48V:2V flying capacitor multilevel converter using current-limit control for flying capacitor balance," 2017 IEEE Applied Power Electronics Conference and Exposition (APEC), Tampa, FL, 2017, pp. 367-372. [17] A. Stillwell, Robert C. N. Pilawa-Podgurski, "A 5-level flying capacitor multi-level converter with integrated auxiliary power supply and start-up," 2017 IEEE Applied Power Electronics Conference and Exposition (APEC), Tampa, FL, 2017, pp. 2932-2938. [18] Z. Ye, Y. Lei, W. c. Liu, P. S. Shenoy and R. C. N. Pilawa-Podgurski, "Design and implementation of a low-cost and compact floating gate drive power circuit for GaN-based flying capacitor multi-level converters," 2017 IEEE Applied Power Electronics Conference and Exposition (APEC), Tampa, FL, 2017, pp. 2925-2931. [19] Y. Li, X. Lyu, D. Cao, S. Jiang and C. Nan, "A high efficiency resonant switched-capacitor converter for data center," 2017 IEEE Energy Conversion Congress and Exposition (ECCE), Cincinnati, OH, 2017, pp. 4460-4466. [20] S. Jiang, C. Nan, X. Li, C. Chung and M. Yazdani, "Switched tank converters," 2018 IEEE Applied Power Electronics Conference and Exposition (APEC), San Antonio, TX, 2018, pp. 81-90. [21] A. Lidow, J. Strydom, M. de Rooij, D. Reusch, GaN Transistors for Efficient Power Conversion, Second Edition, Wiley, 2014, ISBN 978-1-11884476-2. [22] I. Moon et al., "Design and implementation of a 1.3 kW, 7-level flying capacitor multilevel AC-DC converter with power factor correction," 2017 IEEE Applied Power Electronics Conference and Exposition (APEC), Tampa, FL, 2017, pp. 67-73. [23] C. Barth et al., "Experimental evaluation of a 1 kW, single-phase, 3-level gallium nitride inverter in extreme cold environment," 2017 IEEE Applied Power Electronics Conference and Exposition (APEC), Tampa, FL, 2017, pp. 717-723. [24] T. Modeer, C. B. Barth, N. Pallo, W. H. Chung, T. Foulkes and R. C. N. Pilawa-Podgurski, "Design of a GaN-based, 9-level flying capacitor multilevel inverter with low inductance layout," 2017 IEEE Applied Power Electronics Conference and Exposition (APEC), Tampa, FL, 2017, pp. 2582-2589. [25] A. Stillwell, and Robert C. N. Pilawa-Podgurski, "A 5-level flying capacitor multi-level converter with integrated auxiliary power supply and

start-up," 2017 IEEE Applied Power Electronics Conference and Exposition (APEC), Tampa, FL, 2017, pp. 2932-2938. [26] Chen, M. "Merged Multi-Stage Power Conversion: A Hybrid SwitchedCapacitor/Magnetics Approach", PhD Dissertation, Massachussetts Institute of Technology, 2015. [27] Z. Ye, Y. Lei, W. c. Liu, P. S. Shenoy and R. C. N. Pilawa-Podgurski, "Design and implementation of a low-cost and compact floating gate drive power circuit for GaN-based flying capacitor multi-level converters," 2017 IEEE Applied Power Electronics Conference and Exposition (APEC), Tampa, FL, 2017, pp. 2925-2931. [28] D. Reusch and M. de Rooij, "Evaluation of gate drive overvoltage management methods for enhancement mode gallium nitride transistors," 2017 IEEE Applied Power Electronics Conference and Exposition (APEC), Tampa, FL, 2017, pp. 2459-2466. [29] V. Yousefzadeh, E. Alarcon and D. Maksimovic, "Three-level buck converter for envelope tracking in RF power amplifiers," Twentieth Annual IEEE Applied Power Electronics Conference and Exposition, 2005. APEC 2005., Austin, TX, 2005, pp. 1588-1594 Vol. 3. [30] R. Stala, "The Switch-Mode Flying-Capacitor DC–DC Converters With Improved Natural Balancing," in IEEE Transactions on Industrial Electronics, vol. 57, no. 4, pp. 1369-1382, April 2010. [31] C. Carstensen and J. Biela, "A Three-Level Buck Converter With a Wide Voltage Operation Range for Hardware-in-the-Loop Test Systems," in IEEE Transactions on Power Electronics, vol. 31, no. 9, pp. 6176-6191, Sept. 2016. [32] D. Reusch, S.Biswas and M. de Rooij, "GaN Based Multilevel Intermediate Bus Converter for 48 V Server Applications," PCIM Europe 2018; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Nuremberg, Germany, 2018. [33] D. Reusch, S. Biswas and Y. Zhang, "System optimization of a high power density non-isolated intermediate bus converter for 48 V server applications," 2018 IEEE Applied Power Electronics Conference and Exposition (APEC), San Antonio, TX, USA, 2018, pp. 2191-2197. [34] Texas Instruments, LM5113 Datasheet. [Online] www.ti.com. [35] Infineon, “Power and Sensing Selection Guide 2018”.[Online] www.infineon.com/powerandsensing-selectionguide [36] F. Forest, T. A. Meynard, S. Faucher, F. Richardeau, J. J. Huselstein and C. Joubert, "Using the multilevel imbricated cells topologies in the design of low-power power-factor-corrector converters," in IEEE Transactions on Industrial Electronics, vol. 52, no. 1, pp. 151-161, Feb. 2005. [37] Tektronix, TIVH08 Isolated Measurement System. [Online] www.tek.com. [38] Analog Devices LTC7820 Datasheet. [Online] www.analog.com