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Modeling and Analysis of Series–Parallel Switched-Capacitor Voltage Equalizer for Battery/Supercapacitor Strings Yuanmao Ye and Ka Wai E. Cheng, Senior Member, IEEE Abstract— A series–parallel switched-capacitor (SC) power converter is reconfigured as a new voltage equalization circuitry for series-connected batteries or supercapacitors in this paper. The model of the new voltage equalizer is derived and successfully used to analyze the equalization speed and the energy loss. It is a very useful tool to analyze and design the SC-based equalization systems to meet different balancing speed requirements. The analysis and modeling methods can be extended to other SC-based voltage-balancing systems. A prototype is built and the experimental results are provided to confirm the theoretical analysis and the modeling method. Index Terms— Battery-management system, model, switched-capacitor (SC), voltage equalization.

I. I NTRODUCTION ARGE numbers of batteries or supercapacitor cells are usually connected in series to meet high operating voltage requirements. All series-connected cells are, therefore, charged and discharged together. Due to the nonuniform properties of individual cell, repeated charging and discharging will cause small imbalance in the form of unequal voltages existed among cells [1], [2]. To overcome this problem, the voltage-balancing device, also known as a voltage equalizer, is an indispensable piece of equipment in battery-management systems [1]–[4]. The simplest method to equalize battery cells’ voltage is implemented using resistors to consume the exceed energy of higher voltage cells in the form of heat [5], [6]. The main drawbacks of this method are energy waste and the temperature rise. In order to avoid the waste of energy during the voltage-balancing process and to make every cell providing the best performance, various active balancers are designed based on switched-mode power conversion circuits in [7]–[18]. The common design philosophy of these strategies is using power converters to transfer energy from the higher voltage cells to the lower ones. Another type of active cell-balancing methods is implemented by employing switched capacitor (SC) as the

L

Manuscript received October 10, 2014; revised December 29, 2014 and February 14, 2015; accepted March 26, 2015. Date of publication April 1, 2015; date of current version October 29, 2015. This work was supported in part by the Innovation and Technology Fund through the Hong Kong Technology and Innovation Commission and in part by JL Ecopro Technical Ltd., Hong Kong, under Project UIM245. Recommended for publication by Associate Editor Sudip K. Mazumder. The authors are with the Department of Electrical Engineering, The Hong Kong Polytechnic University, Hong Kong (e-mail: [email protected] connect.polyu.hk; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JESTPE.2015.2418339

energy-transfer component [19]–[23]. It has the advantages of small size and cost effectiveness, as well as easy control. According to [24]–[32], the performance of SC power conversion circuits can be seen as a combination of an ideal transformer and an equivalent resistor. It shows the power transfer capacity of SC power conversion circuits mainly depends on the switching frequency and the value of SCs. Specific to the SC-based voltage equalization systems, the voltage-balancing speed can be directly reflected by the model of the SC-balancing circuitry. The model is, therefore, a useful tool to evaluate the performance of an SC-based cell balancer and to guide the design work in practice. In the relevantstudies, unfortunately, this topic is discussed rarely. In this paper, the series–parallel SC converter proposed in [28] and further developed in [29]–[31] is reconfigured as a new voltage-balancing circuitry. Its circuit configuration and operation principle are introduced in Section II. In addition, the model is derived based on its state analysis in Section III. Using the derived model, the voltage-balancing speed and energy conversion loss are discussed in Section IV. In Section V, a four-cell voltage equalizer prototype is built and the experimental verification is given. Finally, the conclusion is drawn in Section VI. II. S ERIES –PARALLEL SC VOLTAGE E QUALIZER A. Circuitry Description and Operation Principle As shown in Fig. 1, the series–parallel SC voltage equalizer is composed of multiple SC units. Each SC unit is made up of an SC Ci and four transistors Sai1 , Sai2 , Sbi1 , and Sbi2 . The same as the conventional two-phase SC converters [31], the SC voltage-balancing circuit is also controlled by a pair of complementary pulse signals with reasonable deadtime. There are, therefore, two clock phases Φa and Φb as shown in Fig. 2. During the phase Φa , all switches Sai1 and Sai2 (i = 1, 2, . . . , n) are turned ON, simultaneously, while switches Sbi1 and Sbi2 being OFF. As a result, the SC Ci is connected in parallel with the battery cell Bi and being charged by or discharges to the battery cell, as shown in Fig. 3. During the phase Φb , switches Sbi1 and Sbi2 are turned ON, whereas Sai1 and Sai2 are OFF. All capacitors are, therefore, connected in parallel manner and charge flows from the higher voltage capacitors to the lower voltage ones, as shown in Fig. 4. The two states operate alternatively with a high frequency and charge is transferred from the higher voltage battery cells to the lower ones, automatically, causing their voltages to change

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Fig. 4.

State circuit of a new SC equalizer during the phase Φb .

B j is higher than the initial voltage of C j , and the capacitor is therefore charged, as shown in Fig. 3 (bottom). The variations of the capacitor voltage and current during the charging process are expressed as (1) Φ a : VC j (t) = V B j − (V B j − VC j _ min )e− rC V B j − VC j _ min − t e rC Φ a : IC j (t) = (2) R where VC j _ min is the initial voltage of C j during the phase Φa , V B j is the voltage of the cell B j and it could be seen as a constant when the capacity of B j is far larger than C, and r is the sum of the ESR of the capacitor and the ON-resistance of the switches Sa j 1 and Sa j 2, i.e., r = rc + 2rs . As shown in Fig. 3 (top), in contrast, the capacitor Ck will discharge to the battery cell Bk when its initial voltage VCk_ max is higher than the battery cell’s voltage V Bk . The variations of the capacitor voltage and current during the discharging process are given as t

Fig. 1. Voltage equalization system implemented by a series–parallel SC converter.

Fig. 2.

Control signals and time slots of SC equalizers.

t

(3) Φ a : VCk (t) = V Bk + (VCk_ max − V Bk )e− rC VCk_ max − V Bk − t e rC (4) Φ a : ICk (t) = R where VCk_ max is the initial voltage of Ck and V Bk is the voltage of the cell Bk during the phase Φa . C. State Analysis in Clock Phase Φb In the duration of the phase Φb , all SCs are connected in parallel, as shown in Fig. 4. Vav (t) is the common voltage of all SC paralleled branches Vav (t) = VCi (t) − r ICi (t) Fig. 3.

State circuit of a new SC equalizer during the phase Φa .

in opposite manner and toward the average value. In order to facilitate the detailed analysis of the equalization process, the following assumptions have been made. All SCs have the same capacitance C and ESR rc , and there are the same ON -resistance rs for all switches. B. State Analysis in Clock Phase Φa In the duration of the phase Φa , charge will transfer from the battery cell B j to the capacitor C j when the voltage of

(5)

where i is ranged from 1 to n, VCi (t) is the instantaneous voltage of Ci , and ICi (t) is the instantaneous capacitor current and being positive for charging, while negative for discharging. The common voltage Vav (t) can be also expressed as Vav (t) =

n 1 [VCi (t) − r ICi (t)]. n

(6)

i=1

Using Kirchhoff’s current law (KCL) at any one of the two common points of all paralleled branches in Fig. 4, the KCL equation could be obtained as given in n i=1

ICi (t) = 0.

(7)

YE AND CHENG: MODELING AND ANALYSIS OF SERIES–PARALLEL SC VOLTAGE EQUALIZER

When the KCL (7) is substituted into (6), the common voltage Vav (t) could be further expressed by n n 1 1 qtotal Vav (t) = VCi (t) = qCi (t) = n nC nC i=1

(8)

i=1

where qCi (t) is the amount of charge stored in the capacitor Ci and qtotal is the total amount of charge of all capacitors. During the phase Φb , charge transfers from the higher voltage capacitors to the lower ones. The total amount of charge qtotal , however, is constant and the voltage Vav (t), therefore, can be seen as a constant voltage source Vav during the phase Φb . For the capacitor Ck with the initial voltage VCk_ min , it will be charged by the constant voltage Vav during the phase Φb . The variation of the capacitor voltage and current during the charging process can be expressed as

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Expanding (14) to all SC units corresponding higher voltage battery cells and (17) to all SC units corresponding lower voltage cells, respectively, a new equation could be derived and given as n

V Bi + nVav =

i=1

Φ b : VC j (t) = Vav + (VC j _ max − Vav )e− rC VC j _ max − Vav − t e rC . Φ b : IC j (t) = R t

(11) (12)

III. M ODELING FOR SC VOLTAGE E QUALIZER Assuming each switching cycle is divided by the two clock phases Φa and Φb evenly, the maximum and minimum values of capacitor voltage VC j obtained at the end of the phases Φa and Φb are given as − 1 VC j _ max = V B j − (V B j − VC j _ min )e 2rC f (13) − 1 VC j _ min = Vav + (VC j _ max − Vav )e 2rC f where f = 1/TS is the switching frequency. Different relationships of the voltages V B j and Vav can be, therefore, derived from (13) as given by V B j + Vav = VC j _ max + VC j _ min V B j − Vav = (VC j _ max − VC j _ min )

(14) 1+e

1 − 2rC f

. (15) − 1 1 − e 2rC f Similarly, the minimum and maximum values of capacitor voltage VCk are obtained at the end of the phases Φa and Φb are expressed as − 1 VCk_ min = V Bk + (VCk_ max − V Bk )e 2rC f (16) − 1 VCk_ max = Vav − (Vav − VCk_ min )e 2rC f . In addition, the different relationships of the voltages V Bk and Vav can be also derived from (16) as given in V Bk + Vav = VCk_ max + VCk_ min Vav − V Bk = (VCk_ max − VCk_ min )

(17) 1+e

1 − 2rC f

1−e

1 − 2rC f

.

(18)

VCi_ max +

i=1

n

VCi_ min .

(19)

i=1

Applying (8) at both of the start and the end moments of the phase Φb , another new equation could be derived and given as n

VCi_ max +

i=1

n

VCi_ min = 2

i=1

qtotal = 2Vav . nC

(20)

The common voltage Vav can be, therefore, derived by substituting (20) into (19) and expressed as

t

(9) Φ b : VCk (t) = Vav − (Vav − VCk_ min )e− rC Vav − VCk_ min − t e rC . (10) Φ b : ICk (t) = R Similarly, the capacitor C j with the higher initial voltage VC j _ max will discharge to the constant voltage source Vav and the capacitor voltage and current are given by

n

Vav

n 1 = V Bi . n

(21)

i=1

During one switching cycle, the average current I Bi flowing into or out of the battery cell Bi could be obtained by dividing the switching cycle TS into the total charge C(VCi_ max − VCi_ min ). Equations (15) and (18) can, therefore, be further developed as Vav = V B j − I B j RSC

(22)

Vav = V Bk + I Bk RSC

(23)

where RSC is the equivalent resistance of the SC power conversion circuit between V Bi and Vav as given −

RSC

1

1 + e 2rC f = . − 1 C f 1 − e 2rC f

(24)

Though this expression of equivalent resistance is similar to that obtained in [24]–[27], the result will be further used to evaluate the balancing speed and regarded as a design consideration in Section IV. According to the above analysis, B j represents any one battery cell with higher voltage and Bk represents any one with lower voltage. According to (21)–(23), the model of the series–parallel SC voltage equalizer with battery string could be depicted in Fig. 5, where the turns ratio of the ideal multiwinding dc transformer is n : 1 : . . . : 1. It shows the energy can be transferred from the higher voltage cells to the lower ones directly, rather than just be transferred between adjacent cells like the equalization circuit introduced in [19] and [21]. IV. M ODEL -BASED A NALYSIS OF BALANCING S PEED , E NERGY L OSS , AND D ESIGN M ETHOD A. Balancing Duration The assumptions that all battery cells have the same capacity C B , which is measured in farads, and there is a linear relationship between the cell voltage and the amount of charge stored in the cell, are made to facilitate the analysis. Using symbols V B1(0), V B2 (0), . . . , V Bn (0) as the battery cells’

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negative current means Bi is discharged to Vav . As time goes on, the cell voltage V Bi is infinitely close to Vav but they are never exactly equal. Hence, using another value V Bi (end) represents the expected value of the battery cell voltage, the duration of the balancing process can be derived from (27) and given as t = RSC C B ln

Vav − V Bi (0) . Vav − V Bi (end)

(29)

After a period of 3RC S C B to 6RC S C B , usually, the cell voltage V Bi is very close to Vav and the equalization process can be regarded as finished. It means the balancing time is mainly decided by the capacity of battery cell and the equivalent resistance of the SC equalizer. Fig. 5.

B. Energy Conversion Loss Analysis

Model of a series–parallel SC equalizer.

The energy stored in the battery string, before equalization, is expressed as 1 2 CB V Bi (0). 2 n

E(0) =

(30)

i=1

Fig. 6.

At the end, all cell voltages are balanced to the average voltage Vav and the total amount of charge is distributed evenly to all battery cells. The energy stored in the battery string is

Equivalent circuit of the voltage balancing process.

initial voltages. The amount of charge stored in all battery cells is, therefore, given as Q(0) = C B

n

V Bi (0).

(25)

i=1

With the operation of the series–parallel SC voltage equalizer, charge transfers from the higher voltage cells to the corresponding SCs during the phase Φa first. Then, this charge flows to other SCs during the phase Φb . For the next phase Φa , the same amount of charge is released to the lower battery cells. In the power transfer process, there is no charge lost or produced and the total amount of charge is, therefore, always constant. The average of the battery cells is, therefore, derived and expressed as Vav

n n 1 Q(0) 1 = V Bi (t) = = V Bi (0). n nC B n i=1

(26)

i=1

It depicts that the common voltage Vav in the model in Fig. 5 is constant for the whole equalization process even though all cell voltages are varied. Hence, the voltage equalization process could be regarded as each separated battery cell discharges to or be charged by the constant voltage source Vav , as shown in Fig. 6. The balancing process can be, therefore, expressed as −

1 2 nC B Vav . (31) 2 Substituting the average voltage expression (21) into (31), the final energy stored in the battery string is further derived as 2 n CB E(∞) = V Bi (0) . (32) 2n E(∞) =

i=1

The energy conversion loss is, therefore, derived from (30) and (32) as given by ⎧ 2⎫ n n ⎨ ⎬ CB 1 2 E loss = E(0) − E(∞) = V Bi (0) − V Bi (0) . ⎭ 2 ⎩ n i=1

i=1

(33) It can be seen that the energy conversion loss is determined by the initial cell voltage distribution and the ended state instead of the balancing speed. For instance, a supercapacitor string has four series connected cells with the initial voltages 2.5, 2.6, 2.7, and 2.8 V and the rated capacity of each cell is 1 F, the total initial energy stored in the four cells is 14.07 J. Finally, all cell voltages are fully balanced to 2.65 V and the final energy is 14.045 J. The energy conversion loss during the balancing process is, therefore, 0.025 J, which is the same as that calculated by (33).

t

(27) V Bi (t) = Vav − [Vav − V Bi (0)]e RSC C B Vav − V Bi (0) − R t C e SC B . (28) I Bi (t) = RSC For (28), the positive current I Bi (t) means the battery cell Bi is charged by the constant voltage source Vav , while the

C. Design Steps To meet different requirements of the balancing speed, circuit parameters, including the value of capacitors and switching frequency, can be determined according to the

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TABLE I E XPERIMENTAL R ESULTS OF THE C ELL -BALANCING P ROCESS

model of SC-balancing circuits. The detailed design steps are presented as follows. 1) Estimating the equivalent resistance RSC of SCs making reference to (29) RSC = treq /(mC B )

(34)

where m is a constant and can be ranged from 3 to 6, C B is the capacity of each battery cell and been measured in farads, and treq is the required balancing duration. 2) Selecting the appropriate switching frequency f according to the type of switching capacitors. 3) According to (24) and the equivalent resistance RSC calculated in the first step to calculate the value of SCs C. V. E XPERIMENTAL R ESULTS Fig. 7 gives the circuit diagram of a four-cell series–parallel SC equalizer prototype built in laboratory. Multiple pulse transformers are employed to implement the gate drivers and all switches are implemented by N-channel MOSFET (IRLU8743PBF, 30 V/3.1 m). For the SC C, two types of NICHICON NS-series electrolytic capacitor (100 μF/21 m and 220 μF/10 m) are used for the test. The pair of complementary control signals Vg_Sa and Vg_Sb is varied between 10 and 30 kHz. With the four-cell SC voltage equalizer prototype, the cell-balancing processes for two-, three-, and four-cell supercapacitor strings are measured under different parameter conditions (C = 220 μF or 100 μF; f = 10 or 30 kHz), as given in Table I. It could be concluded from each column of Table I that the equalization durations for two, three, and four cells are basically the same under the same

Fig. 7.

Four-cell equalizer built in laboratory.

experimental parameters. It means the balancing time is independent of the cell number and this conclusion is consistent with the model given in Fig. 5. The energy loss calculated according to the initial and final voltages is also added in each subfigure. It can be found from each row that the energy loss is almost independent of the balancing time. Fig. 8 shows the voltage waveforms of the four-series supercapacitors during the charging and discharging processes

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Fig. 8. Voltage waveforms of four-series supercapacitors with the balancer prototype. (a) Charging process. (b) Discharging process.

with the constant charging/discharging current 2 A. With the operation of the proposed prototype voltage equalizer during the charging/discharging process, the initial difference of cell voltages is eliminated ultimately. VI. C ONCLUSION The circuit configuration and operation principle of the series–parallel SC voltage equalizer are analyzed in this paper. Based on the detail state analysis, its model depicted as an ideal dc multiwinding transformer with multiple equivalent resistors is derived. The key of the model is the value of the equivalent resistor that related to the switching frequency and capacitance. Based on the model, the voltage equalization speed can be determined. It is very useful in practice to decide the switching frequency and select appropriate SCs to meet the different balancing speed requirements. The energy conversion loss is also discussed based on the derived model. Furthermore, a four-cell equalizer prototype is built in laboratory to verify the theoretical analysis. For the further works, the model-based analysis and design method will be developed and applied to other SC-based voltage equalization systems. R EFERENCES [1] J. Chatzakis, K. Kalaitzakis, N. C. Voulgaris, and S. N. Manias, “Designing a new generalized battery management system,” IEEE Trans. Ind. Electron., vol. 50, no. 5, pp. 990–999, Oct. 2013.

[2] N. H. Kutkut, H. L. N. Wiegman, D. M. Divan, and D. W. Novotny, “Design considerations for charge equalization of an electric vehicle battery system,” IEEE Trans. Ind. Electron., vol. 35, no. 1, pp. 28–35, Jan./Feb. 1999. [3] Y.-S. Lee and M.-W. Cheng, “Intelligent control battery equalization for series connected lithium-ion battery strings,” IEEE Trans. Ind. Electron., vol. 52, no. 5, pp. 1297–1307, Oct. 2005. [4] K. W. E. Cheng, B. P. Divakar, H. Wu, D. Kai, and H. F. Ho, “Batterymanagement system (BMS) and SOC development for electrical vehicles,” IEEE Trans. Veh. Technol., vol. 60, no. 1, pp. 76–88, Jan. 2011. [5] S. Wen, “Cell balancing buys extra run time and battery life,” Analog Appl. J., pp. 14–18, 2009. [Online]. Available: http:// focus.ti.com/lit/an/slyt322/slyt322.pdf [6] J. Cao, N. Schofield, and A. Emadi, “Battery balancing methods: A comprehensive review,” in Proc. IEEE Veh. Power Propuls. Conf., Harbin, China, Sep. 2008, pp. 1–6. [7] A. Xu, S. Xie, and X. Liu, “Dynamic voltage equalization for seriesconnected ultracapacitors in EV/HEV applications,” IEEE Trans. Veh. Technol., vol. 58, no. 8, pp. 3981–3987, Oct. 2009. [8] M. Uno and K. Tanaka, “Single-switch multioutput charger using voltage multiplier for series-connected lithium-ion battery/supercapacitor equalization,” IEEE Trans. Ind. Electron., vol. 60, no. 8, pp. 3227–3239, Aug. 2013. [9] C.-H. Kim, M.-Y. Kim, and G.-W. Moon, “A modularized charge equalizer using a battery monitoring IC for series-connected Li-ion battery strings in electric vehicles,” IEEE Trans. Power Electron., vol. 28, no. 8, pp. 3779–3787, Aug. 2013. [10] Y.-S. Lee and G.-T. Cheng, “Quasi-resonant zero-current-switching bidirectional converter for battery equalization applications,” IEEE Trans. Power Electron., vol. 21, no. 5, pp. 1213–1224, Sep. 2006. [11] Y. Levron, D. R. Clement, B. Choi, C. Olalla, and D. Maksimovic, “Control of submodule integrated converters in the isolated-port differential power-processing photovoltaic architecture,” IEEE J. Emerg. Sel. Topics Power Electron., vol. 2, no. 4, pp. 821–832, Dec. 2014. [12] Y.-H. Hsieh, T.-J. Liang, S.-M. O. Chen, W.-Y. Horng, and Y.-Y. Chung, “A novel high-efficiency compact-size low-cost balancing method for series-connected battery applications,” IEEE Trans. Power Electron., vol. 28, no. 12, pp. 5927–5939, Dec. 2013. [13] C. Olalla, C. Deline, D. Clement, Y. Levron, M. Rodriguez, and D. Maksimovic, “Performance of power-limited differential power processing architectures in mismatched PV systems,” IEEE Trans. Power Electron., vol. 30, no. 2, pp. 618–631, Feb. 2015. [14] A. M. Imtiaz and F. H. Khan, “‘Time shared flyback converter’ based regenerative cell balancing technique for series connected Li-ion battery strings,” IEEE Trans. Power Electron., vol. 28, no. 12, pp. 5960–5975, Dec. 2013. [15] D. Costinett et al., “Active balancing system for electric vehicles with incorporated low voltage bus,” in Proc. 29th IEEE Appl. Power Electron. Conf. Expo., Mar. 2014, pp. 3230–3236. [16] M. Muneeb ur Rehman et al., “Modular approach for continuous celllevel balancing to improve performance of large battery packs,” in Proc. IEEE Energy Convers. Congr. Expo., Sep. 2014, pp. 4327–4334. [17] M. Uno and K. Tanaka, “Double-switch single-transformer cell voltage equalizer using a half-bridge inverter and a voltage multiplier for seriesconnected supercapacitors,” IEEE Trans. Veh. Technol., vol. 61, no. 9, pp. 3920–3930, Nov. 2012. [18] S.-H. Park, K.-B. Park, H.-S. Kim, G.-W. Moon, and M.-J. Youn, “Single-magnetic cell-to-cell charge equalization converter with reduced number of transformer windings,” IEEE Trans. Power Electron., vol. 27, no. 6, pp. 2900–2911, Jun. 2012. [19] C. Pascual and P. T. Krein, “Switched capacitor system for automatic series battery equalization,” in Proc. 12th Appl. Power Electron. Conf. Expo., Feb. 1997, pp. 848–854. [20] G. A. Kobzev, “Switched-capacitor systems for battery equalization,” in Proc. 6th Int. Sci. Pract. Conf. Students, Post-Graduates Young Sci. Modern Tech. Technol., 2000, pp. 57–59. [21] Y. Yuanmao, K. W. E. Cheng, and Y. P. B. Yeung, “Zero-current switching switched-capacitor zero-voltage-gap automatic equalization system for series battery string,” IEEE Trans. Power Electron., vol. 27, no. 7, pp. 3234–3242, Jul. 2012. [22] K. Sano and H. Fujita, “A resonant switched-capacitor converter for voltage balancing of series-connected capacitors,” in Proc. Int. Conf. Power Electron. Drive Syst., Nov. 2009, pp. 683–688. [23] A. C. Baughman and M. Ferdowsi, “Double-tiered switched-capacitor battery charge equalization technique,” IEEE Trans. Ind. Electron., vol. 55, no. 6, pp. 2277–2285, Jun. 2008.

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[24] M. S. Makowski and D. Maksimovic, “Performance limits of switchedcapacitor DC-DC converters,” in Proc. 26th Annu. IEEE/PESC, vol. 2. Atlanta, GA, USA, Jun. 1995, pp. 1215–1221. [25] A. Ioinovici, “Switched-capacitor power electronics circuits,” IEEE Circuits Syst. Mag., vol. 1, no. 3, pp. 37–42, Sep. 2001. [26] S. Ben-Yaakov and M. Evzelman, “Generic and unified model of switched capacitor converters,” in Proc. IEEE Energy Convers. Congr. Expo., Sep. 2009, pp. 3501–3508. [27] J. M. Henry and J. W. Kimball, “Practical performance analysis of complex switched-capacitor converters,” IEEE Trans. Power Electron., vol. 26, no. 1, pp. 127–136, Jan. 2011. [28] J. S. Brugler, “Theoretical performance of voltage multiplier circuits,” IEEE J. Solid-State Circuits, vol. SSC-6, no. 3, pp. 132–135, Jun. 1971. [29] M. D. Seeman and S. R. Sanders, “Analysis and optimization of switched-capacitor DC–DC converters,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 841–851, Mar. 2008. [30] T. M. Van Breussegem, M. Wens, D. Geukens, D. Geys, and M. S. J. Steyaert, “Area-driven optimisation of switched-capacitor DC/DC converters,” Electron. Lett., vol. 44, no. 25, pp. 1488–1489, Dec. 2008. [31] T. Tanzawa, “On two-phase switched-capacitor multipliers with minimum circuit area,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 10, pp. 2602–2608, Oct. 2010. [32] Y. Ye and K. W. E. Cheng, “Voltage-gap modeling method for singlestage switched-capacitor converters,” IEEE J. Emerg. Sel. Topics Power Electron., vol. 2, no. 4, pp. 808–813, Dec. 2014.

Yuanmao Ye received the B.Sc. degree in electrical engineering from the University of Jinan, Jinan, China, in 2007, and the M.Sc. degree in control theory and control engineering from the South China University of Technology, Guangzhou, China, in 2010. He is currently pursuing the Ph.D. degree with the Department of Electrical Engineering, Faculty of Engineering, The Hong Kong Polytechnic University, Hong Kong. He was with the Department of Electrical Engineering, Faculty of Engineering, The Hong Kong Polytechnic University, from 2010 to 2014, as a Research Assistant. His current research interests include various dc–dc power converters, switchedcapacitor technique and its applications, multilevel inverters, power conversion and energy management for smart-grids, and protection and control techniques for dc distribution.

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Ka Wai E. Cheng (M’90–SM’06) received the B.Sc. and Ph.D. degrees from the University of Bath, Bath, U.K., in 1987 and 1990, respectively. He was with Lucas Aerospace, Birmingham, U.K., as a Principal Engineer, where he led a number of power electronics projects, before joining The Hong Kong Polytechnic University, Hong Kong, in 1997. He has written more than 250 papers and seven books. He is currently a Professor and the Director of the Power Electronics Research Centre with The Hong Kong Polytechnic University. His current research interests include all aspects of power electronics, motor drives, electromagnetic interference, electric vehicle, battery management, and energy saving. Dr. Cheng was a recipient of the IEE Sebastian Z De Ferranti Premium Award in 1995, the Outstanding Consultancy Award in 2000, the Faculty Merit Award for best teaching from The Hong Kong Polytechnic University in 2003, the Faculty Engineering Industrial and Engineering Services Grant Achievement Award in 2006, the Brussels Innova Energy Gold Medal with Mention in 2007, the Consumer Product Design Award in 2008, the Electric Vehicle Team Merit Award of the Faculty in 2009, the Geneva Invention Expo Silver Medal in 2011, and the Eco Star Award in 2012.

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Modeling and Analysis of Series–Parallel Switched-Capacitor Voltage Equalizer for Battery/Supercapacitor Strings Yuanmao Ye and Ka Wai E. Cheng, Senior Member, IEEE Abstract— A series–parallel switched-capacitor (SC) power converter is reconfigured as a new voltage equalization circuitry for series-connected batteries or supercapacitors in this paper. The model of the new voltage equalizer is derived and successfully used to analyze the equalization speed and the energy loss. It is a very useful tool to analyze and design the SC-based equalization systems to meet different balancing speed requirements. The analysis and modeling methods can be extended to other SC-based voltage-balancing systems. A prototype is built and the experimental results are provided to confirm the theoretical analysis and the modeling method. Index Terms— Battery-management system, model, switched-capacitor (SC), voltage equalization.

I. I NTRODUCTION ARGE numbers of batteries or supercapacitor cells are usually connected in series to meet high operating voltage requirements. All series-connected cells are, therefore, charged and discharged together. Due to the nonuniform properties of individual cell, repeated charging and discharging will cause small imbalance in the form of unequal voltages existed among cells [1], [2]. To overcome this problem, the voltage-balancing device, also known as a voltage equalizer, is an indispensable piece of equipment in battery-management systems [1]–[4]. The simplest method to equalize battery cells’ voltage is implemented using resistors to consume the exceed energy of higher voltage cells in the form of heat [5], [6]. The main drawbacks of this method are energy waste and the temperature rise. In order to avoid the waste of energy during the voltage-balancing process and to make every cell providing the best performance, various active balancers are designed based on switched-mode power conversion circuits in [7]–[18]. The common design philosophy of these strategies is using power converters to transfer energy from the higher voltage cells to the lower ones. Another type of active cell-balancing methods is implemented by employing switched capacitor (SC) as the

L

Manuscript received October 10, 2014; revised December 29, 2014 and February 14, 2015; accepted March 26, 2015. Date of publication April 1, 2015; date of current version October 29, 2015. This work was supported in part by the Innovation and Technology Fund through the Hong Kong Technology and Innovation Commission and in part by JL Ecopro Technical Ltd., Hong Kong, under Project UIM245. Recommended for publication by Associate Editor Sudip K. Mazumder. The authors are with the Department of Electrical Engineering, The Hong Kong Polytechnic University, Hong Kong (e-mail: [email protected] connect.polyu.hk; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JESTPE.2015.2418339

energy-transfer component [19]–[23]. It has the advantages of small size and cost effectiveness, as well as easy control. According to [24]–[32], the performance of SC power conversion circuits can be seen as a combination of an ideal transformer and an equivalent resistor. It shows the power transfer capacity of SC power conversion circuits mainly depends on the switching frequency and the value of SCs. Specific to the SC-based voltage equalization systems, the voltage-balancing speed can be directly reflected by the model of the SC-balancing circuitry. The model is, therefore, a useful tool to evaluate the performance of an SC-based cell balancer and to guide the design work in practice. In the relevantstudies, unfortunately, this topic is discussed rarely. In this paper, the series–parallel SC converter proposed in [28] and further developed in [29]–[31] is reconfigured as a new voltage-balancing circuitry. Its circuit configuration and operation principle are introduced in Section II. In addition, the model is derived based on its state analysis in Section III. Using the derived model, the voltage-balancing speed and energy conversion loss are discussed in Section IV. In Section V, a four-cell voltage equalizer prototype is built and the experimental verification is given. Finally, the conclusion is drawn in Section VI. II. S ERIES –PARALLEL SC VOLTAGE E QUALIZER A. Circuitry Description and Operation Principle As shown in Fig. 1, the series–parallel SC voltage equalizer is composed of multiple SC units. Each SC unit is made up of an SC Ci and four transistors Sai1 , Sai2 , Sbi1 , and Sbi2 . The same as the conventional two-phase SC converters [31], the SC voltage-balancing circuit is also controlled by a pair of complementary pulse signals with reasonable deadtime. There are, therefore, two clock phases Φa and Φb as shown in Fig. 2. During the phase Φa , all switches Sai1 and Sai2 (i = 1, 2, . . . , n) are turned ON, simultaneously, while switches Sbi1 and Sbi2 being OFF. As a result, the SC Ci is connected in parallel with the battery cell Bi and being charged by or discharges to the battery cell, as shown in Fig. 3. During the phase Φb , switches Sbi1 and Sbi2 are turned ON, whereas Sai1 and Sai2 are OFF. All capacitors are, therefore, connected in parallel manner and charge flows from the higher voltage capacitors to the lower voltage ones, as shown in Fig. 4. The two states operate alternatively with a high frequency and charge is transferred from the higher voltage battery cells to the lower ones, automatically, causing their voltages to change

2168-6777 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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Fig. 4.

State circuit of a new SC equalizer during the phase Φb .

B j is higher than the initial voltage of C j , and the capacitor is therefore charged, as shown in Fig. 3 (bottom). The variations of the capacitor voltage and current during the charging process are expressed as (1) Φ a : VC j (t) = V B j − (V B j − VC j _ min )e− rC V B j − VC j _ min − t e rC Φ a : IC j (t) = (2) R where VC j _ min is the initial voltage of C j during the phase Φa , V B j is the voltage of the cell B j and it could be seen as a constant when the capacity of B j is far larger than C, and r is the sum of the ESR of the capacitor and the ON-resistance of the switches Sa j 1 and Sa j 2, i.e., r = rc + 2rs . As shown in Fig. 3 (top), in contrast, the capacitor Ck will discharge to the battery cell Bk when its initial voltage VCk_ max is higher than the battery cell’s voltage V Bk . The variations of the capacitor voltage and current during the discharging process are given as t

Fig. 1. Voltage equalization system implemented by a series–parallel SC converter.

Fig. 2.

Control signals and time slots of SC equalizers.

t

(3) Φ a : VCk (t) = V Bk + (VCk_ max − V Bk )e− rC VCk_ max − V Bk − t e rC (4) Φ a : ICk (t) = R where VCk_ max is the initial voltage of Ck and V Bk is the voltage of the cell Bk during the phase Φa . C. State Analysis in Clock Phase Φb In the duration of the phase Φb , all SCs are connected in parallel, as shown in Fig. 4. Vav (t) is the common voltage of all SC paralleled branches Vav (t) = VCi (t) − r ICi (t) Fig. 3.

State circuit of a new SC equalizer during the phase Φa .

in opposite manner and toward the average value. In order to facilitate the detailed analysis of the equalization process, the following assumptions have been made. All SCs have the same capacitance C and ESR rc , and there are the same ON -resistance rs for all switches. B. State Analysis in Clock Phase Φa In the duration of the phase Φa , charge will transfer from the battery cell B j to the capacitor C j when the voltage of

(5)

where i is ranged from 1 to n, VCi (t) is the instantaneous voltage of Ci , and ICi (t) is the instantaneous capacitor current and being positive for charging, while negative for discharging. The common voltage Vav (t) can be also expressed as Vav (t) =

n 1 [VCi (t) − r ICi (t)]. n

(6)

i=1

Using Kirchhoff’s current law (KCL) at any one of the two common points of all paralleled branches in Fig. 4, the KCL equation could be obtained as given in n i=1

ICi (t) = 0.

(7)

YE AND CHENG: MODELING AND ANALYSIS OF SERIES–PARALLEL SC VOLTAGE EQUALIZER

When the KCL (7) is substituted into (6), the common voltage Vav (t) could be further expressed by n n 1 1 qtotal Vav (t) = VCi (t) = qCi (t) = n nC nC i=1

(8)

i=1

where qCi (t) is the amount of charge stored in the capacitor Ci and qtotal is the total amount of charge of all capacitors. During the phase Φb , charge transfers from the higher voltage capacitors to the lower ones. The total amount of charge qtotal , however, is constant and the voltage Vav (t), therefore, can be seen as a constant voltage source Vav during the phase Φb . For the capacitor Ck with the initial voltage VCk_ min , it will be charged by the constant voltage Vav during the phase Φb . The variation of the capacitor voltage and current during the charging process can be expressed as

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Expanding (14) to all SC units corresponding higher voltage battery cells and (17) to all SC units corresponding lower voltage cells, respectively, a new equation could be derived and given as n

V Bi + nVav =

i=1

Φ b : VC j (t) = Vav + (VC j _ max − Vav )e− rC VC j _ max − Vav − t e rC . Φ b : IC j (t) = R t

(11) (12)

III. M ODELING FOR SC VOLTAGE E QUALIZER Assuming each switching cycle is divided by the two clock phases Φa and Φb evenly, the maximum and minimum values of capacitor voltage VC j obtained at the end of the phases Φa and Φb are given as − 1 VC j _ max = V B j − (V B j − VC j _ min )e 2rC f (13) − 1 VC j _ min = Vav + (VC j _ max − Vav )e 2rC f where f = 1/TS is the switching frequency. Different relationships of the voltages V B j and Vav can be, therefore, derived from (13) as given by V B j + Vav = VC j _ max + VC j _ min V B j − Vav = (VC j _ max − VC j _ min )

(14) 1+e

1 − 2rC f

. (15) − 1 1 − e 2rC f Similarly, the minimum and maximum values of capacitor voltage VCk are obtained at the end of the phases Φa and Φb are expressed as − 1 VCk_ min = V Bk + (VCk_ max − V Bk )e 2rC f (16) − 1 VCk_ max = Vav − (Vav − VCk_ min )e 2rC f . In addition, the different relationships of the voltages V Bk and Vav can be also derived from (16) as given in V Bk + Vav = VCk_ max + VCk_ min Vav − V Bk = (VCk_ max − VCk_ min )

(17) 1+e

1 − 2rC f

1−e

1 − 2rC f

.

(18)

VCi_ max +

i=1

n

VCi_ min .

(19)

i=1

Applying (8) at both of the start and the end moments of the phase Φb , another new equation could be derived and given as n

VCi_ max +

i=1

n

VCi_ min = 2

i=1

qtotal = 2Vav . nC

(20)

The common voltage Vav can be, therefore, derived by substituting (20) into (19) and expressed as

t

(9) Φ b : VCk (t) = Vav − (Vav − VCk_ min )e− rC Vav − VCk_ min − t e rC . (10) Φ b : ICk (t) = R Similarly, the capacitor C j with the higher initial voltage VC j _ max will discharge to the constant voltage source Vav and the capacitor voltage and current are given by

n

Vav

n 1 = V Bi . n

(21)

i=1

During one switching cycle, the average current I Bi flowing into or out of the battery cell Bi could be obtained by dividing the switching cycle TS into the total charge C(VCi_ max − VCi_ min ). Equations (15) and (18) can, therefore, be further developed as Vav = V B j − I B j RSC

(22)

Vav = V Bk + I Bk RSC

(23)

where RSC is the equivalent resistance of the SC power conversion circuit between V Bi and Vav as given −

RSC

1

1 + e 2rC f = . − 1 C f 1 − e 2rC f

(24)

Though this expression of equivalent resistance is similar to that obtained in [24]–[27], the result will be further used to evaluate the balancing speed and regarded as a design consideration in Section IV. According to the above analysis, B j represents any one battery cell with higher voltage and Bk represents any one with lower voltage. According to (21)–(23), the model of the series–parallel SC voltage equalizer with battery string could be depicted in Fig. 5, where the turns ratio of the ideal multiwinding dc transformer is n : 1 : . . . : 1. It shows the energy can be transferred from the higher voltage cells to the lower ones directly, rather than just be transferred between adjacent cells like the equalization circuit introduced in [19] and [21]. IV. M ODEL -BASED A NALYSIS OF BALANCING S PEED , E NERGY L OSS , AND D ESIGN M ETHOD A. Balancing Duration The assumptions that all battery cells have the same capacity C B , which is measured in farads, and there is a linear relationship between the cell voltage and the amount of charge stored in the cell, are made to facilitate the analysis. Using symbols V B1(0), V B2 (0), . . . , V Bn (0) as the battery cells’

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negative current means Bi is discharged to Vav . As time goes on, the cell voltage V Bi is infinitely close to Vav but they are never exactly equal. Hence, using another value V Bi (end) represents the expected value of the battery cell voltage, the duration of the balancing process can be derived from (27) and given as t = RSC C B ln

Vav − V Bi (0) . Vav − V Bi (end)

(29)

After a period of 3RC S C B to 6RC S C B , usually, the cell voltage V Bi is very close to Vav and the equalization process can be regarded as finished. It means the balancing time is mainly decided by the capacity of battery cell and the equivalent resistance of the SC equalizer. Fig. 5.

B. Energy Conversion Loss Analysis

Model of a series–parallel SC equalizer.

The energy stored in the battery string, before equalization, is expressed as 1 2 CB V Bi (0). 2 n

E(0) =

(30)

i=1

Fig. 6.

At the end, all cell voltages are balanced to the average voltage Vav and the total amount of charge is distributed evenly to all battery cells. The energy stored in the battery string is

Equivalent circuit of the voltage balancing process.

initial voltages. The amount of charge stored in all battery cells is, therefore, given as Q(0) = C B

n

V Bi (0).

(25)

i=1

With the operation of the series–parallel SC voltage equalizer, charge transfers from the higher voltage cells to the corresponding SCs during the phase Φa first. Then, this charge flows to other SCs during the phase Φb . For the next phase Φa , the same amount of charge is released to the lower battery cells. In the power transfer process, there is no charge lost or produced and the total amount of charge is, therefore, always constant. The average of the battery cells is, therefore, derived and expressed as Vav

n n 1 Q(0) 1 = V Bi (t) = = V Bi (0). n nC B n i=1

(26)

i=1

It depicts that the common voltage Vav in the model in Fig. 5 is constant for the whole equalization process even though all cell voltages are varied. Hence, the voltage equalization process could be regarded as each separated battery cell discharges to or be charged by the constant voltage source Vav , as shown in Fig. 6. The balancing process can be, therefore, expressed as −

1 2 nC B Vav . (31) 2 Substituting the average voltage expression (21) into (31), the final energy stored in the battery string is further derived as 2 n CB E(∞) = V Bi (0) . (32) 2n E(∞) =

i=1

The energy conversion loss is, therefore, derived from (30) and (32) as given by ⎧ 2⎫ n n ⎨ ⎬ CB 1 2 E loss = E(0) − E(∞) = V Bi (0) − V Bi (0) . ⎭ 2 ⎩ n i=1

i=1

(33) It can be seen that the energy conversion loss is determined by the initial cell voltage distribution and the ended state instead of the balancing speed. For instance, a supercapacitor string has four series connected cells with the initial voltages 2.5, 2.6, 2.7, and 2.8 V and the rated capacity of each cell is 1 F, the total initial energy stored in the four cells is 14.07 J. Finally, all cell voltages are fully balanced to 2.65 V and the final energy is 14.045 J. The energy conversion loss during the balancing process is, therefore, 0.025 J, which is the same as that calculated by (33).

t

(27) V Bi (t) = Vav − [Vav − V Bi (0)]e RSC C B Vav − V Bi (0) − R t C e SC B . (28) I Bi (t) = RSC For (28), the positive current I Bi (t) means the battery cell Bi is charged by the constant voltage source Vav , while the

C. Design Steps To meet different requirements of the balancing speed, circuit parameters, including the value of capacitors and switching frequency, can be determined according to the

YE AND CHENG: MODELING AND ANALYSIS OF SERIES–PARALLEL SC VOLTAGE EQUALIZER

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TABLE I E XPERIMENTAL R ESULTS OF THE C ELL -BALANCING P ROCESS

model of SC-balancing circuits. The detailed design steps are presented as follows. 1) Estimating the equivalent resistance RSC of SCs making reference to (29) RSC = treq /(mC B )

(34)

where m is a constant and can be ranged from 3 to 6, C B is the capacity of each battery cell and been measured in farads, and treq is the required balancing duration. 2) Selecting the appropriate switching frequency f according to the type of switching capacitors. 3) According to (24) and the equivalent resistance RSC calculated in the first step to calculate the value of SCs C. V. E XPERIMENTAL R ESULTS Fig. 7 gives the circuit diagram of a four-cell series–parallel SC equalizer prototype built in laboratory. Multiple pulse transformers are employed to implement the gate drivers and all switches are implemented by N-channel MOSFET (IRLU8743PBF, 30 V/3.1 m). For the SC C, two types of NICHICON NS-series electrolytic capacitor (100 μF/21 m and 220 μF/10 m) are used for the test. The pair of complementary control signals Vg_Sa and Vg_Sb is varied between 10 and 30 kHz. With the four-cell SC voltage equalizer prototype, the cell-balancing processes for two-, three-, and four-cell supercapacitor strings are measured under different parameter conditions (C = 220 μF or 100 μF; f = 10 or 30 kHz), as given in Table I. It could be concluded from each column of Table I that the equalization durations for two, three, and four cells are basically the same under the same

Fig. 7.

Four-cell equalizer built in laboratory.

experimental parameters. It means the balancing time is independent of the cell number and this conclusion is consistent with the model given in Fig. 5. The energy loss calculated according to the initial and final voltages is also added in each subfigure. It can be found from each row that the energy loss is almost independent of the balancing time. Fig. 8 shows the voltage waveforms of the four-series supercapacitors during the charging and discharging processes

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Fig. 8. Voltage waveforms of four-series supercapacitors with the balancer prototype. (a) Charging process. (b) Discharging process.

with the constant charging/discharging current 2 A. With the operation of the proposed prototype voltage equalizer during the charging/discharging process, the initial difference of cell voltages is eliminated ultimately. VI. C ONCLUSION The circuit configuration and operation principle of the series–parallel SC voltage equalizer are analyzed in this paper. Based on the detail state analysis, its model depicted as an ideal dc multiwinding transformer with multiple equivalent resistors is derived. The key of the model is the value of the equivalent resistor that related to the switching frequency and capacitance. Based on the model, the voltage equalization speed can be determined. It is very useful in practice to decide the switching frequency and select appropriate SCs to meet the different balancing speed requirements. The energy conversion loss is also discussed based on the derived model. Furthermore, a four-cell equalizer prototype is built in laboratory to verify the theoretical analysis. For the further works, the model-based analysis and design method will be developed and applied to other SC-based voltage equalization systems. R EFERENCES [1] J. Chatzakis, K. Kalaitzakis, N. C. Voulgaris, and S. N. Manias, “Designing a new generalized battery management system,” IEEE Trans. Ind. Electron., vol. 50, no. 5, pp. 990–999, Oct. 2013.

[2] N. H. Kutkut, H. L. N. Wiegman, D. M. Divan, and D. W. Novotny, “Design considerations for charge equalization of an electric vehicle battery system,” IEEE Trans. Ind. Electron., vol. 35, no. 1, pp. 28–35, Jan./Feb. 1999. [3] Y.-S. Lee and M.-W. Cheng, “Intelligent control battery equalization for series connected lithium-ion battery strings,” IEEE Trans. Ind. Electron., vol. 52, no. 5, pp. 1297–1307, Oct. 2005. [4] K. W. E. Cheng, B. P. Divakar, H. Wu, D. Kai, and H. F. Ho, “Batterymanagement system (BMS) and SOC development for electrical vehicles,” IEEE Trans. Veh. Technol., vol. 60, no. 1, pp. 76–88, Jan. 2011. [5] S. Wen, “Cell balancing buys extra run time and battery life,” Analog Appl. J., pp. 14–18, 2009. [Online]. Available: http:// focus.ti.com/lit/an/slyt322/slyt322.pdf [6] J. Cao, N. Schofield, and A. Emadi, “Battery balancing methods: A comprehensive review,” in Proc. IEEE Veh. Power Propuls. Conf., Harbin, China, Sep. 2008, pp. 1–6. [7] A. Xu, S. Xie, and X. Liu, “Dynamic voltage equalization for seriesconnected ultracapacitors in EV/HEV applications,” IEEE Trans. Veh. Technol., vol. 58, no. 8, pp. 3981–3987, Oct. 2009. [8] M. Uno and K. Tanaka, “Single-switch multioutput charger using voltage multiplier for series-connected lithium-ion battery/supercapacitor equalization,” IEEE Trans. Ind. Electron., vol. 60, no. 8, pp. 3227–3239, Aug. 2013. [9] C.-H. Kim, M.-Y. Kim, and G.-W. Moon, “A modularized charge equalizer using a battery monitoring IC for series-connected Li-ion battery strings in electric vehicles,” IEEE Trans. Power Electron., vol. 28, no. 8, pp. 3779–3787, Aug. 2013. [10] Y.-S. Lee and G.-T. Cheng, “Quasi-resonant zero-current-switching bidirectional converter for battery equalization applications,” IEEE Trans. Power Electron., vol. 21, no. 5, pp. 1213–1224, Sep. 2006. [11] Y. Levron, D. R. Clement, B. Choi, C. Olalla, and D. Maksimovic, “Control of submodule integrated converters in the isolated-port differential power-processing photovoltaic architecture,” IEEE J. Emerg. Sel. Topics Power Electron., vol. 2, no. 4, pp. 821–832, Dec. 2014. [12] Y.-H. Hsieh, T.-J. Liang, S.-M. O. Chen, W.-Y. Horng, and Y.-Y. Chung, “A novel high-efficiency compact-size low-cost balancing method for series-connected battery applications,” IEEE Trans. Power Electron., vol. 28, no. 12, pp. 5927–5939, Dec. 2013. [13] C. Olalla, C. Deline, D. Clement, Y. Levron, M. Rodriguez, and D. Maksimovic, “Performance of power-limited differential power processing architectures in mismatched PV systems,” IEEE Trans. Power Electron., vol. 30, no. 2, pp. 618–631, Feb. 2015. [14] A. M. Imtiaz and F. H. Khan, “‘Time shared flyback converter’ based regenerative cell balancing technique for series connected Li-ion battery strings,” IEEE Trans. Power Electron., vol. 28, no. 12, pp. 5960–5975, Dec. 2013. [15] D. Costinett et al., “Active balancing system for electric vehicles with incorporated low voltage bus,” in Proc. 29th IEEE Appl. Power Electron. Conf. Expo., Mar. 2014, pp. 3230–3236. [16] M. Muneeb ur Rehman et al., “Modular approach for continuous celllevel balancing to improve performance of large battery packs,” in Proc. IEEE Energy Convers. Congr. Expo., Sep. 2014, pp. 4327–4334. [17] M. Uno and K. Tanaka, “Double-switch single-transformer cell voltage equalizer using a half-bridge inverter and a voltage multiplier for seriesconnected supercapacitors,” IEEE Trans. Veh. Technol., vol. 61, no. 9, pp. 3920–3930, Nov. 2012. [18] S.-H. Park, K.-B. Park, H.-S. Kim, G.-W. Moon, and M.-J. Youn, “Single-magnetic cell-to-cell charge equalization converter with reduced number of transformer windings,” IEEE Trans. Power Electron., vol. 27, no. 6, pp. 2900–2911, Jun. 2012. [19] C. Pascual and P. T. Krein, “Switched capacitor system for automatic series battery equalization,” in Proc. 12th Appl. Power Electron. Conf. Expo., Feb. 1997, pp. 848–854. [20] G. A. Kobzev, “Switched-capacitor systems for battery equalization,” in Proc. 6th Int. Sci. Pract. Conf. Students, Post-Graduates Young Sci. Modern Tech. Technol., 2000, pp. 57–59. [21] Y. Yuanmao, K. W. E. Cheng, and Y. P. B. Yeung, “Zero-current switching switched-capacitor zero-voltage-gap automatic equalization system for series battery string,” IEEE Trans. Power Electron., vol. 27, no. 7, pp. 3234–3242, Jul. 2012. [22] K. Sano and H. Fujita, “A resonant switched-capacitor converter for voltage balancing of series-connected capacitors,” in Proc. Int. Conf. Power Electron. Drive Syst., Nov. 2009, pp. 683–688. [23] A. C. Baughman and M. Ferdowsi, “Double-tiered switched-capacitor battery charge equalization technique,” IEEE Trans. Ind. Electron., vol. 55, no. 6, pp. 2277–2285, Jun. 2008.

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[24] M. S. Makowski and D. Maksimovic, “Performance limits of switchedcapacitor DC-DC converters,” in Proc. 26th Annu. IEEE/PESC, vol. 2. Atlanta, GA, USA, Jun. 1995, pp. 1215–1221. [25] A. Ioinovici, “Switched-capacitor power electronics circuits,” IEEE Circuits Syst. Mag., vol. 1, no. 3, pp. 37–42, Sep. 2001. [26] S. Ben-Yaakov and M. Evzelman, “Generic and unified model of switched capacitor converters,” in Proc. IEEE Energy Convers. Congr. Expo., Sep. 2009, pp. 3501–3508. [27] J. M. Henry and J. W. Kimball, “Practical performance analysis of complex switched-capacitor converters,” IEEE Trans. Power Electron., vol. 26, no. 1, pp. 127–136, Jan. 2011. [28] J. S. Brugler, “Theoretical performance of voltage multiplier circuits,” IEEE J. Solid-State Circuits, vol. SSC-6, no. 3, pp. 132–135, Jun. 1971. [29] M. D. Seeman and S. R. Sanders, “Analysis and optimization of switched-capacitor DC–DC converters,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 841–851, Mar. 2008. [30] T. M. Van Breussegem, M. Wens, D. Geukens, D. Geys, and M. S. J. Steyaert, “Area-driven optimisation of switched-capacitor DC/DC converters,” Electron. Lett., vol. 44, no. 25, pp. 1488–1489, Dec. 2008. [31] T. Tanzawa, “On two-phase switched-capacitor multipliers with minimum circuit area,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 10, pp. 2602–2608, Oct. 2010. [32] Y. Ye and K. W. E. Cheng, “Voltage-gap modeling method for singlestage switched-capacitor converters,” IEEE J. Emerg. Sel. Topics Power Electron., vol. 2, no. 4, pp. 808–813, Dec. 2014.

Yuanmao Ye received the B.Sc. degree in electrical engineering from the University of Jinan, Jinan, China, in 2007, and the M.Sc. degree in control theory and control engineering from the South China University of Technology, Guangzhou, China, in 2010. He is currently pursuing the Ph.D. degree with the Department of Electrical Engineering, Faculty of Engineering, The Hong Kong Polytechnic University, Hong Kong. He was with the Department of Electrical Engineering, Faculty of Engineering, The Hong Kong Polytechnic University, from 2010 to 2014, as a Research Assistant. His current research interests include various dc–dc power converters, switchedcapacitor technique and its applications, multilevel inverters, power conversion and energy management for smart-grids, and protection and control techniques for dc distribution.

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Ka Wai E. Cheng (M’90–SM’06) received the B.Sc. and Ph.D. degrees from the University of Bath, Bath, U.K., in 1987 and 1990, respectively. He was with Lucas Aerospace, Birmingham, U.K., as a Principal Engineer, where he led a number of power electronics projects, before joining The Hong Kong Polytechnic University, Hong Kong, in 1997. He has written more than 250 papers and seven books. He is currently a Professor and the Director of the Power Electronics Research Centre with The Hong Kong Polytechnic University. His current research interests include all aspects of power electronics, motor drives, electromagnetic interference, electric vehicle, battery management, and energy saving. Dr. Cheng was a recipient of the IEE Sebastian Z De Ferranti Premium Award in 1995, the Outstanding Consultancy Award in 2000, the Faculty Merit Award for best teaching from The Hong Kong Polytechnic University in 2003, the Faculty Engineering Industrial and Engineering Services Grant Achievement Award in 2006, the Brussels Innova Energy Gold Medal with Mention in 2007, the Consumer Product Design Award in 2008, the Electric Vehicle Team Merit Award of the Faculty in 2009, the Geneva Invention Expo Silver Medal in 2011, and the Eco Star Award in 2012.