Grenze International Journal of Electrical and Electronics Engineering , Nov 2015
Performance Evaluation of TCHB Multilevel Inverter with Level-Shifted PWM Scheme 1
Sudheer Vinnakoti and 2Venkata Reddy Kota
1
2
Research Scholar, Department of E.E.E, JNTUK, KAKINADA, A.P, INDIA. E-mail:
[email protected] Assistant Professor, Department of E.E.E, JNTUK, KAKINADA, A.P, INDIA. E-mail:
[email protected]
Abstract—Lower output harmonics and lower commutation losses makes the multilevel converters capable to handle high power applications. Cascaded H-Bridge Multilevel Inverters (CHB) are appropriate for high-power applications due to the modular structure that empowers higher voltage operation with exemplary low-voltage semiconductors. Their fundamental drawback is complex circuitry, obliging high number of power devices and passive components. In this paper, a novel topology called Transistor Clamped H-Bridge Multilevel Inverter (TCHB) is proposed to generate a 9-Level output voltage with reduced number of switches and to achieve even power distribution among the devices. Simulations are carried out in MATLAB/SIMULINK for a 9-Level output voltage with Phase Disposition (PD) PWM scheme. Simulation results prove that the proposed scheme reduces the number of switching devices and gives better performance with even power distribution among the devices. Index Terms— Level Shifted PWM (LS-PWM), Phase Disposition (PD), Cascaded H-Bridge Multilevel Inverters (CHB), Transistor Clamped H-Bridge (TCHB) Multi Level Inverter.
I. INTRODUCTION Multilevel inverter has been executed in applications running from medium to high-power levels, such as motor drivers in marine, mining and chemical industries [1]-[4], Power Line Conditioners [5], renewable energy generation and distribution [6], Flexible AC Transmission Systems (FACTS) [7],[8] etc. In all these applications their advantages compensate the cost differential. In the late 1960s, Multilevel converter innovation began with the presentation of the multilevel stepped waveform idea with a series connected H-bridge, which is otherwise called CHB converter. Flying Capacitor (FC) multilevel topology was introduced in the same year for low power applications. Later in 1970s, the Diode-clamped converter / Neutral Point Converter (NPC) was initially presented, with an idea for threelevel NPC (3L-NPC) converter and might be considered as the first genuine multilevel power converter for medium-voltage applications. Later, the CHB was re-introduced in the late 1980s [9] and by 1990s became highly popular among the three topologies [10]. In the same way, the early idea of the FC circuit presented for low power in the 1960s formed into the medium-voltage multilevel converter topology in the early 1990s [11]. Multilevel inverter topology draws many researchers attention; this paper mainly concentrates on CHB. Modularity also permits the cascaded multilevel inverter to be stacked easily for high-power and high-voltage Grenze ID: 01.GIJEEE.1.1.19 © Grenze Scientific Society, 2015
applications. CHB is categorized into symmetrical and asymmetrical configurations. The cascaded multilevel inverter regularly embodies few indistinguishable single phase H-Bridge cells in cascaded arrangement at its output side. This setup is commonly referred as a CHB, which might be delegated symmetrical if the dc bus voltages are equivalent in all the arranged power cells, or as unsymmetrical if otherwise. In an unsymmetrical CHB, dc voltages are differed to create more output levels [12]. Therefore, inverter configuration gets to be more convoluted as every individual power cell must be sized accordingly to their respective power levels, including confined dc sources. This makes symmetrical CHB advantageous over asymmetrical with respect to maintenance and cost. The fundamental limitation connected with the symmetrical CHB is that dc voltages are kept in equilibrium which expands the complexity of the modulator circuit. Considering technological propensity, reduction of the cost is the major challenge in multilevel converters; their cost difference will remain unless the complexity issue is solved both at the power circuit and at the modulator circuit levels. Recently a Transistor Clamped H-Bridge (TCHB) [13] to enhance the output levels with reduced number of switches has been proposed. The TCHB topology has got expanded consideration as it gives a more straight forward methodology to build output levels by taking different voltage levels from the series stacked capacitors. Each cell in TCHB generates a five level output voltage. The proposed 9-Level TCHB consists of two cells connected in series. Phase Disposition (PD) PWM scheme is used to generate gate pulses to the proposed topology. Simulation results validate the applicability of the proposed TCHB topology. II. TCHB INVERTER TOPOLOGY The general configuration of a TCHB cell with a bidirectional switch connected between the first leg of the H-Bridge and the capacitor midpoint is shown in Fig. 1. A single cell of TCHB empowers five level output voltage (±Vdc, ± (1/2) Vdc, 0) to be generated focused around the switching sequence as given in Table I.
Fig 1: Topology for five level transistor clamped H-Bridge cell TABLE I: FIVE LEVEL TRANSISTOR CLAMPED H-BRIDGE OUTPUT VOLTAGE S1
S2
S3
S4
S5
Van
0
1
0
0
1
Vdc
1
0
0
0
1
Vdc /2
0
0
1
0
1
0
0
1
0
1
0
0
1
0
0
1
0
-Vdc/2
0
0
1
1
0
-Vdc
An array of individual cells is connected as shown in Fig. 2 to generate nine level switched output voltage waveforms [13]. The quantity of power cells obliged depends essentially on the working voltage and manufacturing cost. For this case, a two-cell configuration is sufficient to create a high-quality output with up to a 17 level line-line voltage. TCHB accomplishes a 37.5% decrease in the required quantity of main power switches by utilizing just ten controlled power switches rather than sixteen needed in conventional three topologies viz., NPC, FC, and CHB. Moreover, since the two capacitors are joined in parallel with the main dc power supply, no critical capacitor voltage swing is delivered during normal operation. 22
Fig 2: General configuration of three phase CHB
In general, the maximum levels in the phase and line voltages of the proposed inverter, in view of NC cells, are given by the accompanying comparisons: np =4Nc + 1 (1) nL =8Nc + 1 (2) Where, np is the number of phase voltage levels and nL is the number of line voltage levels In light of substantial switching sequence, S1 − S5 in Table I, the cell output voltage Van could be represented by (3) Van= Vdc (S5n -S4n) {½*S1n + │S2n S4n││S3n –S5n│} Summation of all the power cell voltages gives the phase-to neutral voltage, VaN and line voltage, Vab, respectively, as VaN = ∑ Van (4) Vab = VaN – Vbn (5) III. PROPOSED CONTROL SCHEME FOR TCHB INVERTER Modulation control of any sort of multilevel converter is very difficult, and a great part of the reported exploration is focused around to some degree heuristic investigations. Carrier-Based PWM (CBPWM) schemes is an ongoing idea in this work, however specific methodologies are connected to individual inverter structures. Thus, multilevel inverter structures have ordinarily been thought about on the premise of general execution; with little endeavor being made to adjust the best modulation methodology for one topology to 23
different structures. Most of the CBPWM schemes have been derived from the carrier disposition methodology presented by Carrara et al. [9]. CBPWM is classified into LS-CBPWM and PS-CBPWM. The former method is further classified viz., PDPWM, PODPWM and APODPWM. In any CBPWM scheme, For an N-level inverter, (N-1) triangular carriers with same frequency and amplitude are needed, so they completely possess coterminous groups over the entire range. A single sinusoidal reference is then compared with every carrier to investigate the switched output voltages for the converter. PD PWM scheme is widely used in NPC Multilevel Inverters thereby optimizing the line-to-line voltage harmonics because it makes carrier frequency harmonics as a common mode voltage that cancel out in the line-to-line voltage [15]. Since PD PWM scheme is independent of converter topology, this strategy can be used even in CHB but it results in unequal power distribution among the cells which produces high harmonic currents in the input side [1]. In this PWM scheme all the carriers are in phase as shown in Fig 3 and Fig 4 and it is clearly observed that, the carriers of both the cells are displaced by 1800, where the angle of displacement depends on the number of cells required to generate the desired level of output voltage and is given by, θcr,n = 2π(n − 1)/ NC, n= 1, 2 . . .N, Where, NC is the number of cells. (6) 2.5 2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5
0
0.002
0.004
0.006
0.008
0.01 Time
0.012
0.014
0.016
0.018
0.02
0.016
0.018
0.02
Fig 3: PD PWM control scheme for upper cell configuration 2.5 2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5
0
0.002
0.004
0.006
0.008
0.01 Time
0.012
0.014
Fig 4: PD PWM control scheme for lower cell configuration
The modulation index M of the proposed multilevel inverter is characterized by M = (Vref /Vcr) (7) The phase to-neutral voltage Van got focused around the voltage reference magnitude and also the combination of cell voltages, Va1 and Va2, are recorded in Table II. 24
TABLE II: PHASE-TO-NEUTRAL VOLTAGE FOR TWO-CELL CONFIGURATION
0 < Vref ≤ 1
1 < Vref ≤ 2
-1 < Vref ≤ 0
−2 < Vref ≤ -1
Va1
Va2
VaN
0 ½Vdc 0 ½Vdc ½Vdc Vdc ½Vdc Vdc 0 -½Vdc 0 -½Vdc -½Vdc -Vdc -½Vdc -Vdc
0 0 ½Vdc ½Vdc ½Vdc ½Vdc Vdc Vdc 0 0 -½Vdc -½Vdc -½Vdc -½Vdc -Vdc -Vdc
0 ½Vdc ½Vdc Vdc Vdc 3/2Vdc 3/2Vdc 2 Vdc 0 -½Vdc -½Vdc - Vdc - Vdc -3/2Vdc -3/2Vdc -2Vdc
IV. SIMULATION RESULTS AND ANALYSIS The MATLAB/SIMULINK model of TCHB with a single cell is shown in Fig 5. Each cell generates a five level output voltage. An appropriate firing pulses to the power devices in a cell to produce a five-level output voltage is generated by using PD-PWM scheme and are shown in Fig 6. Several such cells are cascaded in order to generate higher level of voltages. [T1]
[T4] g
C E
E
m
g
C
m
g
C
+
[T2]
VA2 1
E
m
1000 V
VN
+
2 [T3]
g
C E
g
m
E
m
C
[T5]
Fig 5: Transistor Clamped H-Bridge topology for a Five Level output voltage AND
NOT
> AND AND >
OR
1 T1
AND
NOT
< AND NOT AND
OR
AND
NOT NOT 0
2 T2
