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Sep 27, 2012 - Abstract—A phase-shifted (PS) pulse-width-modulation (PWM) converter that can solve the drawbacks of existing PS full- bridge converters ...

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 2, FEBRUARY 2013

Phase-Shifted PWM Converter With a Wide ZVS Range and Reduced Circulating Current Il-Oun Lee, Student Member, IEEE, and Gun-Woo Moon, Member, IEEE

Abstract—A phase-shifted (PS) pulse-width-modulation (PWM) converter that can solve the drawbacks of existing PS fullbridge converters, such as narrow zero-voltage-switching (ZVS) range, large duty-cycle loss, large circulating current, and serious secondary-voltage overshoot and oscillation, is proposed in this paper. The proposed converter is composed of two symmetric half-bridge converters (TSHBCs) that are placed in parallel on the primary side and are driven in a phase-shifting manner. Their transformers are connected in series on the secondary side. At the output, a simple energy-recovery circuit (ERC) is employed. Due to this structure, the proposed converter has the advantages of wide ZVS range, less duty-cycle loss, reduced circulating current, and no secondary-voltage overshoot and oscillation, which results in the reduction of rectifier diodes’ voltage stress and EMI. Therefore, the conversion efficiency is higher and the cost of the secondary rectifier is reduced compared to its PS PWM counterparts. In this paper, the circuit configuration, operation principle, and relevant analysis results of the proposed converters are presented. Experimental results on a prototype converter realized with an 80-in plasma display panel sustain power module (320–385 Vd c input, 205 Vd c /5 A output) validate the theoretical analysis. Index Terms—No duty-cycle loss, no secondary-voltage oscillation, phase-shifted (PS) pulse-width-modulation (PWM), reduced circulating current, zero-voltage-switching (ZVS).

I. INTRODUCTION HE traditional phase-shifted (PS) full-bridge (PSFB) converter shown in Fig. 1 exhibits benefits in medium-tohigh-power applications [1]: all primary switches are turned ON under zero-voltage switching (ZVS) without the help of any auxiliary circuits. The switches’ voltage stress is clamped to that of the input voltage. Hence, high-frequency MOSFETs are suitable as main switches for the converter, which raise the power density of the converter. However, such a converter has several serious problems: first, the ZVS range of lagging-leg switches is very narrow under load variation. For this reason, its conversion efficiency is severely degraded as the load decreases [2]. Severe voltage overshoot and oscillation across the diode rectifier are generated due to the resonance between the transformer leakage

T

Manuscript received April 11, 2012; revised May 17, 2012; accepted June 18, 2012. Date of current version September 27, 2012. This work was supported by the National Research Foundation of Korea grant funded by the Korean Government (MEST) (2012-0000981). Recommended for publication by Associate Editor U. K. Madawala The authors are with the School of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology (KAIST), Yuseong-Gu, Daejeon 305-701, Korea (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2012.2205408

Fig. 1.

Traditional PSFB converter.

inductance and the parasitic junction capacitance of the rectifier diode [3]. This increases the diode voltage rating and cost, and causes electromagnetic interference (EMI) problems. Especially in applications where the output voltage is high, much higher voltage diodes are required. However, the use of higher voltage diodes increases power loss and voltage overshoot in the diodes because higher voltage diodes have poor recovery characteristics. Finally, if the converter is fit for a relatively wide input voltage range due to the design considerations such as the hold-up time requirement, the steady-state duty cycle becomes small and the freewheeling interval lengthens under normal operating conditions. Then, excessive circulating current appears on the primary side during the freewheeling interval, increasing the primary-side conduction losses and turn-off switching losses of the lagging-lag switches [4], [28]. In order to overcome the problems of the traditional PSFB converter, many studies have been conducted. First, the ZVS range of lagging-leg switches can be extended by increasing the leakage inductance of the transformer and/or adding an external resonant inductor with large inductance. However, this approach increases duty-cycle loss, which results in high secondaryvoltage stress and increased primary-conduction loss. Another approach is to reduce the magnetizing inductance of the transformer to achieve a wide ZVS range. However, this increases significantly the RMS current stress and conduction losses on the primary side, because the additional current caused by the small magnetizing inductor circulates through all of the switches and transformer at its peak value. The PSFB converter in [5] uses a

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LEE AND MOON: PHASE-SHIFTED PWM CONVERTER WITH A WIDE ZVS RANGE AND REDUCED CIRCULATING CURRENT

saturable reactor on the primary side. However, too much heat is generated on the saturable reactor, and hence it becomes bulky. The PSFB converters in [6] and [29] use a resonant inductor to extend the ZVS range of lagging-leg switches and need two clamping diodes for easy reduction of the secondary-voltage overshoot and oscillation. However, the converter suffers from an increased loss in the duty cycle, and a severe reverse-recovery phenomenon is generated on the additional clamping diodes when there is a light load. In addition, its ZVS operation cannot still be achieved at a very light load [7], [8]. Many PSFB converters extending the ZVS range without the increase of duty-cycle loss were introduced in [9]–[13]. In the converters, however, the current stress of all the switches is higher than the traditional PSFB converter due to the assistant current source for a wide ZVS range, which leads to the increase of conduction loss. To minimize the increase of current stress, one or two bulky inductors and some coupled inductors with large inductance are additionally required. The PSFB converters with a current-doubler rectifier can also solve the problems. However, the current ripple of two output inductors must be designed to be very large for a wide ZVS range. This results in an increase of RMS current stress in the converters [14], [15]. In [16] and [17], the PSFB converters with two transformers were introduced. Due to the use of two transformers, the ZVS operation in the converters is achieved under entire load conditions. However, the large dc bias currents flowing through the transformers increase the core losses and size of transformers [30]. The PSFB converters with zero-voltage and zero-current-switching (ZVZCS) operation can provide another solution to the problems. In these converters, leading-leg switches are turned ON with ZVS and lagging-leg switches are turned OFF with ZCS. Thus, MOSFETs as leading-leg switches and insulated gate bipolar transistors (IGBTs) as lagging-leg switches are generally preferred. Because the ZVS operation of leading-leg switches is achieved the same way as that of the traditional PSFB converter, its range is wide under load variations. Moreover, nearly constant efficiency can be obtained over a wide input voltage range because the primary current is reset during freewheeling intervals. However, for ZCS operation and countermeasures to side effects such as high secondary-voltage stress and primary-current overshoot, they require many additional components, which result in high cost and a complex structure [18]–[21]. In addition, using IGBTs to suit ZCS operation precludes the use of high switching frequency to realize smaller magnetic components and capacitors [22]–[25]. In this paper, a new PS pulse-width-modulation (PWM) converter that can solve the drawbacks of existing PSFB converters is proposed. The proposed converter is composed of two symmetric half-bridge converters (TSHBCs) that are placed in parallel on the primary side. Their transformers are connected in series on the secondary side. At the output, a simple energyrecovery circuit (ERC), which was used to ensure the ZVZCS operation of the PSFB converter in [26], is employed. In general, it is known that in a conventional symmetric half-bridge converter (SHBC), the ZVS operation of all the switches cannot be guaranteed. However, all the switches in the proposed converter are turned ON with ZVS under entire load conditions, although

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the proposed converter consists of TSHBCs and uses the ERC utilized for ensuring the ZVZCS operation in [26]. It is achieved by using only the magnetizing inductance of the transformer in one of TSHBCs without any additional large resonant inductors or circuits. In addition, the proposed converter has no problems related to an increase of duty-cycle loss. This allows the turns ratio of the transformers to be designed to be better than that of the traditional PSFB converter with a large resonant inductor or the converter in [6]. Thus, both the voltage stress across the diode rectifier and the load current reflected to the primary side can be reduced. These contribute to the improvement in the conduction loss. Due to the use of ERC, the primary-circulating currents in freewheeling intervals are reduced, which decreases the primary-side conduction and turn-off switching losses. The secondary-voltage overshoot and oscillation are also eliminated perfectly. Thus, EMI can be improved and low voltage-rated diodes can be employed in the secondary rectifier. The use of low-voltage diodes reduces power loss on the rectifier stage because low-voltage diodes have advantages such as lower ONstate voltage and better recovery characteristics compared to high-voltage diodes. A low-profile design becomes a possibility because two transformers transfer the equal power from the input source to the output load simultaneously. This results in a slim power supply. Finally, the output is regulated by adjusting the PS time between the TSHBCs at a fixed-switching frequency, like existing PSFB converters. Thus, it can be easily implemented using a dedicated controller for PS PWM converters. The circuit configuration and operation principle of the proposed converter are presented in Section II. The relevant analysis results are given in Section III. The performance of the proposed converter is confirmed by the experimental results of a prototype converter realized with an 80-in plasma display panel (PDP) sustain power module (320–385 Vdc input, 205 Vdc /5 A output) in Section IV. The conclusion is given in Section V. II. PROPOSED PS PWM CONVERTERS A. Circuit Configuration Fig. 2 shows the circuit configuration of the proposed converter. As shown in Fig. 2, the proposed converter is composed of TSHBCs in parallel on the primary side; one of TSHBCs consists of switches Q1 and Q2 , a blocking capacitor CB , and a transformer T1 . The other consists of switches Q3 and Q4 , a blocking capacitor CB , and a transformer T2 . The two transformers T1 and T2 are connected in series on the secondary side. For high-output-voltage applications, a full-bridge rectifier featuring low-voltage stress is employed for rectification. At the output, a simple ERC that consists of a capacitor and two diodes is employed. B. Operation Principle Fig. 3 shows the key operating waveforms of the proposed converter in the steady state. Referring to the figure, it is known that all the switches are driven with a constant duty ratio (D = 0.5), ignoring the dead time Tdead . The TSHBCs are run by adjusting the PS time TΦ . Each switching period is divided

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Fig. 2.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 2, FEBRUARY 2013

Proposed converter.

into two half cycles: t0 –t11 and t11 –t22 . Because the operational principles of two half cycles are symmetric, only the first half cycle is described. This half cycle can be subdivided into 11 modes, whose operating circuits are shown in Fig. 4. In order to illustrate the operation of the proposed converter, several assumptions are made. These are detailed next: 1) the output inductor LO is large enough to be considered as a constant current source during a switching period; 2) the blocking capacitor CB is large enough to be considered as a constant voltage source of VIN /2; 3) the magnetizing inductance Lm 2 of the transformer T2 is large enough to ignore the effect of the magnetizing current during a switching period; 4) the main switches are all MOSFETs with parasitic diodes of Db 1 , Db 2 , Db 3 , and Db 4 ; 5) the output capacitances of all the MOSFETs have the same capacitance of COSS ; 6) the junction capacitances of all rectifier diodes have the same capacitance of Cj ; 7) the transformers of T1 and T2 have the same turns ratio of n = NS 1 /NP 1 = NS 2 /NP 2 ; 8) the clamping capacitors CC are large enough to be considered as a constant voltage source of VC . Mode 1 [t0 –t1 ]: Mode 1 begins when switches Q2 and Q4 are in ON-state and diodes D2 , D4 , and DC 1 are conducting. During this mode, the primary voltage Vp 1 (t) of the transformer T1 and the primary voltage Vp 2 (t) of the transformer T2 are the negative and positive halves of the input voltage, respectively. Thus, the magnetizing current iL m 1 (t) decreases linearly from its initial value and iL m 2 (t) increases linearly. However, iL m 2 (t) is very low, nearly zero because the magnetizing inductance Lm 2 of T2 is very large. The input voltage of rectifier Vsec (t) is equal to VC , where VC is the average value of the voltage vC c (t) across the clamping capacitor CC in the ERC, because D2 , D4 , and DC 1 are conducting. This voltage is applied to two leakage inductors through two transformers, and then the secondary current isec (t)

increases linearly from its initial value. The current of DC 1 , iD c 1 (t) also increases linearly from zero. The voltage stress of diodes D1 and D3 are equal to VC . Several currents in this mode can be expressed as follows: ip1 (t) = iL m 1 (t) + nisec (t) = −iQ 2 (t)

(1)

ip2 (t) = iL m 2 (t) + nisec (t) ≈ nisec (t) = iQ 4 (t)

(2)

isec (t) = isec (t0 ) +

VC (t − t0 ) = −iD 2&D 4 (t) + Llk 2 )

n2 (Llk 1

(3) iL m 1 (t) = iL m 1 (t0 ) −

0.5VIN (t − t0 ) Lm 1

(4)

iD c1 (t) = iD c1 (t0 ) +

VC (t − t0 ). n2 (Llk 1 + Llk 2 )

(5)

Mode 2 [t1 –t2 ]: Mode 2 begins when isec (t) becomes zero in mode 1. Then, D2 and D4 are turned OFF and the secondary side of the transformers is separated from the primary side. The output inductor current IL o flows through DC 1 . Vp 1 (t) and Vp 2 (t) are still the negative and positive halves of the input voltage, respectively. Thus, iL m 1 (t) decreases continuously. During this mode, the voltages of the two leakage inductors are zero. The currents in this mode can be given by ip1 (t) = iL m 1 (t) = iL m 1 (t1 )−

0.5VIN (t − t1 ) = −iQ 2 (t) Lm 1 (6)

ip2 (t) ≈ 0 = iQ 4 (t)

(7)

isec (t) = 0

(8)

iD c1 (t) = IL o .

(9)

Mode 3 [t2 –t3 ]: Mode 3 begins when Q2 is turned OFF at t2 . Then, the resonance of COSS1 , COSS2 , Llk 1 , and Lm 1 occurs in SHBC1. By this resonance, the voltage across COSS1

LEE AND MOON: PHASE-SHIFTED PWM CONVERTER WITH A WIDE ZVS RANGE AND REDUCED CIRCULATING CURRENT

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Vp1 (t) = VQ 2 (t) − 0.5VIN

(12)

Vsec (t) = n(Vp1 (t) + Vp2 (t)) = nVQ 2 (t)

(13)

ip1 (t) = iL m 1 (t) = iL m 1 (t2 ) isec (t) = 0 ≈

(14)

ip2 (t) n

(15)

where iL m 1 (t2 ) = −0.5ΔIripple .

(16)

Mode 4 [t3 –t4 ]: Mode 4 begins when Vsec (t) reaches Vc in mode 3. Then, D1 and D3 begin to conduct and the resonance of COSS1 , COSS2 , Llk 1 , and Llk 2 occurs in the primary-power path. The voltages of COSS1 and COSS2 are discharged and charged by the resonance, respectively. During this mode, Vsec (t) is clamped to Vc and Vp 1 (t) increases to 0.5VIN with a sinusoidal waveform. The sum of the voltages of the two leakage inductors also increases to VIN −VC /n. The voltages and currents in this mode can be given by VQ 1 (t) = VIN − VQ 2 (t)

(17)

VC − zO ip1 (t3 ) sin ωO (t − t3 ) (18) n (19) Vp1 (t) = VQ 2 (t) − 0.5VIN

VQ 2 (t) =

VC n ip1 (t) = ip1 (t3 ) cos ωO (t − t3 )

Vlk 1 (t) + Vlk 2 (t) = VQ 2 (t) −

isec (t) =

(20) (21)

1 ip2 (t) (ip1 (t) + 0.5ΔIripple ) ≈ n n (22)

iD c1 (t) = IL o − isec (t)

(23)

ip1 (t3 ) = −0.5ΔIripple

(24)

ΔIripple =

VIN TS 4Lm 1

ωO = 2πfO =   zO =

Fig. 3.

Key operating waveforms of the proposed converter in a steady state.

is discharged linearly and the voltage across COSS2 is charged linearly. During this mode, the voltages of the two leakage inductors still maintain zero. Vp 1 (t) increases linearly with the same slope as that of the voltage across COSS2 . Vp 2 (t) is maintained at 0.5VIN . The voltages and currents in this mode can be expressed as follows: VQ 1 (t) = VIN − VQ 2 (t) VQ 2 (t) =

|iL m 1 (t2 )| (t − t2 ) 2COSS

(10) (11)

(25) 1 2(Llk 1 + Llk 2 )COSS

Llk 1 + Llk 2 . 2COSS

(26)

(27)

From (17), (18), and (24)–(27), we can know that the ZVS of Q1 (or Q2 ) is related to Llk 1 , Llk 2 , and Lm 1 . Due to these three elements, SHBC1 has the capability of ZVS turn-on under entire load conditions. The ZVS condition of SHBC1 will be detailed in the next section. Mode 5 [t4 –t5 ]: Mode 5 begins when the voltage across CO S S 1 reaches zero at t4 . Then, the parasitic diode Db 1 of Q1 begins to conduct and Q1 is turned ON with ZVS. During this mode, Vsec (t) is maintained at Vc and Vp 1 (t) is equal to 0.5VIN . The sum of the voltages across the two leakage inductors is given by Vlk 1 (t) + Vlk 2 (t) = VIN −

VC . n

(28)

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 2, FEBRUARY 2013

Fig. 4. Operating circuits during the first half cycle: (a) Mode 1, (b) Mode 2, (c) Mode 3, (d) Mode 4, (e) Mode 5, (f) Mode 6, (g) Mode 7, (h) Mode 8, (i) Mode 9, (j) Mode 10, and (k) Mode 11.

By (28), the currents flowing through the leakage inductors increase linearly. iL m 1 (t) also increases linearly due to a positive Vp 1 (t). The currents in this mode can be expressed as follows:

isec (t) = isec (t4 ) +

nVIN 2 n (Llk 1

− VC (t − t4 ) + Llk 2 )

iD c1 (t) = IL o − isec (t) = iD c (t4 ) −

(29)

nVIN − VC (t − t4 ) n2 (Llk 1 + Llk 2 ) (30)

0.5VIN (t − t4 ) Lm 1

(31)

ip1 (t) = iL m 1 (t) + nisec (t) = iQ 1 (t)

(32)

ip2 (t) ≈ nisec (t) = iQ 4 (t).

(33)

iL m 1 (t) = −ΔIripple +

Mode 6 [t5 –t6 ]: Mode 6 begins when the current through Dc 1 , iD c 1 (t), reaches zero at t5 . Then, the two leakage inductors begin to resonate with the junction capacitors in diodes D2 and D4 . This resonance increases gradually the voltage stress of D2 and D4 . The relevant voltages and currents can be expressed as

LEE AND MOON: PHASE-SHIFTED PWM CONVERTER WITH A WIDE ZVS RANGE AND REDUCED CIRCULATING CURRENT

follows:

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in this mode can be expressed as follows:

VD 2&D 4 (t) = (VC − nVIN ) cos ωO 1 (t − t5 ) + IL o zO 1 sin ωO 1 (t − t5 ) + nVIN Vsec (t) = VD 2&D 4 (t)

VQ 3 (t) = VIN − (34)

(36)

nVIN − VC sin ωO 1 (t − t5 ) zO 1

(37)

where

 zO 1 =

1 2n2 (Llk 1

+ Llk 2 )Cj

n2 (Llk 1 + Llk 2 ) . 2Cj

(38)

(39)

Mode 7 [t6 –t7 ]: Mode 7 begins when Vsec (t) becomes VC +VO . Then, the diode DC 2 in the ERC is forward-biased and the resonance of the two leakage inductors and the clamping capacitor CC occurs. During this mode, Vsec (t) and the voltage stress of D2 and D4 are clamped at VC + VO because DC 2 is conducting due to the above resonance. In this mode, the secondary currents can be given by isec (t) = IL o + iD c2 (t) iD c2 (t) =

(40)

nVIN − VO − vC (t6 ) sin ωO 2 (t − t6 ) zO 2 + (isec (t6 ) − IL o ) cos ωO 2 (t − t6 )

ωO 2 = 2πfO 2 =   zO 2 =

1 n2 (Llk 1

+ Llk 2 )CC

n2 (Llk 1 + Llk 2 ) . CC

(41) (42)

(43)

As described previously, the diode rectifier in the proposed converter does not experience the severe secondary-voltage overshoot and oscillation of existing PSFB converters. Thus, the proposed converter can use much lower voltage-rated diodes than its counterparts, which result in low cost and less power loss. Mode 8 [t7 –t8 ]: Mode 8 begins when iD c 2 (t) becomes zero. During this mode, we can obtain the following equation because the two primary voltages Vp 1 (t) and Vp 2 (t) are 0.5VIN , the sum of the voltages of the two leakage inductors is zero, and Vsec (t) is VC +VO : VC = nVIN − VO .

Vp2 (t) = 0.5VIN −

nIL o (t − t8 ) 2COSS

Vlk 1 (t) + Vlk 2 (t) = −VQ 4 (t).

isec (t) = IL o cos ωO 1 (t − t5 )

ωO 1 = 2πfO 1 = 

VQ 4 (t) = VIN − VQ 3 (t)

(35)

Vlk 1 (t) + Vlk 1 (t) = VIN − Vsec (t)/n

+

nIL o (t − t8 ) 2COSS

(44)

Mode 9 [t8 –t9 ]: Mode 9 begins when Q4 is turned OFF at t8 . Then, by the energy stored in the output inductor LO , the voltage across COSS3 is discharged linearly and the voltage across COSS4 is charged linearly. Vp 2 (t) decreases from 0.5VIN to −0.5VIN and Vsec (t) is maintained at VC +VO . The voltages

(45) (46) (47) (48)

As described previously, the ZVS of Q3 (or Q4 ) is achieved by the energy stored in the output inductor LO . As the output inductance of LO is quite large, its energy is large enough to realize the ZVS for Q3 in a wide load range. That is, compared to that of Q1 or Q2 , the ZVS of Q3 (or Q4 ) is achieved easily in the proposed converter. Mode 10 [t9 –t10 ]: Mode 10 begins when the voltage across COSS3 reaches zero. At the same time, the parasitic diode Db 3 of Q3 starts to conduct and the two leakage inductors resonate with the junction capacitors of D2 and D4 . By this resonance, the voltages of D2 and D4 and Vsec (t) decrease with a sinusoidal waveform as in Vsec (t) = VD 2&D 4 (t) = (VC + VO ) cos ωO 1 (t − t9 ).

(49)

Mode 11 [t10 –t11 ]: Mode 11 begins when Vsec (t) reaches VC . Then, DC 1 is forward-biased. Because Vp 1 (t) is 0.5VIN and Vp 2 (t) is −0.5VIN during this mode, the clamping capacitor voltage VC is applied to the two leakage inductors through the transformers. Thus, the current through the two leakage inductors and isec (t) decrease linearly, while iD c 1 (t) increases linearly. At the end of this mode, Q3 is turned ON with ZVS. In this mode, the currents can be expressed as isec (t) = IL o −

VC (t − t10 ) + Llk 2 )

n2 (Llk 1

iD c1 (t) = IL o − isec (t) =

(50)

VC (t − t10 ). (51) n2 (Llk 1 + Llk 2 )

Mode 12–22 [t11 –t22 ]: The operations from Mode 12 to Mode 22 are the same as previous modes except for the direction of the powering path. III. RELEVANT ANALYSIS RESULTS A. Topology Comparison A ZVZCS PSFB converter with the same ERC as the proposed converter was introduced in [26]. However, if the value of a magnetizing inductor is designed to be small in the converter, all the switches can operate with ZVS, not ZVZCS under a wide load variation. The small magnetizing inductance also allows the traditional PSFB converter shown in Fig. 1 to have a wide ZVS range. In this part, two topologies including the converter in [26] and traditional PSFB converter with small magnetizing inductance for a wide ZVS range are compared with the proposed converter. To simplify the analysis, we assume that the output inductor current is a constant current source and all magnetizing

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 2, FEBRUARY 2013

Fig. 5. Key operating waveforms of (a) traditional PSFB converter with small magnetizing inductance, (b) converter in [26] with small magnetizing inductance, and (c) proposed converter.

Fig. 6.

Primary RMS current stress at a full load: (a) at SHBC1 (Transformer T1 ) and (b) at SHBC2 (Transformer T2 ).

currents have the same current ripple. Fig. 5 shows the key operating waveforms of each converter for topology comparison. Comparing Figs. 5(a) with Fig. 5(b) reveals that the converter in [26] has a smaller circulating current during the freewheeling interval than the traditional PSFB converter. As a result, the converter in [26] will have lower conduction and turn-off switching losses. From Fig. 5(b) and (c), however, we can see that the proposed converter has a performance over the converter in [26] with a small magnetizing inductance; first, because the additional current of Lm 1 , which extends the ZVS range of SHBC1, never flow through Q3 , Q4 , and T2 in SHBC2, the RMS current stress and conduction losses in SHBC2 do not increase. Besides,

in spite of the use of small magnetizing inductance of T1 , the primary RMS current stress in the SHBC1 is much lower than the traditional PSFB converter with small magnetizing inductance, because the average value of the magnetizing current of T1 is zero within a half-switching period, and its contribution to the total RMS current at heavy loads is negligible. Also, due to the secondary ERC circuit, the primary circulating current is nearly removed and the primary peak current stress becomes much lower compared to the counterparts. Consequently, the primary RMS current stress is significantly improved, which is confirmed in the analysis results in Fig. 6. Additionally, the turn-off switching loss is also further improved. In conclusion,

LEE AND MOON: PHASE-SHIFTED PWM CONVERTER WITH A WIDE ZVS RANGE AND REDUCED CIRCULATING CURRENT

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where ΔIripple =

VIN TS . 4Lm 1

From (55), it is noted that the ZVS condition is independent of the load conditions. This is because the secondary current isec (t) is reset to zero during the ON-state of the switches in SHBC1 and the current flowing through Q1 (or Q2 ) equals the magnetizing current iL m 1 (t) before the turn-off of the switches, as shown in Fig. 3. Therefore, if (55) is satisfied under any load conditions, the switches in SHBC1 will turn ON with ZVS under entire load conditions. Fig. 7.

Voltage waveform across the output inductor L O during half period.

although the small magnetizing inductance of T1 is used for extending the ZVS range, we can say that the proposed converter has the performance over the counterparts in terms of the primary RMS current stress and turn-off switching loss. B. DC Conversion Ratio The dc conversion ratio of the proposed converter can be derived by using the principle of volt-second balance on the output inductor in Fig. 7. Because the durations of modes 2, 5, 8, and 9 are very narrow and hence they can be ignored, it can be derived as VO M= ≈ 2nDeff . (52) VIN The effective duty cycle is found from the PS time Tφ between TSHBCs as Tφ + Tdead + T01 (53) Deff = TS where T01 is the time interval of Mode 1 or Mode 12. From (52) and (53), it is noted that the output voltage of the proposed converter can be modulated by adjusting Tφ at a fixedswitching frequency, like the conventional PSFB converters. Hence, it can be easily implemented using a dedicated controller for PS PWM converters such as UCC3895. C. ZVS Condition As described in Section II-B, the ZVS of SHBC2 in the proposed converter is easily achieved in a wide load range due to the output inductor, like that of the leading-leg switches in existing PSFB converters. However, the ZVS of SHBC1 is different from that of the lagging-leg switches of existing PSFB converters. In this part, we investigate the ZVS condition of SHBC1. From Fig. 3, the ZVS condition of SHBC1 is obtained as t4 − t2 ≤ Tdead .

(54)

Equation (54) can be represented using (11) and (18) as follows:   4VC COSS VC 0.5zO ΔIripple sin ωO Tdead − ≥ VIN − nΔIripple n (55)

D. Duty-Cycle Loss In general, it is widely known that utilizing a large resonant inductor for extending the ZVS range reduces the effective duty cycle (or increases the duty-cycle loss). To compensate for this, the turns ratio of the transformer is designed to be poor, which thereby increases the primary conduction losses and secondary voltage stress. However, the ZVS range of the proposed converter is extended using only the magnetizing inductor of the transformer in SHBC1, which is parallel with the powering path. Thus, the proposed converter has no problems related to the duty-cycle loss. E. Voltage Oscillation and Power Loss in Rectifier Diodes Fig. 8 shows the experimental waveforms of the PSFB converter with two clamping diodes in [6] and TSHBCs without ERC. From the figure, we can see the severe secondary-voltage overshoot and oscillation. It comes from the resonance of the transformer leakage inductance and the junction capacitance of the rectifier diodes and is well explained in [3]. The secondaryvoltage overshoot and oscillation can cause an EMI problem. In addition, high-voltage-rated diodes should be used in the rectifier stage due to the voltage overshoot. For example, diodes with a 600-V rating are required in our application. However, the diodes with a 600-V rating have a high ON-state voltage of around 2 V, which results in a high conduction loss. To reduce the secondary-voltage overshoot and oscillation, [27] proposed a secondary RCD snubber circuit. However, the snubber resister consumes the energy stored in the transformer leakage inductance through the resonance of the leakage inductance and the junction capacitance of rectifier diodes. Consequently, much loss on the snubber resister is generated as the output power increases. Additionally, the secondary-voltage overshoot and oscillation still exists. As described in Section II-B, the proposed converter has no secondary-voltage overshoot and oscillation because the input voltage of rectifier Vsec (t) is clamped to the sum of the clamping capacitor voltage and the output voltage. Therefore, much lower voltage-rated diodes can be employed in the proposed converter. In our application, diodes with a 300-V rating that have an ONstate voltage of 1 V are needed. This results in a 50% reduction in the conduction losses on the rectifier diodes because the ONstate voltage of a 300-V rating diode is half that of a 600-V rating diode. Moreover, the energy stored in the leakage inductances

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 2, FEBRUARY 2013

Fig. 8. Secondary-voltage overshoot and oscillation at the nominal input voltage, i.e., 385 V and a full load of 5 A in (a) PSFB converter with clamping diodes [6] and (b) TSHBCs without ERC. TABLE I COMPONENT LIST

Fig. 9.

Controller for the experiment of the proposed converter.

is transferred to the output by the resonance of the leakage inductances and the clamping capacitance in ERC during Mode 7. Thus, the energy consumed in the resister of the RCD snubber is also saved. Due to these advantages, efficiency can be further improved and the cost can be reduced.

IV. EXPERIMENTAL RESULTS The proposed converter and the converters for comparison are realized with the specifications of an 80-in PDP sustain power module given next: 1) input voltage: VIN = 320–385 V;

LEE AND MOON: PHASE-SHIFTED PWM CONVERTER WITH A WIDE ZVS RANGE AND REDUCED CIRCULATING CURRENT

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Fig. 10. Key experimental waveforms of the proposed converter at the nominal input voltage, i.e., 385 V and a full load of 5 A. (a) V p 1 (t), ip 1 (t), V p 2 (t), and ip 2 (t) and (b) V p 1 (t), V p 2 (t), V se c (t), and ip 2 (t).

Fig. 11.

ZVS waveforms of SHBC1 of the proposed converter: (a) at no load, (b) at 20% of full load, (c) at 50% of full load, and (d) at full load.

2) output voltage: VO = 205 V; 3) maximun output current: IO (m ax) = 5 A; 4) switching frequency: fS = 100 kHz. The prototype converter for the experiment was built and tested to verify the operational principle, advantages, and performances of the proposed converter using the components, as shown in Table I. The controller for the experiment is shown in Fig. 9. In order to alleviate the voltage overshoot and oscillation, the snubber circuit (R = 10 kΩ/3 W, C = 4.7 μF/630 V, D = UF4004) introduced in [27] is employed in the converters for comparison. The converter with clamping diodes in [6] built for the comparison is designed in such a way that the ZVS operation is achieved in the range of 50%–100% of full load. This is because to ensure the ZVS operation under light-load conditions,

it needs a very large resonant inductor, which results in very high voltage stress across the rectifier diodes, high conduction losses, and no regulation of the output voltage. A. Waveforms Fig. 10 shows the key waveforms of the proposed converter at the nominal input voltage, i.e., 385 V and a full load of 5 A. As shown in Fig. 10, all measured waveforms well follow the theoretical waveforms described in Fig. 3. Furthermore, we can see that the secondary voltage Vsec (t) in Fig. 10(b) has no voltage overshoot and oscillation. Figs. 11 and 12 show the ZVS waveforms of SHBC1 and SHBC2 in the proposed converter under different load conditions, respectively. From Figs. 11 and 12, it is clear that all the switches in the proposed converter are turned ON with ZVS under entire load conditions. In addition,

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Fig. 12.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 2, FEBRUARY 2013

ZVS waveforms of SHBC2 of the proposed converter: (a) at no load, (b) at 20% of full load, (c) at 50% of full load, and (d) at full load.

waveforms. Having no secondary-voltage overshoot and oscillation and using a low voltage-rated diode also contribute to the improvement in the efficiency. V. CONCLUSION

Fig. 13.

Efficiency under different load conditions.

we can see that the circulating current and turn-off switching losses are reduced, compared to existing PSFB converters with ZVS operation. B. Efficiency Fig. 13 shows the efficiency measured using a power analyzer (PPA2520, KinetiQ) under different load conditions when the input voltage is 385 V. As shown in Fig. 13, the proposed converter has the maximum efficiency of 96.28% at a full load and achieves a significant improvement in the efficiency compared with its counterparts. This is because the proposed converter operates with ZVS under entire load conditions while having no effect of duty-cycle loss, and the circulating current and turnoff switching losses are reduced, as shown in the experimental

This paper has presented a new PS PWM converter that can solve the drawbacks of existing PSFB converters, such as narrow ZVS range against load variation, large duty-cycle loss, large circulating current, and serious secondary-voltage overshoot and oscillation. The theoretical analysis in this paper also showed why the proposed converter has a better performance than existing PSFB converters. The experiment results of a prototype converter realized with the specifications of an 80-in PDP sustain power module showed that the theoretical analysis is valid and the proposed converter achieves a significant improvement in efficiency. Due to the advantages, the proposed converter is applicable especially to the high-voltage applications such as PDP sustain power module, high-voltage battery charger (200–400 V), etc. REFERENCES [1] J. A. Sabat`e, V. Vlatkovic, R. B. Ridley, F. C. Lee, and B. H. Cho, “Design considerations for high-voltage high-power full-bridge zero-voltageswitching PWM converter,” in Proc. Appl. Power Electron. Conf. and Expos. 1990, 2013, pp. 275–284. [2] B. Chen and Y. Lai, “Switching control technique of phase-shift-controlled full-bridge converter to improve efficiency under light-load and standby conditions without additional auxiliary components,” IEEE Trans. Power Electron., vol. 25, no. 4, pp. 1001–1011, Apr. 2010. [3] K. Park, C. Kim, G. Moon, and M. Youn, “Voltage oscillation reduction technique for phase-shift full-bride converter,” IEEE Trans. Ind. Electron., vol. 54, no. 5, pp. 2779–2790, Oct. 2007.

LEE AND MOON: PHASE-SHIFTED PWM CONVERTER WITH A WIDE ZVS RANGE AND REDUCED CIRCULATING CURRENT

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Il-Oun Lee (S’10) was born in Korea in 1976. He received the B.S degree in electrical and electronic engineering from Kyungpook National University, Taegu, Korea, and the M.S. degree in electrical engineering from Seoul National University, Seoul, Korea, in 2000 and 2002, respectively. He is currently working toward the Ph.D. degree at the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea. Beginning in 2003, he was a Research Engineer in the PDPDevelopment Group, Samsung SDI, Korea, for five years, where he was involved in circuit and product development for 42in, 50-in, 63-in, and 80-in PDP TV. From 2008 to 2009, he was a Senior Engineer in the Power Advanced Development Group, Samsung Electro-Mechanics Co. Ltd., where he was involved in the power circuit development for LED lighting, LCD TV, PDP TV, and server power system, His current research interests include dc–dc converters, power-factor-correction ac–dc converters, LED driver, battery charger for electric vehicle, digital display power systems, and a digital control approach of dc–dc converters.

Gun-Woo Moon (S’92–M’00) received the M.S. and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1992 and 1996, respectively. He is currently a Professor in the Department of Electrical Engineering, KAIST. His research interests include modeling, design and control of power converters, soft-switching power converters, resonant inverters, distributed power systems, power-factor correction, electric drive systems, driver circuits of PDPs, and flexible ac transmission systems. Dr. Moon is a Member of the Korean Institute of Power Electronics, Korean Institute of Electrical Engineers, Korea Institute of Telematics and Electronics, Korea Institute of Illumination Electronics and Industrial Equipment, and Society for Information Display.

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