Effect of Metal Layout Design on Passivation Crack Occurrence using both Experimental and Simulation Techniques R.B.R van Silfhout1), W.D. van Driel2), Y.Li2), M.A.J. van Gils1), J.H.J. Janssen2), G.Q. Zhang1), G. Tao2), J. Bisschop2) 1)
Philips CFT/Centre for Industrial Technology, P.O. Box 218, 5600 MD, Eindhoven, The Netherlands
[email protected] 2) Philips Semiconductors, P.O. Box 30008, 6534 AE, Nijmegen, The Netherlands
Abstract Thermo-mechanical reliability is one of the concerns for semiconductor developments due to miniaturization, introduction of new materials, and higher application temperatures. FE modeling techniques are developed to predict the effect of IC interconnect metal designs on the thermo-mechanically-induced cracking of passivation layers. Experimental techniques on specially designed IC packages are developed to verify the predicted passivation cracks. With the verified 2D and 3D models, various simulations are performed and it is established that delamination of IC/compound interface is a key trigger for passivation cracking. When delamination is present, crack occurrence is found to depend on the metal layout and location on the IC. Optimizing the metal layout design can even prevent passivation cracks. By combining efficient & accurate simulations with a limited number of experiments, passivation crack can be quantitatively predicted prior to physical prototyping. 1. Introduction In semiconductor industry, Integrated Circuit (IC) designers have to design robust metal interconnect layouts that guarantee reliability during waferfab processes, package assembly, and qualification tests. Thermomechanical related failures are one of the major causes of reliability problems due to differences in Coefficient of Thermal Expansion (CTE), higher application temperatures, new materials, and the ongoing miniaturization.
Figure 1 shows an example of a damaged metal interconnect line and cracked passivation layer that covers the metal. Passivation crack and metal shift eventually causes electrical failures such as oxidation of metal and short-circuiting. Finite Element (FE) methodologies are developed widely to predict reliability prior to physical prototyping. Still, the predictive character is largely qualitative due to a lack of measuring techniques and failure modeling techniques [1]. One of the reasons is that delamination is a key failure mode and a trigger for other failures in ICs and packages [2, 3]. Delamination is at present difficult to predict quantitatively for the large variation in material interfaces existing in electronic packages, such as ceramics/compound (epoxy with filler particles), ceramics/ceramics, lead frame/compound, plating /compound, and glue/compound interfaces. In most of the package simulations, the IC is modeled as a homogeneous dice of silicon because of simplicity reasons. Recently, more advanced modeling techniques are explored to predict effects in local IC structures in a packaged IC such as bond pads, metal lines, and topography [2, 4]. Together with measuring the criteria for delamination it remains a challenging task to predict delamination quantitatively and to understand the mechanisms so that delamination can be prevented [5]. Our modeling methodology aims at predicting the effect of interconnect metal design on passivation crack occurrence when the IC/compound interface is delaminated. The simulation results and experimental observations will be discussed in the following sections. 2. Methodology
Figure 1: Shifted metal lines and cracked passivation layer covering the metal line.
2.1. Experiments Specially designed IC/package samples are developed to observe passivation cracks and to verify crack predictions from simulations (crack energy). The samples contain ICs with various test structures designed in the top metal level of the interconnect stack which are present in the corners of the IC. Figure 2 shows a typical corner structure of the interconnect metallization, further referred to as ‘test structure’. Among others, test structures contain bond pads (purple squares) and a metal power line (wide red line).
2.2. FE models Parametric FE models are developed to predict passivation cracks by applying the J-integral approach, which is based on Linear Elastic Fracture Mechanics (LEFM). 2D cross-section simulations are applied to predict the numerical J-values due to a small initial crack in the top passivation layer.
Figure 3: 2D Model showing lead frame (black), IC (magenta), and compound (blue), symmetry is on the right side.
Figure 2: Typical IC corner layout with distance metal power line to edge of the IC (a). Six different test structures are defined with varying values for parameter ‘a’. The structures are referred to as S1 till S6 with increasing distance ‘a’, see Table 1. Our initial idea was to trigger failures in a structure by making ‘a’ small, and to obtain a safe structure by making ‘a’ large.
Figure 3 shows the 2D model. Due to symmetry, ½ of the package is modeled. The small structures on top of the silicon contain dielectrics, metal seal, metal bond pad, metal line, and passivation Figure 4 schematically shows a magnification of the test structure cross-section. The passivation (blue) is covering the metallisation (orange) and is the same color as the substrate in this figure. A magnification is shown of the crack location and mesh. 3D models are developed to predict the distribution of Jvalues in the corners of the IC (3D effect). Figure 5 shows the 3D model (IC only) in which the test structure can be identified.
Table 1: Values for ‘a’ in the test structures. Test structure S1 S2 S3 S4 S5 S6
a [um] 78 138 203 269 334 400
The ICs are further assembled in modern plastic encapsulated packages which finally undergo e standard Temperature Cycle Testing (TCT). At various stages in the assembly and testing processes, Scanning Acoustic Microscopy (SAM) analyses are performed to determine the amount of delamination at the IC/compound interface. After TCT, packages are decapped and the following analyses are performed to observe different failures: • Pinhole analyses to detect passivation cracks. During a pinhole test an etching fluid is put on top of the IC, which runs through passivation cracks (if present) and etches away the metal. This is visible by changes in reflection/color. • Visual inspection to detect metal shift and passivation cracks. • Scanning Electron Microscopy (SEM) and Focused Ion Beam (FIB) analyses to detect both failures in cross-sections.
Figure 4: Magnification of the metallization on top of the IC (IC edge is on left side).
Figure 5: 3D model of ¼ package (only IC part is shown).
Both 2D and 3D models contain the IC (with metal corner structures on top), assembled in a plastic encapsulated package. The metal layout can be varied in the model to analyze the effect of various metal layouts such as distance of metal line to the edge of the IC (Figure 2, parameter ‘a’) and designs with and without bond pads outside the metal line. To obtain reliable models, reliable material models are vital. Because they are known to be strongly non-linear (depending on temperature, time, process conditions, etc) the materials are characterized. The molding compound is measured time and temperature dependent. For the thin film materials, warpage and indentation measurements are developed and performed [6]. Table 2 shows the materials and material models applied in the simulations. Table 2: Materials and material models applied. Item Lead frame Die attach
Material Cu Glue
Substrate Compound
Silicon EMC (Epoxy Molding Compound) Al
Metallization & bond pads Dielectrics
SiO2
Passivation
SiO2, PSG, SiN
Material model Elastic-plastic Temperature dependent Linear elastic Temperature and time dependent (visco-elastic) Elastic-perfectly plastic (temperature dependent) Isotropic, linear elastic Isotropic, linear elastic
The materials are activated during the simulation steps in order to describe the reality as close as possible and predict the correct stress history. Figure 6 shows the modeled temperature loading profile. It is mentioned that process times are taken into account in the simulations, but are not shown in this figure. Wafer Back-End Moulding +compound +lead frame
TCT
delaminated
Cure
Figure 6: Typical processes modeled, including delamination. The figure also shows when IC/compound delamination is added in the package. The wafer back-end processes are simplified as one cool down step from 450°C to RT with
only the IC materials activated (substrate, interconnect metal layers, dielectric, and passivation). The simulated packaging processes are the molding and curing processes. During these processes no delamination is present (perfect adhesion between all materials). Delamination at the IC/compound interface is included during TCT and the effect of this delamination is predicted in the subsequent TCT processes. The amount of delamination is taken as an input parameter in the simulations, thus initiation and growth is not predicted. In this way, the consequences of realistic and observed delamination are predicted without simulating initiation and growth of the delamination itself. Further model assumptions and simplifications are the following: • Isothermal conditions are assumed. • The stress free state of the materials is set at its process temperatures. • Intrinsic stresses in the dielectric and passivation layers are taken into account as initial stress state at 450°C. • Initial IC warpage is neglected. • J-integral values are calculated in the top layer only for a constant crack length. In the models several contact methods are applied to overcome the following modelling issues: 1. Meshing mm scale and nm scale in one model: • The ‘glued’ contact option is applied in order to use large elements in the silicon and small elements in thin film structures together in both 2D and 3D models. • In the 2D model ‘glued’ contact is applied to mesh the crack tip independently of the rest of the model (see magnification in Figure 4) • In the 3D model ‘glued’ contact is applied to allow a fine mesh in the corner metal layout together with a rough mesh in the rest of the model. 2. Modelling perfect adhesion and delamination in one simulation: • The ‘glued’ contact option is applied to simulate perfect adhesion in the first processes. Subsequently, in the last TCT processes, ‘touching’ contact is activated for the passivation/compound interface to include delamination. 3. Modelling the 3D corner effect of J-values: • Compound nodes are linked with IC nodes to simulate the interlocking effect of compound and passivation. The effects of crack length and crack direction are first established in separate 2D simulations [2]. All simulations are then performed with the same (critical) crack direction and length and J-integral values are predicted at the crack tip. Within one simulation, results are obtained for perfect adhered materials (no delamination) and for delaminated IC/compound
interface. Figure 6 shows where delamination is included during the temperature loading. The 2D model is meshed with 4-noded plane strain elements with enhanced bending description. The xdisplacements are linked for all nodes in the symmetry plane, see Figure 7. A single node is fixed in all directions near the small metal features. This technique is chosen to prevent large deformations in elements near the crack and in the compound, especially because the compound elements are activated when IC elements are already deformed (see Figure 6).
• Distance metal line / IC edge Figure 9 shows an example of a decapped sample. In this particular test structure, passivation cracks and metal shift are observed. A large amount of delamination at the IC/compound interface is found before TCT and after decapping (removal of compound) visual inspection clearly shows both failures.
Figure 7: Boundary conditions applied to prevent largely deformed elements. The 3D model aims at predicting the compound forces on the passivation in the IC corners. Links between the IC and the compound are added to simulate the interlocking effect of a metal line at that position. Figure 8 is a visualization of this model, showing the delaminated area (contact regions) and the links between the IC and the compound. The compound is artificially moved in vertical direction to visualize this. The distribution of the forces predicted by the 3D model is used to scale the numerical J-integral values predicted by the 2D simulations in order to obtain the corner effect on passivation cracks.
Figure 9: Observed metal shift (red circle) and metal wrinkling. It is clearly visible that the shifting of the metal line and bond pads runs from the corner towards the inside of the IC. Also notice the wrinkled metal surface, showing that the metal is pushed towards the centre of the IC. As mentioned above, delamination is observed in this failed sample. From all experimental observations, delamination at IC/compound interface is found to be the major trigger for passivation crack and metal shift. Figure 10 shows two identical structures from similar samples, but with different amounts of delamination. The difference in delamination is obtained by applying different MSL preconditioning (Moisture Sensitivity Level) to the samples. It can be seen that with delamination (left figure) metal shift is clearly visible and without delamination (right picture) no metal shift can be seen. In the right sample also no passivation crack is found.
Figure 8: 3D model showing contact bodies (exploded view) to include delamination on the IC/compound interface.
Figure 10: Comparison test structure S2 with delamination (left) and without delamination (right).
3. Results The observations from the experiments are described followed by the simulation results for the following effects: • Delamination • Metal design
The physics behind the mechanism is determined by the simulations and agrees with the experimental observations. Figure 11 shows the predicted failure mechanism where delamination of the IC/compound interface is of major influence on passivation cracking. The effect of metal layout design can now be analyzed for its effect on failures with or without the presence of
delamination. Because delamination is the key factor causing passivation crack and metal shift, further results are given for delaminated cases only.
shows major cracking and metal shifting as can be seen in Figure 9. The structures S5 and S6 show no failures. Therefore, the calculated ranking and experimental ranking agree very well. It is stated that the ranking is done with similar amounts of delamination in the experiments and simulations. It can be concluded that the simulations are able to predict passivation crack reliably. The simulation results show that the distance from the metal line to IC edge (a) has an important non-linear effect on the crack energy, which explains the ranking. This is visualized by S1 till S6 in Figure 12 having increasing ‘a’ respectively and S2 having the highest crack energy.
Figure 11: Compound (brown) pushing against the passivation (red). Metallization and substrate are not shown (white).
Calculated crack energy
Cracking energy
-65°C, 10% delamination
Cracking energy
J-integral level
With bondpad Without bondpad
0
1
2
3
4
5
6
Allowable Figure 13: J-level with and without bond pad outside the power line.
S1
S2
S3
S4
S5
S6
Figure 12: Calculated J-values with allowable crack energy from the experimental observations. By combining the simulation results with experimental observations, the allowable J-level of the passivation material is found. Figure 12 shows the predicted J-values for the test structures. Ranking the test structures from worst to best gives the following: • S2, S1, S3, S4, S5, and S6. The structures S2, S1, S3, and S4 consistently show failures to a different extent. For instance: structure S2
To analyze the effect of bond pads on the J-values, test structures are simulated without bond pads. Figure 13 shows that similar trends exist for the 6 test structures, but that the chance on cracking is about 5 times higher in areas where no bond pads are located. With the developed simulation models, able to predict the product/process behavior reliably and efficiently, simulation-based optimization is applied. Simulationbased optimization involves finding settings for a number of designs parameters that are optimal with respect to several simulated responses (J-integral value). Since there are many possible design/process parameter settings and because non-linear FE simulations are often time consuming, the crucial question becomes finding the best possible parameter setting with a minimum number of simulations. The disadvantage of direct optimization approaches is that little insight is obtained in the behavior of the responses in terms of the complete design space. Moreover, when the optimization problem changes (e.g., changing in the bound on a response parameter), the
optimization procedure has to be restarted. This paper uses our developed optimization strategy and method [7, 8]. This strategy focuses on the development of a reliable Response Surface Model (RSM) for the underlying nonlinear response by integrating the adaptive (sequential) Design Of Experiments (DOE) with advanced RSM methodologies. Once the RSM has satisfied the specified accuracy criteria, various types of design optimizations can be carried out efficiently. A space-filling Latin-Hypercube-Design of 20 variations is first constructed for two design parameters, silicon thickness and the distance metal line to edge of the IC (parameter a). Using the parametric non-linear FE models, simulations are carried out for all the 20 designs, and the resulting J-integral values are used as the response parameter.
Figure 14: RSM showing nonlinear effect of J-values as a function of silicon thickness and ‘a’. Figure 14 shows an example of the combined non-linear effects of the two parameters on passivation crack. The RSM is generated with quadratic models including interactions between the parameters. The design optimization problem is to choose the parameters such to minimize J-values, within the specified ranges of design variations. It can be seen that the J-values strongly depend not only on the distance 'a' but also on the die thickness in a non-linear way. This indicates that an optimum structure can be found based on these 2 parameters. 4. Conclusions From the experimental observations and the simulation results the following is concluded: • Delamination is the key trigger for passivation cracking and metal shift. Both in the experiments and from the simulations delamination is found to be the main cause for failures. • Metal layout has a major effect on passivation crack and metal shift. The simulations predicted failures in the same ranking as found from the experiments and show that metal layout can be optimized to prevent failures.
Based on the above, the simulation models and methodology are capable of predicting the effects of metal layout on failure occurrence, critical locations, and root causes. Furthermore, the developed methodology, models, and limited number of test samples can be used to predict failures prior to prototyping of real products. Acknowledgments The authors would like to acknowledge all Themert team members for their hard work and devotion. This work would not have been successful without the team spirit. References 1. Silfhout R.B.R van, Li Y., Driel W.D. van, Janssen J.H.J., Kuper F., Schravendeel R.L., Zhang G.Q., Gils M.A.J. van, Jansen M., “State of the Art on Thermo-Mechanical Modelling of IC Backend Processes”, Proc 2nd EuroSimE Conference, France 2001 pp. 277-289. 2. Silfhout R.B.R van, Roustant J.D., Driel W.D. van, Li Y., Zhang G.Q., Yang D.G., “Effect of Delamination of IC/compound Interface on Passivation Cracking”, Proc 4th EuroSimE Conference, France 2003, pp. 353-358. 3. Yuen M.F., Fan H., “Delamination of Electronic Packages”, Proc 4th EuroSimE Conference, France 2003, pp. 15-21. 4. Sauber J., “Modelling of Die Surface Features on Integrated Circuits to Improve Device Reliability”, MSC Users’ Conference, 1996. 5. Liu C.J., Zhang G.Q., Driel W.D. van, Silfhout R.B.R. van, Gils M.A.J. van, Ernst L.J. “Prediction of Interfacial Delamination in Stacked IC Structures using Combined Experimental and Simulation Methods”, Proc 4th EuroSimE Conference, France 2003, pp. 337-343. 6. Silfhout R.B.R van, Driel W.D. van, Li Y., Zhang G.Q., Ernst L.J., “Prediction of Back-End ProcessInduced Wafer Curvature and Experimental Verification”, ECTC 2002, pp. 123-128. 7. W.D. van Driel, G.Q. Zhang, J.H.J. Janssen, L. J. Ernst, “Response Surface Modelling for Non-linear Packaging stresses”, Journal of Electronic Packaging 125 (4), 2003, pp. 490-497. 8. G.Q. Zhang, J.Janssen, L.J. Ernst, J. Bisschop, Z.N. Liang, F. Kuper, and R. Schravendeel, “Virtual thermo-mechanical prototyping of electronic packaging using Philips’ optimization strategy”, IMAPS2000, USA, 2000.
