Platform of 3D Package Integration

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Wei Chung Wang1,2, Fred Lee1, GL Weng1, Willie Tai1, Michael Ju1, Ron Chuang1, Weileun ..... Xueren Zhang, and Tong Yan Tee, “Advanced Warpage.
Platform of 3D Package Integration Wei Chung Wang1,2, Fred Lee1, GL Weng1, Willie Tai1, Michael Ju1, Ron Chuang1, Weileun Fang2 1 Advanced Semiconductor Engineering Inc. Taiwan, R.O.C 2 MEMS Institute, National Tsing Hua University Hsinchu, Taiwan, R.O.C 1 26 Chin 3rd Rd., Nantze Export Processing Zone, Kaohsiung, Taiwan 811, R.O.C [email protected], +886-7-3617131 Abstract Package on Package (PoP) is a package technology placing one package on top of another to integrate different functionalities while still remains a compact size. PoP offers procurement flexibility, lower cost of ownership, better total system costs and faster time to market. Normally designers use top package for memory application and bottom package for ASIC, Baseband or Processor application. By using this PoP technology, the memory KGD issue can be mitigated since the memory to be integrated with bottom package can be burn-in and tested before integration with bottom package. In addition; the development cycle time and cost can be reduced since memory is decoupled from ASIC/Baseband/Processor from the perspective of qualification, yield, sourcing, procurement timing and logistic handling. However, stringent coplanarity control for bottom package is necessary to ensure high package stacking yield when combining with top packages that are normally coming from different sources with different warpage behavior. Besides, the customized mold chase fabrication is costly and time consuming for product prototyping. A state-of-the-art 3D package integration platform based on current FBGA infrastructure had been proposed, developed and validated to resolve the issues listed above and yet is complied with JEDEC package outline standard for PoP. Introduction The development work started in 2002 and was used in camcorder application. Initially the chip was packaged in a special PoP package which has an interposer between two packages to accommodate the thick (0.53mm) globe top on bottom package (shown in figure 1a), the product was then redesigned to remove the interpose for further total package height and cost reduction by using transfer molding process and then became a common 15mmx15mm PoP as shown in figure 1b. A turnkey flow includes memory assembly, memory B/I, memory final test, ASIC probe, ASIC package, ASIC final test, packages stack, and final stacked module test was developed. In the first generation PoP development, the key focus is to ensure high package stacking yield. Hence, a lot of efforts had been spent to the improvement of package warpage control of both top and bottom package, and also an unique “ball on ball” package stack technology is developed to accommodate excess top and bottom package warpage, the experiment data indicates that high stacking yield (99.7%) is achieved even in the warpage condition of average 100um and maximum 238um for bottom package. This technology also enables the adoption of thick mold cap of bottom package and finer (0.5mm) interconnection pitch between top and bottom package.

1-4244-0985-3/07/$25.00 ©2007 IEEE

+ + (a) Package on Package with Interposer

(b) Package on Package without Interposer Figure 1 Package on Package Configurations In view of the constraint of long prototyping cycle time coming from customized mold chase fabrication, a 2nd generation PoP package development was launched to eliminate the usage of top gate mold system. A trial of using releasing tape along with side gate mold system had achieved preliminary success, but it was then replaced by a mold array structure in considering of unit cost. The following sections are dedicated to describe issues encountered and corresponding resolution, a state-of-the-art 3D integration platform is designed and validated, package and board level reliability of this platform is also provided. Package Stacking Technology Understanding the package warpage behavior is essential to achieve high package stack yield of PoP. Basically PoP is a FBGA stacks on the top ball pads of a miniaturized PBGA. The warpage behavior of FBGA and miniaturized PBGA during reflow process will determine the stacking yield. There had been a lot of attention paid by researchers and engineers on package warpage improvement through process optimization or material properties optimization. [1-6]. In summary, package warpage is determined by properties of mold compound and substrate, die size and thickness, mold cap size and thickness, process conditions, etc. By changing the package characteristics and material properties mentioned above, package warpage could be manipulated from concave to convex contour. In traditional package design, the warpage direction (convex or concave) is not of concerned as long as the coplanarity could meet customer’s criteria or JEDEC standard. However, when the waprage directions of top and bottom package are different, the yield of package stacking

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h2

h1

H2

H1

C2 C1

Figure 2 : Warpage tolerance of BoP v.s BoB

Cell BoB - top ball dia. (mm) BoB - bottom ball dia. (mm) Sample size Package Stacking Yield Cell BoP - equivalent ball dia. (mm Sample size Package Stacking Yield

1 0.25 0.25 30 96.7% 1'

2 0.3 0.2 30 100% 2'

3 0.3 0.25 30 100% 3'

4 0.35 0.2 30 100% 4'

0.31 30 0%

0.33 30 0%

0.35 30 0%

0.37 30 0%

Table 1 : Package warpage tolerance DOE Max. tolerable warpage (um)

will be impacted, hence limits the flexibility of top package supplier sourcing which is one of the major advantages of PoP. A common understanding of warpage control requirement for bottom package is at least 100um and targeting for 80um in a 14x14 FBGA stacking on bottom PoP package with 0.27mm mold cap thickness. This warpage performance can be achieved through core material selection, optimization of core thickness and mold compound shrinkage rate, and a proprietary thermal process. However, it still requires 0.45mm size balls attached on top package to provide enough stand-off. Whenever thicker mold cap or finer top to bottom package interconnection pitch are required, an even more strict coplanarity will be required. This continuous push of coplanarity control during product miniaturization will prolongs development cycle time and limits component suppliers. A “ball-on-ball” package stacking technology is developed to alleviate coplanarity requirement. Comparing with the method of BoP (balls on pads), BoB (balls on balls) interconnection shows superior capability to accommodate package warpage. This can be explained through a simple and idealized calculation shown below. Figure 2 is a schematic drawing of maximum bottom package warpage state of BoP and BoB interconnection, the maximum tolerate warpage is defined as the situation where the outer most balls of top package just contact with ball pads or balls on bottom package. Hence h1 is approximately two third of the original diameter and h2 is approximately 85% of the original diameter while H1 and H2 are the sum of the corresponding value of two balls. Assuming same solder volume used for these two methods, figure 3 shows the maximum tolerable package warpage of BoP and BoB with different solder volume used, it indicates BoB is more tolerate to warpage by around 30um. An experiment was then conducted to validate the theory proposed above, the cells of experiment are designed as table 1, the total solder volume of cell 1,2,3,4 are same as cell 1’, 2’, 3’ 4’ correspondingly. The test vehicle selected for this experiment is a 14x14mm package with 0.27mm mold cap and 0.5mm package-to-package interconnection pitch. Package stacking yield and solder joint cross-section are the characteristics to be observed. The same manufacturing batch of top packages (max. warpage of 80um) is randomly used in all cells while bottom packages are categorized into two groups, one group with 80um max. warpage level (for BoP) and another with 120um max. (for BoB). Both groups pass normal distribution check by JMP.

120 100 80 60 40

C1 (BoB)

20

0 BoP Dia BoB Dia

C2 (BoP) 0.31

0.33

0.35

0.37

0.38

0.25/0.25

0.3/0.2

0.3/0.25

0.35/0.2

0.3/0.3

(mm)

Figure 3 : Maximum tolerable warpage of BoP and BoB

Cell 1 : 0.29mm Avg.

Cell 2 : 0.30mm Avg

Cell 3 : 0.28mm Avg.

Cell 4 : 0.29mm Avg

Figure 4 : Solder joint Shape and Stand-off (0.27mm cap) As the yield data listed in table 1, BoB shows superior warpage tolerance than BoP and also capability of 0.5mm interconnection pitch. The yield of all BoP cells are 0% due to open failure mode while only 1 unit from cell 1 of BoB cells failed due to open failure mode. The 100% fail of BoP cells is due to the interference of bottom package mold cap. 0.27mm thick mold cap is used in this experiment, hence most of the solder balls could not touch with ball pads even in cell 4’ which use the largest solder ball diameter. An interesting observation on the solder joint cross-section is that the average solder joint heights of Cell 1 to Cell 4 are equivalent, only shapes are different. Figure 4 shows the details of each cell, and the cross-section images again reflect the interference of mold cap during stacking. The solder joint shape of cell 1 & 2 are obviously in a stretch state that can potentially induce open failure in high coplanarity packages and the yield data does support this theory. Actually, cell 3 & 4 are also in a stretch state, this can be tell from the equivalent ball diameter and the solder joint height after package stack.

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Stand-off : 0.39mm Avg

(a)

Figure 5 : Solder Joint Shape and Stand-off (0.35mm cap) Cell 3 is selected as the optimal solution since it uses standard FBGA ball diameter for top package and the solder joint shape is less stretched. A confirmation run of sample size 5742ea with maximum 149um coplanarity is conducted, 100% package stacking yield is achieved. In order to explore the capability of BoB, a thicker mold cap (0.35mm) is used to see if BoB is still capable to accommodate. Figure 5 is the cross-section of BoB interconnection using 0.35mm ball diameter for both top and bottom package. This result shows a PoP package with 0.35mm mold cap and 0.5mm interconnection pitch is feasible when BoB is adopted. Comparing with BoP interconnection that requires 0.45mm ball size (equivalent ball size of two 0.35mm balls) for 0.27mm mold cap and 0.65mm interconnection pitch, BoB exhibits superior capability Challenges of Package on Package The feature of decoupling the devices in top and bottom packages from the aspects of development, qualification, sourcing and logistic management is the main advantage of PoP. Hence, total cost of ownership and development cycle time can be reduced. However, the infrastructure is yet to be established since top gate mold system is not current prevailing type and mold chase is customized per package size and mold cap thickness. Before the completion of this infrastructure, the prototyping cycle time is much more longer than current FBGA due to the fabrication of mold chase and the production volume ramp is constraint by top gate mold system availability. Besides, warpage control and fine pitch interconnection are still challenges down the road of miniaturization. A 2nd generation PoP which can use side gate mold system and resolve the challenges is the object to be developed. Release Film Assisted Side Gate Mold PoP To adopt side gate mold system, the easiest way is to sacrifice several corner balls as figure 6a shown for gate insert location; however, this layout of ball pads does not comply with JEDEC standard of top package and will also limit total available ball counts for top package. To be able to keep the location of gate insert available for interconnection, a high temperature resistance tape is attached on substrates before assembly process (figure 6b), the gate insert will only contact with the tape during molding process (figure 6c) and can be easily removed. By using this release film, side gate mold system can be used for JEDEC standard PoP and yet mold flash issue is totally resolved since mold flash will only remain on tape and will be completely removed.

(b)

(c) Figure 6 : Side Gate Molding with Release Film

Figure 7 : Top Gate Molding for PoP Comparing with this release film assisted side gate molding PoP, top gate molding PoP (figure 7) has higher substrate utilization rate which results in lower unit cost since the former one need to leave extra space for the gate inserts in array type substrate design. This is an extremely critical factor for PoP to meet cost target of portable electronics market. Hence further re-engineering of PoP is required to be able to use side gate mold system for molded array type substrate. Mold Array Package type PoP (MAPPoP™) The function of ball pads on the top side peripheral of PoP substrate is to connect with top package terminals, hence the original mold chase was designed as individual cap for each die on the substrate to keep ball pads exposed, as shown in figure 7. This design concept makes top gate system necessary and mold chase dependent upon package size. A manufacturing flow re-engineering is conducted to resolve this issue. Figure 8 is the re-engineered process flow of Mold Array Package type PoP (MAPPoP™), this flow adds a proprietary, low cost process of interconnection implant to facilitate the use of fin gate mold system, and also makes mold chase independent of package size.

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Table 2 : Coplanarity Comparison

Bottom PKG

Top PKG

PoP Type

Die Count/ Thickness

Die Size (mm)

Single/ 75um

8.8X8.6

Stacked/ 50um

8.8X8.6 + 4.0X4.0

Interconnection Implant TRD PoP MAPPoP™

D/A, W/B, M/D & Solder Printing

TRD PoP

+

MAPPoP™

Coplanarity (um) Mean

Max

Min

Std Dev

S/S

84.9

115.8

64.7

9.4

153

50.7

93.0

22.0

12.7

309

66.2

127.0

43.8

15.1

208

48.9

85.5

33.3

9.7

116

Table 3 : Coplanarity of Different BOM Compound A

Compound B

Coplanarity (um) Max/Mean/Min Std Dev Max/Mean/Min

Figure 8 : MAPPoP™ Process Flow

Coplanarity

90 80 70 60 50 40 All Pairs

E-679FGB

Tukey-Kramer Core Material

0.05

t-Test Difference Estimate

2.54709

Std Error

0.99716

Lower 95%

0.58737

Upper 95%

4.50681

t-Test 2.554

DF 445

95 / 66 / 51

8.6

91 / 55 / 36

10

MGC 832NX

98 / 65 / 40

9.5

92 / 58 / 36

10.26

MAPPoP™ has a mechanically more balanced structure than traditional PoP as the package is fully covered by molding compound. This will result in better coplanarity performance. An array type 1/2/1 substrate for 14x14mm package size with 0.3mm total thickness was used to build both traditional PoP and MAPPoP™ for coplanarity performance comparison. Both single die and stack die configurations are built in this study, and the mold cap thickness for traditional PoP is 0.27mm while that for MAPPoP™ is 0.25mm. Table 2 is the coplanarity summary of each configuration by using the same molding compound. It indicates MAPPoP™ is superior to traditional PoP by 35um in average for single die case and 17um for stack die case. In addition, the embedded interconnections can provide stand-off ranges from 50um to 200um for top package solder balls through control of different milling depth, hence 0.3mm ball diameter for top package is feasible for 0.65mm pitch or even 0.5mm pitch. An in-situ optical microscope is used for the behavior observation of a 0.65mm pitch FBGA with 0.3mm size SAC105 solder balls stacking on a MAPPoP™. It indicates solder joints start to collapse at about 210oC and reach the lowest height at 217oC, this temperature range is close to the pasty temperature range of SAC105 composition. Through the design of embedded interconnection pad size and stand-off of bottom package, ball size of top package, the total stacked MAPPoP™ thickness can be same as traditional PoP while has the capability of 0.5mm interconnection pitch and can be assembled on PWB without pre-stack of top and bottom package.

Figure 9 : Optical Microscope Image of MAPPoP™

832NX

Std Dev

E679-FGB

Prob > |t| 0.0110

Assuming equal variances

Figure 10 : Coplanarity of Different Substrate Core After molding process, a mechanical milling process and solder printing process will be conducted to compose the interconnection pads on top side. Figure 9 is the optical image of the top side of MAPPoP™ before singulation. A MAPPoP™ package will be completed after normal marking, ball mount and singulation process.

Reliability The test vehicle used for coplanarity comparison is assembled for reliability characterization of MAPPoP™ structure. Both package level and board level tests are conducted to understand the characteristics of MAPPoP™. For package level reliability tests, two substrate core material types (MGC 832NX, E-679-FGB) and two molding compound types are selected for comparison. All of them are halogens free material. The result shows all of them can pass MSL 3 with 260oC peak temp followed by TCT1000 cycles, HAST96hrs, THT1000hrs, and HTST1000hrs with sample size of 77ea for each item. E-679-FGB is superior to 832NX

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in terms of coplanarity as figure 10 shown, but the improvement is less significant compared with mold compound effect as table 3 shown. For board level characteristics, drop test is the main interest since the application of this package is for hand held devices and which is more prone to drop during field application environment. Different solder ball composition of SAC105, SAC305 and LF35 with Ni/Au substrate surface finish are built for drop performance comparison [7], the test board and test conditions are listed below. Test Board – Dimension (L x W x t) : 132 x 77 x 1 (mm) Ball Pads Size : 0.28mm Solder Mask Opening : 0.43mm (NSMD) Surface Finish : Cu/OSP Via : 0.11mm (Via in Pad) Material : FR4 Layers : 8L Supplier : Ibiden Test Conditions – Package Direction – Facing Downward Test Standard – JESD22-B110 Condition B Peak Acceleration – 1500G (+/- 20%) Pulse Duration – 0.5ms (+/- 30%) Velocity Change – 467cm/s (+/-10%) Failure Criteria – 1000ohm detected for followed by 3 additional such events during 5 subsequent drops. Figure 11 is the Weibull chart of these three lead free solder composition, LF35 shows better performance than SAC105 and both pass at least 30 drops for all samples. As to SAC305, this composition exhibits shorter characteristic life and the shortest life sample only survived 17 drops. Probability - Weibull 99.00

Weibull LF35

90.00

F=28 / S=32 SAC105 F=31 / S=13

63.2

SAC305 50.00

Acknowledgments The authors would like to appreciate ASE Corp. R&D stress Lab for conducting drop test, and ASEK QA Lab for conducting package reliability tests. References 1. T. M. Wang, I. M. Daniel, and J. T. Gotro, “Thermoviscoelastic Analysis of Residual Stress and Warpage in Composite Laminates,” J. of Composite Material, vol. 26, no. 6, 1992, pp. 883-899. 2. S. Banerji, P. M. Raj, F. Liu, et al, “The Role of Stiff Base Substrates in Warpage Reduction for Future HighDensity-Wiring Requirements,” Proc. of 8th International Symposium on Advanced Packaging Materials, 2002, pp.221-225. 3. R. L. Shook, J. J. Gilbert, E. Thomas, et al, “Impact of Ingressed Moisture and High Temperature Warpage and High Temperature Warpage Behavior on the Robust Assembly Capability for Large Body PBGAs,” Proc. of 53rd ECTC Conference, 2003, pp. 1823-1828. 4. Xueren Zhang, and Tong Yan Tee, “Advanced Warpage Prediction Methodology for Matrix Stacked Die BGA during Assembly Processes,” Proc. of 54th ECTC Conference, 2004, pp. 593-600. 5. D. G. Yang, K.M.B. Jansen, L. J. Ernst, et al, “Prediction of Process-Induced Warpage of IC Packages Encapsulated with Thermosetting Polymers,” Proc. of 54th ECTC Conference, 2004, pp. 98-105. 6. Sung Yi, Paresh D. Daharwal, Yeong J. Lee, et al, “Study of Low-modulus Die Attach Adhesives and Molding Compounds on Warpage and Damage of PBGA,” Proc. of 56th ECTC Conference, 2006, pp. 939-945. 7. ASE Internal drop test report of 14x14 352L MAPPoP™

Unreliability, F(t)

F=43 / S=2

Conclusions A state-of-the-art 3D package integration platform based on current FBGA manufacturing infrastructure had been proposed, developed and validated. This platform demonstrates superior capability in the aspects of warpage characteristics, time to market, time to high volume ramp, total cost of ownership, finer pitch capability, and package stacking yield. Both package level and board level reliability are conducted to qualify this package and the result is promising.

10.00

5.00

1.00 10.00

100.00 Drop, (s)

1000.00

β1=2.8368, η1=276.4715, ρ=0.9698 β2=1.9288, η2=240.6340, ρ=0.9774 β3=2.3305, η3=175.9441, ρ=0.9963

Figure 11: Drop test performance of MAPPoP™

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