Polycrystalline silicon-germanium films for integrated ... - IEEE Xplore

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JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 12, NO. 2, APRIL 2003

Polycrystalline Silicon–Germanium Films for Integrated Microsystems Andrea E. Franke, John. M. Heck, Tsu-Jae King, Senior Member, IEEE, and Roger T. Howe, Fellow, IEEE

Abstract—Two approaches were demonstrated for fabricating microstructures after completion of CMOS circuits with aluminum metallization. The first approach employed n-type poly-Ge deposited at 400 C as a structural material with an SiO2 sacrificial layer and an HF release. The CMOS circuits were protected from the release etchant with an amorphous Si layer. Clamped-clamped lateral resonator test structures had quality . Following a 500 C, 30 s factors in vacuum as high as RTA the poly-Ge stress was 200 MPa (tensile) and the resistivity was 5.3 m -cm. In the second integration approach, p-type poly-Si0 35 Ge0 65 deposited at 450 C was the structural material with poly-Ge as the sacrificial material and H2 O2 as the release etchant. The H2 O2 did not significantly etch the p-type poly-SiGe structural layer and no protection of the underlying CMOS layers was needed. For the first time, the fabrication of LPCVD surface microstructures directly on top of standard electronics was demonstrated, providing dramatic reductions in both MEMS-CMOS interconnect parasitics and device area. A folded flexure lateral resonator had a quality factor in vacuum as high as . No stress or dopant-activation anneal was needed, since the in situ boron-doped poly-SiGe was found to have an as-deposited stress of only 10 MPa (compressive) and a resistivity of only 1.8 m -cm. [761]

30 000

15 000

Index Terms—Microelectromechanical (MEMS) devices, microresonators, CMOS integrated circuits, semiconductor films.

I. INTRODUCTION

T

HE integration of MEMS with electronics by cofabrication has several advantages compared to multichip implementations. With the MEMS and electronic circuits on separate chips, the parasitic capacitance and resistance of the interconnects, bond pads, and bond wires can attenuate the signal, contribute significant noise, and place a ceiling on the maximum operating frequency. This problem is especially severe for thin-film, surface-micromachined structures in which position is sensed capacitively. Having the MEMS devices and electronic circuits on the same die also reduces packaging complexity and improves Manuscript received September 21, 2001; revised July 8, 2002. This work was supported under Grant EEC-9712750 from the National Science Foundation. Subject Editor K. D. Wise. A. E. Franke is with the Department of Electrical Engineering and Computer Sciences and Berkeley Sensor and Actuator Center, University of California at Berkeley, Berkeley, CA 94720-1770 USA. J. M. Heck is with the Berkeley Sensor and Actuator Center, and Applied Science and Technology, University of California at Berkeley, Berkeley, CA 94720-1770 USA and also with Microsystems Technology group at Intel Corporation, Santa Clara, CA 95050 USA. T.-J. King is with the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720-1770 USA. R. T. Howe is with the Department of Electrical Engineering and Computer Sciences, Berkeley Sensor and Actuator Center, and Department of Mechanical Engineering, University of California at Berkeley, Berkeley, CA 94720-1770 USA. Digital Object Identifier 10.1109/JMEMS.2002.805051

reliability by minimizing the number of off-chip electrical connections. Monolithically integrating multiple sensors with electronics enables sensors measuring motion along different axes to be precisely aligned, to share data easily, to have greater accuracy, and to be less susceptible to external disturbances. Finally, depending on the integration strategy that is adopted, there may be significant overall cost savings by cofabricating the microstructures and electronics on the same substrate. Although there are substantial benefits to integrating MEMS and electronics, several challenges have to be addressed. A low thermal budget is required after metallization of the electronic circuits to prevent junction spiking, metal hillocking, parametric shifts due to dopant diffusion, or diffusion of Cu into low-k interlayer dielectrics. The maximum temperature allowed after metallization depends on the particular core and barrier metals used and is in the range of 400–500 C. A second issue is the relatively thick MEMS structural and sacrificial layers (2–10 m thick), which create significant height variations on the wafer surface. High-resolutionlithography,whichisneededforsubmicroncomplementary metal-oxide-semiconductor (CMOS) technology, is not possible on such rough surfaces. Electrical interconnects between the MEMS and electronics are also an important consideration, since they should be minimum length and be made in a highly conductive layer to minimize parasitic resistance and capacitance. Finally, it may be necessary to protect the on-chip electronics from the MEMS release etchant. There are three general approaches to integrating MEMS and electronics. The MEMS fabrication can be done in a module that precedes the electronics module [1], the fabrication steps for the electronics and MEMS can be interleaved [2]–[8], or the MEMS can be fabricated modularly after the electronics [9]–[20]. Interleaving the processes leads to processing compromises that limit microsystem performance. Since foundries cannot be used, considerable capital investment is necessary. Modular integration, on the other hand, offers several advantages over interleaving strategies. Since separate development and optimization of both MEMS and electronics processes is possible, modular integration should lead to much higher performance devices. Of the two modular approaches, the CMOS-first approach is the most desirable. If the MEMS are fabricated before the electronics, the increased topography is an issue which can be addressed, yet low-cost, state-of-the-art, commercial electronics foundries cannot be employed. If the MEMS are fabricated after the electronics, foundry CMOS can be used and the required capital investment would be greatly reduced. Historically, the major challenge with post-CMOS modular integration of MEMS has been the thermal processing budget. However, Ge as MEMS processes employing poly-Ge or poly-Si

1057-7157/03$17.00 © 2003 IEEE

FRANKE et al.: POLYCRYSTALLINE SILICON-GERMANIUM FILMS FOR INTEGRATED MICROSYSTEMS

PROPERTIES OF Si, Si

Ge

AND

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TABLE I Ge. VALUES ARE FOR SINGLE CRYSTAL MATERIAL, EXCEPT FOR THOSE MARKED “POLY” WHICH ARE VALUES FOR POLYCRYSTALLINE MATERIAL

a structural material can be performed with adequately low thermal budgets to allow integration after standard electronics Ge films fabrication. In this paper, the properties of poly-Si relevant for integrated MEMS application are described. Then, two approaches for fabricating microstructures in a modular fashion after completion of CMOS circuitry are presented: the first employing n-type poly-Ge as the structural material and SiO as the sacrificial material, the second employing p-type as the structural material and poly-Ge as the poly-Si Ge sacrificial material. Finally, remaining challenges for integrated Ge are discussed. MEMS technology using poly-Si II. PROPERTIES OF POLY-Si

Ge FILMS

In this section, selected properties of poly-SiGe films are described and compared to those of poly-Si films. For reference, a and Ge is procomparison of the properties of Si, Si Ge vided in Table I. A. Fabrication Processes Ge has been extensively 1) Deposition: Poly-Si studied in recent years as an electronic material for application in heterojunction bipolar junction transistors (BJTs) with Ge as the base material [29], [30] and in CMOS devices Si Ge as the gate, source/drain, or channel with poly-Si material [31]–[33]. Therefore, its deposition behavior (Fig. 1) and electrical properties are fairly well known. Conventional Ge LPCVD equipment can be used to deposit Poly-Si films by thermal decomposition of germane (GeH ) and silane (SiH ) [35] or disilane (Si H ) [36]. Si deposition is catalyzed by the presence of Ge, so that the film deposition rate increases dramatically with increasing Ge content when deposition is limited by surface reactions. Reasonable deposition rates (greater than 50 min) can be achieved at temperatures below

Fig. 1. Deposition rate versus inverse of deposition temperature for films of various Ge mole fractions. Adapted from [35] and [38]. Films were deposited in a conventional LPCVD furnace using SiH and/or GeH as the gaseous sources. In the present work, poly-Si Ge films were doped in situ either by adding PH , which lowered the deposition rate, or by adding B H , which raised the deposition rate.

475 C for films with greater than 50% Ge content, and at temperatures down to 340 C for pure Ge [37]. Ge films can be heavily doped by the incorporaPoly-Si tion of dopants in situ during deposition [39] or ex situ by ion implantation and subsequent thermal annealing [40]. The resisGe films generally decreases with tivity of p-type poly-Si Ge content, due to increases in carrier mobility and dopant activation rate. However, the resistivity of n-type films increases 40 , due to reduced dopant actiwith Ge content above vation [40]. In this work, in situ phosphorus-doped poly-Ge structural films were and in situ boron-doped poly-Si Ge studied. The n-type poly-Ge was deposited at 400 C and 300

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mtorr, at a rate of 210 min by pyrolysis of 219 sccm of GeH and 5 sccm of 50% PH /50% SiH . The resistivity of the as-deposited n-type poly-Ge was found to be 20 m -cm. The p-type wa deposited at 450 C and 600 mtorr, at 170 poly-Si Ge min by pyrolysis of 85 sccm of SiH , 90 sccm of GeH and 50 sccm of 10% B H /90% SiH . The resistivity of the was 1.8 m -cm, remarkably low bep-type poly-Si Ge cause of the high dopant activation and carrier mobility compared to n-type poly-SiGe [40]. Ge alloys can be etched in 2) Plasma Etching: Poly-Si fluorine-, chlorine-, and bromine-containing plasmas including CF , SF , Cl , HBr or CHF [41]–[44]. Selective etching of both Ge and Si with etch-rate ratios as high as 40 for Ge:Si 70 for Si:Ge has been demonstrated [41]. The etching and of Ge by fluorine atoms is much less dependent on ion bombardment than the etching of Si. Thus, by using a CF plasma at higher pressure, the importance of ion bombardment is reduced, and the Ge:Si etch rate ratio is enhanced. Conversely, using a SF H CF plasma, the Si:Ge etch rate ratio is enhanced, due to the formation of a carbonaceous material and a germanium-sulfide compound on the Ge surface. In this work, a Cl /HBr etch chemistry was used to etch the structural poly-Ge materials, at a pressure of 15 mT, an RF or poly-Si Ge power of 300 W at the top electrode, an RF power of 150 W at the bottom electrode, a gap of 5.8 cm, Cl flow of 50 sccm, and HBr flow of 150 sccm. These conditions were found to etch poly-Ge and poly-Si at 0.41 and 0.16 m/min, respectively, and the etch rate increased approximately linearly with Ge content. 3) Chemical Etching: In this work, two chemical solutions Ge selectively to Si and SiO : RCA were used to etch poly-Si SC-1 solution, and hydrogen peroxide. RCA SC-1 is a commonly used cleaning solution for silicon wafers [45], which consists of ammonium hydroxide, hydrogen peroxide and deionized H O, 1:1:5) heated to 75 C. It has water (NH OH H O Ge , with been shown to be an effective etchant for poly-Si etch rate increasing exponentially with Ge content [46], [47]. The second etchant, hydrogen peroxide (30% in water) heated to 90 C, was first reported to etch germanium in 1959 [48], Ge for . [49], with excellent selectivity to poly-Si Therefore, hydrogen peroxide is particularly useful as a release etchant that can remove a poly-Ge sacrificial layer without structural layer developed attacking the p-type poly-Si Ge for the integrated MEMS process. Ge films of various composiThe etch rates of poly-Si tions in RCA SC-1 and hydrogen peroxide were measured. The films were deposited onto thermally oxidized silicon wafers and patterned with lithography and plasma etching. The solutions were heated in a convection oven, and once the temperature had stabilized, chips diced from the wafers were immersed in the solutions. The film thicknesses were measured before and after etching using a Nanospec microspectrophotometer or by profilometry. The thickness of the 80% and 100% Ge films were measured by profilometry since the Nanospec was not calibrated for Ge film measurement. Fig. 2 shows the etch rates as a function of Ge content, determined by Rutherford backscattering spectrometry (RBS). 4) Annealing: In order to maintain a low thermal processing budget for the n-type Ge MEMS fabrication process, rapid

Fig. 2. Etch rate of poly-Si peroxide.

Ge

films in RCA SC-1, and hydrogen

thermal annealing (RTA) by high-power tungsten-halogen lamp irradiation was employed to lower the resistivity of the poly-Ge films. Because Ge has a lower energy band gap than Si, it absorbs the lamp radiation much more efficiently than Si. Its higher absorption coefficient results in selective heating of Ge during the anneal [50]. This feature can be exploited to realize higher annealing temperatures for integrated poly-Ge MEMS devices than would otherwise be possible with furnace annealing. The selective annealing of structural films is a novel approach to the integration of MEMS with microelectronics. The annealing temperature during RTA was monitored by a thermocouple attached to a small piece of Si located inside the quartz chamber. Because of the differential heating effect, the actual temperature of the poly-Ge film during the anneal is not known. The temperature during anneal is expected to be less for patterned poly-Ge films compared to unpatterned films, due to two-dimensional edge-cooling effects. In this paper, results are reported for patterned poly-Ge films annealed at 550 C for 30 s. The 550 C, 30 s anneal was confirmed to have no adverse effect on the electrical performance of the underlying CMOS devices (see Fig. 12). The resistivity of n-type poly-Ge films decreased from 20 to 5.3 m -cm after RTA treatment. B. Mechanical Properties In order to study residual stress, fracture strength, and quality factor, microstructures were fabricated using the following processing sequence: first, a 2- m-thick sacrificial film of phosphosilicate glass (PSG) was deposited onto a Si wafer; then was deposited and n-type poly-Ge or p-type poly-Si Ge patterned using a Cl /HBr dry etch process. Finally, the structures were released using a timed etch in a hydrofluoric-acidcontaining solution, followed by a rinse in deionized water and methanol and CO critical-point drying. 1) Residual Stress and Strain Gradient: Residual stress in 5.1- m-thick patterned n-type poly-Ge films was determined by analyzing microstructures designed to determine stress (see Fig. 3). These structures are anchored in the square regions located at the left and right. Any residual stress causes the beams to expand or contract upon release, and their resultant relative motion can be determined using the verniers. Unannealed poly-Ge microstructures were found to have 100 MPa (tensile)


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Fig. 3. Microstructures used to measure residual stress. In the lower, right figure there are four pairs of structures with increasingly long beams. The anchors of the upper three pairs are outside the field of view.

stress. After 550 C, 30 s RTA, the stress increased to 200 MPa (tensile). A value of 132 GPa was used for the Young’s modulus in order to calculate the stress from strain measurements. The vertical tip deflection of 1-mm-long cantilever beams was measured with an optical microscope [51]. The strain gra, where dient was then calculated from the formula is the tip deflection and is the beam length, and was found to m for as-deposited poly-Ge. A 550 C, 30 s be 1.3 10 m . Increasing RTA reduced the strain gradient to 9.4 10 the 550 C RTA time to 120 s further reduced the strain gradient m . to 1 10 The residual stress of 3.1-mm-thick patterned p-type films was so low that it could not be acpoly-Si Ge curately measured using the microstructures in Fig. 3. Instead, a microstructure providing a mechanical amplification of the strain had to be used [52]. Stress was calculated with an estimated Young’s modulus of 146 GPa to be 10 MPa (compressive), which is quite low for an as-deposited film. The strain gradient m for as-deposited p-type poly-Si Ge . was 1.9 10 2) Fracture Strain: The fracture strengths of the structural films were characterized by measuring the strain state in cantilever beams as they fractured due to in-plane bending. The test structure which was used for these measurements is shown in Fig. 4, and has previously been used to measure the fracture strength of poly-Si [23], [53]. This device consists of a folded-flexure supported shuttle which has an array of six cantilever beams (the test specimen) attached to it. The shuttle is pushed by an off-chip motorized micrometer probe, and its motion is constrained along the longitudinal axis by the flexure. As the shuttle advances, the beams bump into contacts. The displacement of each beam is tracked to an accuracy within 0.2 m using a video image capture system. From the displacement at fracture, the maximum strain at failure for each beam can be calculated using nonlinear beam theory. Details of this analysis method have been published previously [53].

Fig. 4.

Test device to measure fracture strength. A probe is pushing the shuttle.

The cantilever beams tested have lengths of 50, 60, and 70 m. Beam widths were measured in a calibrated scanning elecm. A tron microscope (SEM) and found to be 3.5 total of 36 unannealed poly-Ge beams and 34 poly-Ge beams annealed at 550 C for 30 s were tested. The measured frac0.3%, ture strain for the unannealed poly-Ge was 1.1% but the annealed poly-Ge had significantly improved fracture 0.3%. A total of 28 unannealed p-type strength of 1.7% beams were tested, and the fracture strain was poly-Si Ge . found to be In comparison, phosphorus doped poly-Si structural layers fabricated with the Microelectronics Center of North Carolina (MCNC) Multi-User MEMS Process (MUMPS) exhibit a 0.2% (2.6 GPa 0.3 GPa) strain at fracture of 1.5% when measured using the same test device structure [23]. The MCNC poly-Si films were deposited at 610 C and 300 mtorr and subsequently annealed at 1050 C for 30 min. These results indicate that the strength of the n-type poly-Ge and p-type films is comparable to that of poly-Si. poly-Si Ge 3) Quality Factor: Clamped-clamped n-type poly-Ge resonators [26], [54] were tested to determine quality factor, .

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Fig. 5. Frequency (amplitude and phase) characteristics of an n-type poly-Ge resonator.

Fig. 6. poly-Si

Resonant frequencies were first determined by observing the structures resonate in air. The resonators were excited with a 10 - ac signal and 30–80 V dc across the drive combs. Measurements of were performed in a vacuum probe station under pressures ranging from the tens of mtorr to the tens of torr. An HP4195A network analyzer was used to supply 707 V–5 mV ac and 5–40 V dc to the resonator drive electrode. Current from the sense electrode was fed to an off-chip electromechanical amplitude modulation (EAM) circuit with a gain of 1 M before reaching the network analyzer [55]. The EAM circuit was used to minimize parasitic effects and to determine accurately. As frequency is scanned, resonance can be located by a sharp peak in , where amplitude together with a 180 phase shift. is is the resonant frequency and is . dB dB Quality factors as high as 30 000 were measured at a resonant frequency of 32.479 kHz for n-type poly-Ge (Fig. 5). folded-flexure resonators were P-type poly-Si Ge driven in vacuum to determine their quality factor. The resonators were excited with a 53 mV - ac signal and 7 V dc on the drive electrode, and at a pressure of 290 torr. Current from the sense electrode was fed to the EAM circuit. Quality factors as high as 15 000 were measured at a resonant frequency of 11.783 kHz (Fig. 6). 4) Microstructure: Transmission electron microscopy (TEM) was performed on patterned, as-deposited n-type poly-Ge (Fig. 7) and patterned poly-Ge that had been annealed at 550 C for 5 minutes in N (Fig. 8). For MEMS fabrication after electronic circuit fabrication, a 550 C anneal for 30 s was performed to lower the resistivity and stress gradient of the poly-Ge. A longer anneal of 5 min was performed on the sample sent for TEM analysis so that the equilibrium crystal structure could be more accurately predicted. The microstructure of the as-deposited poly-Ge is equiaxed; i.e., there is no preferred growth direction (see Fig. 7). The grain size remains constant through the thickness of the film. Since the deposition temperature, 400 C, is over 100 C above the amorphous/polycrystallinetransitiontemperature,insituphosphorous doping may inhibit nucleation and a columnar microstructure. The 550 C, 5 min anneal resulted in a surprisingly large amount of grain growth (Fig. 8). The average grain size in the as-deposited films was 200–600 , and after the anneal the average grain size was about 1 m. The poly-Ge that was annealed at 550 C for 5 min had a stress of 290 MPa (tensile),

Fig. 7.

Frequency (amplitude and phase) characteristics of a p-type Ge resonator.

Cross-sectional TEM of as-deposited n-type poly-Ge.

calculated from measurements of strain and an estimated Young’s modulus of 132 GPa. In comparison, the as-deposited poly-Ge had a stress of 100 MPa (tensile) and a 550 C, 30 s RTA increased the stress to 200 MPa (tensile). The significant grain growth resulted in contraction of the film as loosely packed grain boundaries were eliminated. Since the film was constrained by the substrate, tensile stress resulted. The larger thermal expansion coefficient of the Ge compared to the Si substrate also contributed to the tensile stress. TEM was also performed on an as-deposited p-type film (Fig. 9). The microstructure of the poly-Si Ge is columnar with small grains at p-type poly-Si Ge the bottom of the film. This microstructure is predicted to give compressive stress with higher compressive stress at the bottom of the film due to competitive grain growth and thus a positive, upward-curling strain gradient. This agrees with the measured stress of 10 MPa (compressive), and the positive m . These results are similar strain gradient of 1.9 10 to those for poly-Si films with columnar microstructure [56]. Unlike as-deposited poly-Si, however, the magnitude of the


Fig. 8. Cross-sectional TEM of n-type poly-Ge annealed at 550 C for 5 min. Four grains are numbered.

stress of the p-type poly-Si Ge is quite low. Lowering the deposition temperature so that it is closer to the amorphous/polycrystalline transition temperature would give a more equiaxed microstructure and possibly lower the strain gradient of the as-deposited films. III. MODULAR INTEGRATION OF MEMS WITH ELECTRONIC CIRCUITRY Fabricating the MEMS after the electronics allows semiconductor foundries to be used, minimizing the capital investment needed and leveraging state-of-the-art electronics technology. The major challenge with post-CMOS modular integration of MEMS is the thermal budget limitation imposed on the MEMS fabrication process. However, MEMS processes employing poly-Ge or poly-SiGe as a structural material can be performed with an adequately low thermal budget to allow integration after standard CMOS fabrication. A. Structural N-type Poly-Ge and Sacrificial SiO In traditional MEMS fabrication, n-type poly-Si is used for the structural layer and SiO is used as the sacrificial material. For an initial demonstration, wafers with completed CMOS electronic circuits designed for n-type MEMS were fabricated, and so n-type Ge films were studied. Poly-Si Ge films with poly-Si less than 1 were found to be too resistive for MEMS applications, even after low thermal budget anneals that were compatible with the electronics. Therefore, n-type poly-Ge was used as the structural layer and SiO was used as the sacrificial layer. The starting substrates were four-inch diameter Si wafers with amplifier circuits covered with a SiO passivation layer. These circuits were fabricated using a baseline, 3 m gate length, CMOS technology in 1992, and archived (Fig. 10). To form metal interconnects and complete the electronics fabrication, contact openings were formed in the passivating

Fig. 9.

Cross-sectional TEM of as-deposited p-type poly-Si

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Ge

.

SiO layer, and then 5000 of Al-Si(2%) was sputtered and patterned using standard lithography and dry etch processes. No barrier layer was used between the Si and the Al-Si(2%) metal interconnect. Such a layer would help to prevent problems with junction spiking during the deposition and annealing steps of the MEMS fabrication process, and may be necessary for more advanced CMOS technologies due to the shallower source/drain junction depths. The circuit fabrication was completed with a 400 C, 30 min sintering anneal. The CMOS circuitry was protected with a bilayer of low temperature oxide (LTO) and undoped amorphous Si ( -Si). The 6750 thick layer of LTO was deposited at 400 C in 1 h. The 590 thick -Si was deposited in two steps: the first at 450 C for 6 min and the second at 410 C for 40 min. Both -Si depositions were at 500 mtorr and with 200 sccm of Si H . The purpose of the 590 thick -Si layer was to protect the CMOS devices during the HF release etch for the MEMS structures. In order to minimize the possibility of HF penetrating the -Si through pinholes, the -Si layer was formed with two deposition steps. Before the deposition of the poly-Ge ground plane layer, a 3500- layer of LTO was deposited to serve as an etch stop. While a clear end-point signal can be detected at the completion of poly-Ge etching and the beginning of -Si etching, the etch selectivity is poor (2.6:1), and a relatively thin -Si layer was used in order to maintain good electrical isolation of devices. With further optimization of the amorphous Si thickness, the LTO etch stop layer could be removed to eliminate the possibility that the ground plane could be undercut by the HF used -Si SiO to release the structural material. Vias in the SiO multilayer stack were then formed using conventional lithography and plasma etching. The vias go down to an n poly-Si connection strap. In priciple, the vias could go down to the Al instead and the n poly-Si connection strap could be eliminated, reducing interconnect resistance. This was not done because exposed metal was not permitted in the LPCVD furnace.

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Fig. 10. Cross-sectional diagram of the n-type poly-Ge MEMS modularly integrated after completion of CMOS transistors with Al interconnect. Dimensions are not to scale so that all layers can be clearly visible.

Next, the n poly-Ge ground plane material was deposited. The poly-Ge films for the ground plane and structural layers were deposited at 400 C and 300 mT by pyrolysis of GeH and PH . Since Ge does not readily nucleate on SiO , a thin ( 5 ) seeding layer of Si was deposited in situ before the poly-Ge. The deposition conditions for the 3100 thick n poly-Ge ground plane were: a predeposition of 200 sccm Si H for 1 min, and a deposition of 100 sccm GeH , 10 sccm 50% PH /50% SiH for 50 min. The ground plane layer was patterned using conventional lithography and dry etch processes. A sacrificial layer of 2.1 m of LTO was then deposited. A cleaning procedure was needed before the deposition, however poly-Ge is rapidly etched in piranha and RCA SC1 solutions. Therefore, the wafers were cleaned using solvents to remove the organics, followed by an HF dip and rinsing in DI water. No densification anneal was performed. Vias in the LTO were then patterned and etched down to the n-type poly-Ge ground plane. The structural layer of n poly-Ge was deposited, filling the vias and thereby forming anchors from the structural layer to the ground plane. The same deposition conditions were used as for the ground plane layer except that the deposition time was increased to 4 h and 45 min to give a 2.2 m thick film. The structural layer was patterned using conventional lithography and dry etch processes. The wafers were diced, and individual dice were rapid thermal annealed at 550 C for 30 s to lower the resistivity of the poly-Ge. The sacrificial LTO was then etched away using a solution containing hydrofluoric acid. The substrate was rinsed with water and methanol and finally air dried. Stiction was not observed, so no special techniques such as critical point drying were required. Stiction forces may be lower than with poly-Si structures either because the poly-Ge is rougher or because the oxides that form on poly-Ge have different surface chemistry than SiO . This process allows the MEMS structures to be fabricated directly on substrates with conventional electronics to reduce parasitic resistance and capacitance associated with chip-to-chip interconnects. While the MEMS were not fabricated directly over the electronics in this process, it would have been possible to do so, thereby significantly reducing cost by saving space on the die, and further reducing interconnect parasitics. Fig. 11 shows an SEM micrograph of the released poly-Ge resonator and the integrated amplifier.

Fig. 11. SEM micrograph of the completed poly-Ge resonator and standard CMOS amplifier with Al metallization. The resonator and amplifier were designed by Clark Nguyen [26].

Transistors on the chips were tested before and after MEMS fabrication to determine how the processing affected the electronics. The drive current versus gate voltage for transistors m m were measured after the metal with was patterned and sintered, and then again after all the MEMS processing steps (see Fig. 12). The drive current versus drain voltage with different fixed gate voltages after MEMS processing are also displayed in Fig. 12. The transistors were fully functional after the MEMS processing, however the drive current versus gate voltage curves changed. The current increased when the gate voltage was above the threshold voltage, and the leakage current deceased somewhat for subthreshold gate voltages. These changes are typical following sintering, and therefore the 400 C depositions and the 550 C, 30 s RTA acted as sintering steps, improving the transistor performance. Even though the MEMS processing improved the performance of the transistors, ideally there should be no change in their characteristics. If such changes occur, the electronic circuits may not function as designed, or the design has to be altered to accommodate the MEMS processing. Perhaps a


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Fig. 12. Transistor characteristics with W=L = 50 m=3 m before and after MEMS processing (400 C poly-Ge depositions, a 550 C, 30-s RTA, and an HF release etch).

longer or higher temperature sinter after metallization would have lowered the contact resistance more so that less of a shift would have been seen after MEMS processing. Since Al with plugs, 2% Si was used with no barrier metals, silicides, or these results do not necessarily indicate how modern transistors might be affected by the MEMS processing [34]. One experiment was done to determine the effects of MEMS processing on modern CMOS devices. The MEMS step that was the most threatening to the transistor performance was the 550 C, 30 s anneal. Therefore, the modern transistors with 0.5 m gate length and Al/0.5%Cu core metal with Ti/W barriers were annealed at 550 C for 30 s. Virtually no change in drain current versus gate voltage was observed, indicating that the barrier metal successfully prevented metal diffusion. The integrated poly-Ge resonator and the trans-impedance amplifier were tested as shown in Fig. 13. The resonators were excited with an ac signal and a dc voltage on the drive electrode. The resulting ac current from the sense comb was fed into the on-chip trans-impedance amplifier. The output of the amplifier was an ac voltage whose amplitude and phase were measured with the network analyzer. The frequency response of the integrated poly-Ge resonator and the CMOS amplifier is displayed in Fig. 14. The devices were tested in air and the resonator had a of 45 and a resonant frequency of 14.05 kHz. The peak in amplitude and 180 phase shift that were detected at resonance indicate that both the resonator and amplifier were functional. If the amplifier had been damaged by the MEMS processing, the peak in amplitude and the phase shift would have been lost in the noise. B. Structural P-Type Poly-Si

Ge

and Sacrificial Poly-Ge

In the second integration approach, a p-type film was used for the structural layer and poly-Si Ge poly-Ge was used as the sacrificial layer. CMOS amplifiers, buffers, and test transistors were fabricated with a baseline,

Fig. 13. Schematic diagram showing the voltages applied to drive the poly-Ge resonator in air. The ac current signal from the sense comb went into the trans-impedance amplifier, and then the signal went off chip to the network analyzer.

Fig. 14. Frequency response of the integrated poly-Ge resonator and the CMOS amplifier.

3 m gate length CMOS process on four-inch diameter Si folded-flexure resonators wafers. P-type poly-Si Ge

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Fig. 15. Cross-sectional diagram of the p-type poly-Si Ge MEMS modularly integrated after completion of CMOS transistors with Al interconnect. Dimensions are not to scale so that all layers can be clearly visible.

were fabricated directly over the amplifiers to demonstrate the area savings afforded by this integration approach. The gate material for both the NMOS and PMOS transistors was n-type poly-Si. The p-type poly-Si strap used to connect the MEMS and the electronic circuits was deposited undoped and was implanted along with the p-type source/drain regions of the transistors (Fig. 15). The metal interconnects were Al with 2% Si. No barrier metal layers were used. The circuits were completed with a 20 min sinter at 400 C and were passivated with 1 m of low temperature oxide (LTO) deposited at 400 C. Since H O would be used as the release etchant, no special layers were needed to protect the SiO and the Al-Si(2%) from the release etchant. Vias through the LTO layers covering the p-type poly-Si connection strap were formed using conventional lithography and dry etch steps. In principle, the vias could go down to the Al instead and the p poly-Si connection strap could be eliminated, reducing interconnect resistance, but this was not done because exposed metal was not permitted in the LPCVD furnace. After the circuits were fabricated and the vias were opened, was deposited. The poly-Si Ge p poly-Si Ge films for the ground plane and structural layers were deposited at 450 C and 600 mT by pyrolysis of SiH , GeH and B H . does not readily nucleate on SiO , a thin Since Si Ge thick) seeding layer of Si was deposited in situ before ( deposition. The deposition conditions the poly-Si Ge thick p poly-Si Ge ground plane for the 4100 were: predeposition using 200 sccm Si H for 2 min at 300 mtorr and 425 C, and deposition using 85 sccm SiH , 90 sccm GeH , 50 sccm 10% B H /90% SiH , for 30 min at 600 mT and 450 C. The ground plane layer was patterned using conventional lithography and dry etch processes. Since standard wafer cleaning procedures are not possible whenever or poly-Ge were exposed, PRS3000 resist poly-Si Ge stripper, O plasma, HF and water were used to clean the wafers before furnace depositions. Before the deposition of the sacrificial poly-Ge, a 500- -thick layer of LTO was deposited to act as an etch stop for the anchor etch. A 2- m-thicklayer ofundoped poly-Ge was deposited using these conditions: predeposition using 200 sccm Si H for 5 min at 300 mtorr and 375 C, and deposition using 220 sccm GeH for 2 h and 45 min at 300 mT and 375 C. Vias in the poly-Ge were then patterned and etched down to the thin LTO etch stop above

Fig. 16. P poly-Si Ge resonator fabricated on top of a CMOS amplifier with Al-Si(2%) interconnect. Wires are bonded to the exposed Al-Si(2%) bond pads. Based on a design by Clark Nguyen, 1992 [26].

the p poly-Si Ge ground plane, and the oxide in the vias was removed with an HF dip. These vias allow the structural layer to be anchored and connected to the ground plane. If the etch time is well established, the LTO etch stop layer is not necessary, assuming tight control of the poly-Ge film thickness and the plasma etch rate. layer was then deposited, The structural p poly-Si Ge using the same deposition conditions as for the ground plane layer, except that the deposition time was increased to 3 h to give a 2.5- m-thick film. The structural layer was patterned using conventional lithography and dry etch processes. The etch was stopped at the poly-Ge using optical endpoint detection. Vias were then etched through the poly-Ge and LTO down to Al-Si(2%) contact pads. The vias were patterned with conventional lithography and the poly-Ge was etched with a standard dry etch. The LTO was etched with a wet pad etch consisting of: 4 parts of NH F (40% concentration), 1 part of HF (49% concentration), and 2 parts of glycerine. Pad etches are designed to etch SiO with high selectivity to the metal interconnects. The wafers were diced, and the structures were released in one hour using H O (30% concentration) at 80 C. A 30 s dip in pad etch removed the LTO etch stop layer covering the ground so that it could be probed. The chips plane p poly-Si Ge were rinsed in water, methanol, and dried. A critical point dry


Fig. 17.

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Transistor characteristics with W=L = 50 m=3 m before and after MEMS processing (450 C poly-Si

was found not to be necessary. Fig. 16 shows an SEM micrograph of a released poly-SiGe resonator on top of an integrated amplifier. Again, the electronics were tested before and after MEMS processing to ensure that the transistor characteristics were unchanged. Along with the amplifier circuits, there were single transistors on the chip to test how the MEMS processing affected the transistor performance. The drive current versus gate m m was meavoltage for transistors with sured after the metal was patterned and sintered, and then again after all the MEMS processing steps (see Fig. 17). The drive current versus drain voltage with different fixed gate voltages after MEMS processing are also displayed in Fig. 17. The transistors were fully functional after the MEMS processing, and virtually no change was seen in the drive current versus gate voltage curves. This indicates that the thermal budget for the MEMS processing was sufficiently low and did not affect the transistor performance. The integrated poly-SiGe resonator and the trans-impedance amplifier were also tested. The resonators were excited with an ac signal and a dc voltage on the drive electrode. The resultant ac current from the sense comb was fed into the trans-impedance amplifier. The output of the amplifier was an ac voltage and the amplitude and phase were measured with the network analyzer. The frequency response of the integrated poly-Ge resonator and the CMOS amplifier is displayed in Fig. 18. The devices were tested in air and the resonator had a of 70 and a resonant frequency of 20.815 kHz. The peak in amplitude and 180 degrees phase shift that were detected at resonance indicate that both the resonator and amplifier were functional. If the amplifier had been damaged by the MEMS processing, the peak in amplitude and the phase shift would have been lost in the noise. The integrated resonator and amplifier were also tested in a vacuum of 40 torr. A of approximately 14 000 was measured at a resonant frequency of 17.96 kHz. The resonant frequency shifted because the resonator that was tested in vacuum was from a wafer

Ge

depositions).

Fig. 18. Frequency response of the integrated poly-SiGe resonator and the CMOS amplifier tested in air.

that had a thicker structural film than that of the resonator tested in air. IV. DISCUSSION The integration of poly-Si Ge MEMS in a modular fashion on top of standard CMOS circuitry with aluminum metallization has been successfully demonstrated. The MEMS were fabricated Ge , which was shown to be a high-quality meusing poly-Si chanical material, on par with poly-Si. The low thermal budget of Ge MEMS processes did not adversely affect the the poly-Si electronics. In the second integration approach, a poly-Ge sacrificial layer was used, which was removed using hydrogen peroxide, requiring no special passivation of the electronics and allowing access to metal bond pads. Modern electronic circuits have 5–8 levels of metal interconnect. Connecting the MEMS ground plane to a poly-Si layer beneath all metal layers would require large and deep vias. These vias would consume a large amount of die area, but more importantly would add significant parasitic capacitance to the connection between the circuits and the MEMS. This would degrade the microsystem performance, and therefore

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connecting the MEMS groundplane to the top metal level is highly desirable. Research is needed to determine how Ge nucleates and grows on exposed metal and poly-Si whether a low resistance, Ohmic contact could be made. One advantage of using more modern electronic circuits, however, is that junction spiking would be less of a concern considering plugs are used to contact active regions. that silicides and Ge MEMS processing temperatures used At the poly-Si in this work, dopant diffusion affecting transistor performance would not be a significant issue. Ge films have yet to be optimized for MEMS apPoly-Si plications. Deposition conditions and annealing conditions can be varied to reduce stress, stress gradient, and increase the fracture strain and quality factor. Understanding the relationship between the film processing, the microstructure, and the resultant mechanical properties is key to being able to optimize the film properties. Major challenges remain for the successful application of integrated MEMS-electronics technologies. The “back-end” processes of dicing, assembly, and encapsulation of MEMS are not standard, since the wafer contains released microstructures. Testing and calibration of MEMS present further challenges. Although solutions to these issues have been found for specific applications, more general solutions remain to be developed. These issues will need to be addressed before MEMS can reach Ge MEMS their full potential. The integration of poly-Si with electronics is an important step toward the realization of inexpensive, fully integrated microsystems.

ACKNOWLEDGMENT The authors would like to thank P. Tobin, S. Samavedam, and S. Bagchi of Motorola, Austin, TX, for the TEM analysis.

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Andrea E. Franke was born in Milwaukee, WI, in 1974. She received the B.S. degree in electrical engineering and the B.S. degree in materials science and engineering from Carnegie Mellon University, Pittsburgh, PA, in 1995. She received the M.S. degree in electrical engineering from the Massachusetts Institute of Technology (MIT), Cambridge. She received the Ph.D. degree in electrical engineering from the University of California at Berkeley in 2000. At MIT, her research involved the anisotropic etching of 200 nm period arrays of inverted pyramids for X-ray diffraction grating applications. At Berkeley, her research focused on polycrystalline silicon-germanium films for integrated microsystems. Currently, she is a diffusion process engineer at the Advanced Products Research and Development Laboratory at Motorola. Her work involves developing polycrystalline silicon and silicon-germanium processes as well as epitaxial silicon and silicon-germanium processes. These processes are applied to gate stacks implementing high dielectric constant metal oxides, raised source/drains for silicon on insulator applications, and strained Si devices. John Heck received the B.A. degree in physics from Johns Hopkins University, Baltimore, MD, in 1994 and the M.S. and Ph.D. degrees in applied science and technology from the University of California at Berkeley in 1997 and 2001, respectively. For his dissertation research at Berkeley, he developed a high-aspect ratio micromachining technique using poly-SiGe for MEMS packaging. For his Master’s degree research, he studied X-ray optics for high-resolution imaging of aqueous biological samples. Currently, he is a member of the Microsystems Technology group at Intel Corporation, Santa Clara, CA. His research involves developing new MEMS processes for radio frequency communications products, and novel methods for packaging MEMS. Tsu-Jae King (SM’00) was born in Ithaca, NY, in 1963. She received the B.S., M.S., and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1984, 1986, and 1994, respectively. At Stanford University, her research involved the seminal study of polycrystalline silicon-germanium films and their applications in metal-oxide-semiconductor technologies, for which she received the Ross M. Tucker AIME Electronics Materials Award. She joined the Xerox Palo Alto Research Center as a Member of Research Staff in 1992, to research and develop polycrystalline-silicon thin-film transistor technologies for high-performance flat-panel display and imaging applications. During her tenure with Xerox PARC, she served as a Consulting Assistant Professor of Electrical Engineering at Stanford University. In August 1996, she joined the faculty of the University of California at Berkeley, where she is now an Associate Professor of Electrical Engineering and Computer Sciences, with a Guest Faculty appointment at the Lawrence Berkeley National Laboratory, and the Director of the UC Berkeley Microfabrication Laboratory. Her research activities are presently in sub-100 nm Si devices and technology, and thin-film materials and devices for integrated microsystems and large-area electronics. Dr. King is a Member of the Electrochemical Society (ECS), the Society for Information Display (SID), and the Materials Research Society (MRS). She has served on committees for many technical conferences including the Device Research Conference, the International Conference on Solid State Devices and Materials, and the International Electron Devices Meeting, and is presently a member of the IEEE EDS VLSI Technology and Circuits Technical Committee. Since 1999, she has served as an Editor for the IEEE ELECTRON DEVICE LETTERS. Roger T. Howe (S’79–M’84–SM’93–F’96) was born in Sacramento, CA, on April 2, 1957. He received the B.S. degree in physics from Harvey Mudd College, Claremont, CA, in 1979 and the M.S. and Ph.D. degrees in electrical engineering from the University of California at Berkeley in 1981 and 1984, respectively. He was a member of the Faculty of Carnegie Mellon University, Pittsburgh, PA, during the 1984–1985 academic year and was an Assistant Professor at the Massachusetts Institute of Technology (MIT), Cambridge, from 1985 to 1987. In 1987, he joined the University of California at Berkeley, where he is now a Professor in the Departments of Electrical Engineering and Computer Science and Mechanical Engineering, as well as a Director of the Berkeley Sensor & Actuator Center. His research interests include silicon microsensors and microactuators, as well as micromachining and microassembly processes.