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High-Speed Capacitorless 1T-DRAM. Jin-Woo Han, Seong-Wan Ryu, Dong-Hyun Kim, and Yang-Kyu Choi. Abstract—Unified random access memory (URAM) ...
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 3, MARCH 2010

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Polysilicon Channel TFT With Separated Double-Gate for Unified RAM (URAM)—Unified Function for Nonvolatile SONOS Flash and High-Speed Capacitorless 1T-DRAM Jin-Woo Han, Seong-Wan Ryu, Dong-Hyun Kim, and Yang-Kyu Choi

Abstract—Unified random access memory (URAM) with a separated double-gate is demonstrated on a fully depleted polysilicon (poly-Si) thin-film-transistor (TFT) template. Integration of a front-gate dielectric of tunneling oxide/nitride/control oxide (O/N/O) and a floating poly-Si channel provides the two versatile functions of nonvolatile silicon oxide–nitride oxide–semiconductor Flash memory and high-speed capacitorless single-transistor 1T-DRAM in a single transistor. In this design, the memory mode of URAM is selected according to user specifications. As the back-channel is assigned for capacitorless 1T-DRAM while the front-channel is devoted for Flash memory, spatial separation minimizes undesired soft programming in the front O/N/O layer and allows for capacitorless 1T-DRAM operation irrespective of the data state of the nonvolatile memory. This feature presents interference-free operation between the two modes. In addition, the virtue of the TFT process allows the potential for stackable memory for ultra-high-density era. Index Terms—Capacitorless 1T-DRAM, Flash memory, nonvolatile memory (NVM), separated double-gate, silicon oxide–nitride oxide–semiconductor (SONOS), thin-film transistor (TFT), unified random access memory (URAM).

I. I NTRODUCTION

A

S A FORM of multifunctional memory at the device level, tied double-gate finFET unified random access memory (URAM) has been demonstrated on various test vehicles that include silicon-on-insulator [1], buried Si:C [2], buried n-well [2], and buried Si:Ge [3] substrates. A combination of a nitride trap layer and a floating-body capacitor enables URAM to perform a nonvolatile memory (NVM) and high-speed capacitorless 1T-DRAM operation in a single transistor. In earlier double-gate finFET URAMs [1]–[3], there were two major problems. First, the data states of the NVM are partially disturbed by the operation of the capacitorless 1T-DRAM when

Manuscript received September 23, 2009. First published February 2, 2010; current version published February 24, 2010. This work was supported in part by the National Research Program for the 0.1-Tb Nonvolatile Memory Development, which is sponsored by the Ministry of Knowledge Economy, and in part by the National Research Foundation Grant K20901000002-09E010000210 funded by the Korea government. The review of this paper was arranged by Editor G.-T. Jeong. J.-W. Han, D.-H. Kim, and Y.-K. Choi are with the Division of Electrical Engineering, School of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, Daejeon 305-701, Korea (e-mail: [email protected]; [email protected]). S.-W. Ryu is with the Hynix Semiconductor, Ichon 467-701, Korea. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2009.2038584

Fig. 1. Schematic of the device structure and operational modes in the separated double-gate URAM. The front- and back-channel are assigned for SONOS Flash memory and capacitorless 1T-DRAM, respectively. This spatial separation minimizes the soft programming in the front O/N/O and allows the capacitorless 1T-DRAM function regardless of the NVM data state.

two modes utilize the same channel due to the shared use of one tied-gate. Therefore, programming by impact ionization for capacitorless 1T-DRAM can unavoidably affect the state of the trapped charges. Second, the NVM data in all memory cells in the memory block should be initialized so as to have a uniform threshold voltage (VT ) before the URAM mode is enabled for capacitorless 1T-DRAM. Thus, the initialization step inevitably destroys the NVM data. These problems can both be eliminated if the NVM and the capacitorless 1T-DRAM mode use their own channel. A schematic of the separated doublegate structure and the operational modes are shown in Fig. 1. The front- and back-gate are independently controlled, and the front- and back-channel are assigned for NVM and capacitorless 1T-DRAM, respectively. Thereby, the impact of VT in the front-channel, i.e., NVM data, on the back-channel potential is decoupled. The spatial separation for these two functions can mitigate undesirable soft programming as well as enable capacitorless 1T-DRAM to function regardless of the data state of the NVM. In this paper, separated double-gate URAM is realized using thin-film-transistor (TFT) technology. Although TFT technology is adopted due to its simple process for a thin backgate dielectric, the separated double-gate device can be expanded to silicon-on-thin-buried-oxide technology for superior performance that originated from the single-crystal nature of the active channel material [4].

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Fig. 2. Operational sequence of URAM. (a) Tied double-gate URAM [1]–[4]. (b) Separated double-gate URAM. In the tied double-gate URAM, an initialization step is required to set the VT state of the capacitorless 1T-DRAM and a verification and reinitialization loop is necessary due to the soft programming issue. In contrast, the separated double-gate URAM eliminates the need for this initialization step and verification loop because the interference between two modes is eliminated.

To satisfy the demand for higher memory density, the size of the memory device should be miniaturized. As device dimensions scale down toward the sub-10-nm regime, however, physical challenges and process difficulties pose a limit of scaling. Three-dimensional stacking technologies, instead of downscaling, have been recognized as an alternative approach to continue the push for higher memory density [5]–[7]. Stackable memory has been realized by wafer stacking technology [5], single-crystal stacking technology [6], and TFT technology [7]. Among these three approaches, polysilicon (poly-Si) TFT has attracted much attention due to its simple and cost-effective process. Therefore, URAM expanded to a TFT template can be a prototype for future stackable memory applications. In this paper, the electrical characteristics of this design are explored. After a fundamental dc analysis, the transient characteristics and reliability of NVM are investigated, and the capacitorless 1T-DRAM characteristics are discussed. Finally, the interference between two modes is examined. II. O PERATION P RINCIPLE Fig. 2 shows the operational sequence used in the tied double-gate finFET [1]–[3] and in the separated double-gate device. In the tied double-gate device, if the NVM mode is chosen, silicon-oxide–nitride-oxide–semiconductor (SONOS) Flash operation is activated. However, if the high-speed (1TDRAM) mode is selected, the NVM data (namely, VT ) in all memory cells in the block should be initialized before the mode is changed. Unless VT is initialized and remains at low VT , a higher gate voltage is required to bias the fixed gate overdrive voltage (VG –VT ). This high gate voltage gradually increases VT as a result of undesired charge trapping [8]. In contrast, if VT is very low, approaching zero, impact ionization can occur, even at a transistor in an OFF state, because the carrier supplement is sufficient to trigger impact ionization. Thus, drain disturbance takes place among adjacent cells. Therefore, presetting of the initial VT is crucial and requires optimization. It is important

Fig. 3. TEM image of the TFT-based URAM. A heavily doped back-gate and a back-gate dielectric of 6 nm are used. The thickness of the undoped poly-Si channel is 20 nm, and the thickness of the front O/N/O layer is 5/8/7 nm. The gate and spacer lengths are 90 and 40 nm, respectively.

to note that impact ionization during programming of capacitorless 1T-DRAM adversely affects the trapped charges in the tunneling oxide/nitride/control oxide (O/N/O) layer, causing the undesired charge trapping gradually to distort a set value of VT . While a faster writing speed of capacitorless 1T-DRAM requires strong impact ionization conditions, the programming bias should be restricted so as not to disturb the trapped charge in the O/N/O layer. In addition, to verify whether the cells have been subject to soft programming, VT should be periodically monitored. The memory block should be reinitialized if a cell fails the verification test. This verification and reinitialization loop is a time-consuming process and hinders the operational speed. In an effort to eliminate this laborious problem, separated double-gate URAM is employed for the two independent memory operations. Fig. 2(b) shows the operational sequence for the separated double-gate URAM. The front-channel is allocated for NVM while the back-channel is assigned for the capacitorless 1T-DRAM. As a result of the spatial separation, the impact ionization process for the capacitorless 1T-DRAM occurs at the back-channel so that the soft programming in the front O/N/O can be suppressed. Therefore, the absence of

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HAN et al.: POLYSILICON CHANNEL TFT WITH SEPARATED DOUBLE-GATE FOR UNIFIED RAM

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Fig. 4. (a) Transfer and (b) output characteristics. The front-channel shows a higher threshold voltage (VT ), a lower ON-current (ION ), a higher SS, and a higher DIBL compared to the back-channel because the front-channel utilizes the thick O/N/O dielectric. On the other hand, the back-channel shows a higher GIDL current compared to that of the front-channel due to the thinner back-gate dielectric and larger back-gate to drain overlap area. The kink point in the output characteristics assures the generation of holes and their accumulation.

a verification and reinitialization cycle improves the operation speed and reduces the power consumption. In addition, as the independently assigned channel for NVM and capacitorless 1TDRAM decouples the impact of the VT in the front-channel on the back-channel potential, the capacitorless 1T-DRAM can work while the NVM data states remain unchanged. III. D EVICE FABRICATION A (100) bulk Si wafer is used as a starting material. After the back-gate doping process is carried out by As+ ion implantation at a dose of 1 × 1015 /cm2 , a SiO2 layer of 6 nm is thermally grown for the back-gate dielectric. Amorphous silicon of 20 nm is then deposited and annealed at 600 ◦ C for 24 h with N2 ambient. Although a channel thickness of 20 nm is appropriate to suppress short-channel effects, it lacks sufficient space to retain excess hole charges. However, the fully depleted thin body biased with a negative voltage at the supplementary gate forms a deep potential well, which accommodates excess hole charges. An active layer with a width of 500 nm is then patterned. As a front-gate dielectric stack, tunneling oxide/nitride/control oxide (O/N/O) of 5/8/7 nm is formed, and an n+ in situ poly-Si gate is then deposited. A photoresist (PR) with a line width of 150 nm is defined using a KrF scanner, and the width of the PR is reduced to 90 nm using a partial ashing process [9]. After the gate with a length of 90 nm is patterned, a SiO2 spacer of 40 nm is formed. Finally, source/drain implantation and activation are carried out. It should be clear that the source/drain and the gate are nonoverlapped. The nonoverlapped region near the source/drain junction becomes partially depleted, which allows the excess hole accumulation even in the thin-body structure. Therefore, the introduction of nonoverlap structure results in the kink effect for the capacitorless 1T-DRAM. Fig. 3 shows transmission electron microscopy (TEM) images of the fabricated device. IV. R ESULTS AND D ISCUSSION A. DC Characteristics Fig. 4(a) shows the front- or back-gate voltage (VFG or VBG ) versus the drain current (ID ) characteristics. The front-

channel shows a higher VT , a lower ON current (ION ), a higher subthreshold slope (SS), and a higher drain-induced barrier lowering (DIBL) value compared to the back-channel because the front-channel employs a thick O/N/O dielectric. On the other hand, the back-channel shows a higher gate-induced drain leakage (GIDL) current compared to the front-channel due to the thin back-gate dielectric and the large back-gate to drain overlap area. The channel mobility extracted by the transconductance method is 39 cm2 /V · s. Fig. 4(b) shows the drain voltage (VD ) versus the drain current (ID ) characteristics. The floating-body effect, which is essentially a kink effect, can be examined from the output characteristics. As the drain voltage increases, the impact ionization process generates excess holes. If the excess holes are stored in the floating body, the positive body charges lower the value of VT , resulting in an increased amount of drain current. The kink point in the ID –VD plot assures the generation of holes and their accumulation. B. Nonvolatile Flash Characteristics As capacitorless 1T-DRAM requires a drain terminal in all memory cells, the array of URAM is a NOR-type architecture. The NVM mode accordingly utilizes the hot-carrier injection (HCI) mechanism for program/erase (P/E) operations. The P/E transient characteristics are shown in Fig. 5. While the front-gate serves as a main gate and is properly biased, the back-gate serves as a support gate and is grounded. The P/E conditions are given as follows. In a programming operation, while the VD,PGM varies from 3.5 to 5 V in 0.5-V steps, VFG,PGM is fixed at 10 V for hot-electron injections. In an erasing operation, while the VD,ERS varies from 4 to 5.5 V in 0.5-V steps, VFG,PGM is fixed at −11 V for hot-hole injections. The P/E conditions at VD,PGM = 4.5 V/VFG,PGM = 10 V with τPGM = 10 μs for programming and VD,PGM = 5.5 V/VFG,PGM = −11 V with τPGM = 300 μs for erasing exhibit a distinctive VT window of 4 V. The data retention and endurance characteristics are shown in Fig. 6. At room temperature, both the retention and endurance characteristics show a negligible amount of data loss. At 125 ◦ C, although there is a little charge loss, the extrapolated retention time is longer than 10 years with a VT window of 2.1 V.

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Fig. 5. Transient characteristics for the NVM mode. (a) Programming. (b) Erasing. The HCI mechanism is utilized for P/E operations. The P/E conditions at VD,PGM = 4.5 V/VFG,PGM = 10 V with τPGM = 10 μs for programming and VD,PGM = 5.5 V/VFG,PGM = −11 V with τPGM = 300 μs for erasing exhibit a threshold voltage window of 4 V.

Fig. 6. Reliability characteristics of the NVM mode. (a) Endurance. (b) Retention. At room temperature, both the retention and endurance characteristics show a negligible amount of data loss. At 125 ◦ C, although the charge loss phenomenon appears to occur, the extrapolated retention time with a VT window of 2.1 V is longer than 10 years.

is less than 0.2 V. There is a tradeoff relationship between the VT window of NVM and the interference of the backchannel. The VT window for the NVM should be restricted so as to suppress the interference. Although the VT window criterion for the NVM is held below 1.2 V, refinement of the device geometry can further relieve the VT window criterion. In an independently controlled separated double-gate, when the front-channel is depleted, the front-gate effect on VBT becomes [10] dVBT 3tox,b Cox,f CSi = = dVFG Cox,b (CSi + Cox,f ) 3tox,f + tsi Fig. 7. Impact of the trapped charge at the front O/N/O on the back-channel VT . A VFT window of 1.2 V provides a VBT shift of 0.2 V.

C. Capacitorless 1T-DRAM Characteristics Fig. 7 shows the impact of the front-channel VT (VFT ), i.e., the trapped charge, on the back-channel VT (VBT ). VFT linearly affects VBT . The slope of VFT versus VBT implies how the back-channel potential is influenced by the front-channel potential. The steeper slope indicates that the VT change in the NVM strongly affects the back-channel potential, whereas the proposed structure exhibits a small slope of 0.17 V/V. If the VT window criterion for NVM is set to 1.2 V, VBT distortion

where Cox,f and Cox,b represent the front- and back-gate capacitance, respectively, tox,f and tox,b are the front- and back-gate dielectric thickness, respectively; CSi is the channel capacitance; and tsi is the channel thickness. In order to decouple the interference between the two channels, a higher Cox,b and a lower CSi are required. In other words, a thinner backgate dielectric and greater thickness of the body can widen the VT window criterion to suppress the interference fully. As a thicker body can aggravate the short-channel characteristics, a decreased back-gate dielectric thickness is highly preferred. Given the insignificant influence of VFT , i.e., the data states of NVM, on the back-channel potential, capacitorless 1TDRAM can be used irrespective of the NVM state. Fig. 8

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Fig. 8. (a) Capacitorless 1T-DRAM characteristics for NVM “0” and NVM “1” states. The similar sensing characteristics are achieved regardless of the data states of NVM. (b) Data retention characteristics show that the retention time of NVM “0” shows longer than that of NVM “1” because the charged electron retains the excess holes in the body.

shows the P/E characteristics of the capacitorless 1T-DRAM operation. Impact ionization (VBG = 1 V and VD = 3.5 V) is used to generate excess holes, and the forward junction current (VBG = 1 V and VD = −2 V) is utilized to eliminate the excess holes. The P/E pulse width is 50 ns. The read conditions are VBG = 1 V and VD = 0.8 V. While the back-gate serves as the main gate, the front-gate serves as a supportive gate. To secure the hole storage volume in the fully depleted channel, a potential well is formed at the front-channel by applying VFG = −1 V. In both NVM states, i.e., “0” and “1”, similar sensing characteristics are achieved. As indicated in Fig. 8, the sensing current window is approximately 250 nA/μm. As the fraction of the stored data diminishes with the sensing time due to the recombination process, the extrapolated retention time is approximately 0.9 ms. This unsatisfactory performance is attributed to the inherent features of the poly-Si channel, such as its low mobility, low impact ionization efficiency, and low carrier lifetime. Although the measured current sensing window and resultant retention time appears to be too small for immediate applications, the performance can be improved by several technologies [11], [12]. For a wider sensing window and longer retention time, more holes should be generated and the generated holes should survive. The improved impact ionization efficiency and decreased recombination rate will improve the performance. If the size of a single grain becomes larger than the channel area, the mobility and the impact ionization rate will increase, and the recombination rate will decrease [13]. In other words, the development of a recrystallization process to enhance channel mobility and reduce the defect density can boost the performance of capacitorless 1T-DRAM.

Fig. 9. VFT shift caused by charge trapping in the front O/N/O layer after cyclic capacitorless 1T-DRAM operation. The soft programming was found to be negligible. TABLE I C OMPARISON OF URAM FOR A M ULTIFUNCTIONAL C HIP. I N THE S EPARATED D OUBLE -G ATE URAM, THE M EMORY C APACITY C AN B E D OUBLED VIA S IMULTANEOUS O PERATION OF NVM AND C APACITORLESS 1T-DRAM

D. Disturbance Between NVM and Capacitorless 1T-DRAM Modes As capacitorless 1T-DRAM uses the back-channel, the charge trapping in the front O/N/O layer can be inhibited. To check for soft programming, the front-channel VT is monitored during the cyclic operation of capacitorless 1T-DRAM, as shown in Fig. 9. The VFT was found to be unaffected by the P/E cycles, which assures that the NVM data states are sustained regardless of the capacitorless 1T-DRAM operation. This feature provides great benefits for TFT-based URAM. Table I compares

the features of tied double-gate and the separated double-gate URAM. Assuming that the core region consists of four banks, for the tied double-gate URAM, the mode of each bank should be assigned as only one of the two modes: NVM or capacitorless 1T-DRAM. Therefore, some fraction of the memory chip consists of the capacitorless 1T-DRAM function, and the NVM

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function occupies the remaining area. In contrast, for the separated double-gate URAM, the disturbance-free operation allows capacitorless 1T-DRAM operation with the conservation of the NVM data. Thus, while the NVM data states remain in the background, high-speed operation is possible. Additionally, the aforementioned data verification and reinitialization steps are removed. Hence, the simultaneous function of the capacitorless 1T-DRAM and NVM can double the memory capacity, as all memory banks can be allocated for the capacitorless 1T-DRAM without disturbance to the NVM state. V. C ONCLUSION URAM has been demonstrated on a fully depleted polySi TFT template by utilization of a separated double-gate. Integration of a front-gate dielectric of O/N/O and a floating poly-Si channel provides the two versatile functions of nonvolatile SONOS Flash memory and high-speed capacitorless 1T-DRAM in a single-memory transistor. Using the independently controlled double-gate characteristics, the front- and back-channel are assigned for NVM and capacitorless 1TDRAM, respectively. The spatial separation allows the 1TDRAM operation regardless of the data state of the NVM, which doubles the memory capacity. In addition, as the impact ionization for capacitorless 1T-DRAM occurs at the backchannel, undesired soft charge trapping in the front O/N/O layer is suppressed. This feature can exclude the soft programming phenomenon, which eliminates the need for verification and reinitialization sequences. Moreover, it improves the operational speed and reduces the power consumption. With these advantages of TFT-based URAM, i.e., the separated doublegate characteristics, the advantages of the TFT process can be applied to stackable memory in future for ultra-high-density applications.

[7] H. Yin, W. Xianyu, A. Tikhonovsky, and Y. S. Park, “Scalable 3-D finlike poly-Si TFT and its nonvolatile memory application,” IEEE Trans. Electron Devices, vol. 55, no. 2, pp. 578–584, Feb. 2008. [8] J.-W. Han, S.-W. Ryu, S.-J. Choi, and Y.-K. Choi, “Gate-induced drainleakage (GIDL) programming method for soft-programming-free operation in unified RAM (URAM),” IEEE Electron Device Lett., vol. 30, no. 2, pp. 189–191, Feb. 2009. [9] Y.-K. Choi, T.-J. King, and C. Hu, “A spacer patterning technology for nanoscale CMOS,” IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 436– 441, Mar. 2002. [10] M. Masahara, Y. Liu, K. Sakamoto, K. Endo, T. Matsukawa, K. Ishii, T. Sekigawa, H. Yamauchi, H. Tanoue, S. Kanemaru, H. Koike, and E. Suzuki, “Demonstration, analysis, and device design considerations for independent DG MOSFETs,” IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 2046–2053, Sep. 2005. [11] D. N. Kouvatsos, A. T. Voutsas, and M. K. Hatalis, “High-performance thin-film transistors in large grain size polysilicon deposited by thermal decomposition of disilane,” IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 2046–2053, Sep. 2005. [12] S. Jagar, M. Chan, M. C. Poon, H. Wang, M. Qin, P. K. Ko, and Y. Wang, “Single grain thin-film-transistor (TFT) with SOI CMOS performance formed by metal-induced-lateral-crystallization,” in IEDM Tech. Dig., 1999, pp. 293–296. [13] N. Yamauchi, J.-J. J. Hajjar, and R. Reif, “Poly silicon thin-film transistors with channel length and width comparable to or smaller than the grain size of the thin film,” IEEE Trans. Electron Devices, vol. 38, no. 1, pp. 55–60, Jan. 1991.

Jin-Woo Han received the B.S. degree in 2004 from Inha University, Incheon, Korea, and the M.S. degree in 2006 from the Korea Advanced Institute of Science and Technology, Daejeon, Korea, where he is currently working toward the Ph.D. degree in the Division of Electrical Engineering, School of Electrical Engineering and Computer Science. His research interests include multiple-gate MOSFET, novel device, and nanofabrication technology, and his research covered a broad area in silicon devices ranging from device design to process development, simulation, characterization, and modeling.

R EFERENCES [1] J.-W. Han, S.-W. Ryu, C. Kim, S. Kim, M. Im, S. J. Choi, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.-K. Choi, “A unified-RAM (URAM) cell for multi-functioning capacitorless DRAM and NVM,” in IEDM Tech. Dig., 2007, pp. 929–932. [2] J.-W. Han, S.-W. Ryu, S. Kim, C.-J. Kim, J.-H. Ahn, S.-J. Choi, K. J. Choi, B. J. Cho, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.-K. Choi, “Band offset FinFET-based URAM (Unified-RAM) built on SiC for multi-functioning NVM and capacitorless 1T-DRAM,” in VLSI Symp. Tech. Dig., 2008, pp. 200–201. [3] J.-W. Han, S.-W. Ryu, S. Kim, C.-J. Kim, J.-H. Ahn, S.-J. Choi, K. J. Choi, B. J. Cho, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.-K. Choi, “Energy band engineered unified-RAM (URAM) for multi-functioning 1T-DRAM and NVM,” in IEDM Tech. Dig., 2008, pp. 227–230. [4] R. Tsuchiya, M. Horiuchi, S. Kimura, M. Yamaoka, T. Kawahara, S. Maegawa, T. Ipposhi, Y. Ohji, and H. Matsuoka, “Silicon on thin BOX: A new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control,” in IEDM Tech. Dig., 2004, pp. 631–634. [5] K. W. Lee, T. Nakamura, T. Ono, Y. Yamada, T. Mizukusa, H. Hashimoto, K. T. Park, H. Kurino, and M. Koyanagi, “Three-dimensional shared memory fabricated using wafer stacking technology,” in IEDM Tech. Dig., 2000, pp. 165–168. [6] S.-M. Jung, J. Jang, W. Cho, H. Cho, J. Jeong, Y. Chang, J. Kim, Y. Rah, Y. Son, J. Park, M.-S. Song, K.-H. Kim, J.-S. Lim, and K. Kim, “Three dimensionally stacked NAND Flash memory technology using stacking single crystal Si layers on ILD and TANOS structure for beyond 30 nm node,” in IEDM Tech. Dig., 2006, pp. 37–40.

Seong-Wan Ryu received the B.S. degree in electrical and electronic engineering from Hanyang University, Seoul, Korea, in 2004 and the M.S. and Ph.D. degrees from the Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 2006 and 2009, respectively. He is currently with Hynix Semiconductor Inc., Ichon, Korea. His current research interests include Flash memory, multiple-gate MOSFET, novel device, nanofabrication technology, and CMOS characterization.

Dong-Hyun Kim received the B.S. degree from Kyungpook National University, Daegu, Korea, in 2007. He is currently working toward the M.S. degree in electrical engineering and computer science in the Division of Electrical Engineering, School of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, Daejeon, Korea. He is currently with Samsung Electronics, Ltd., Kyungki-Do, Korea. His research interests include capacitorless 1T-DRAM and NVM on the MOSFETs. His research covers device design to process development, simulation, characterization, and modeling.

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HAN et al.: POLYSILICON CHANNEL TFT WITH SEPARATED DOUBLE-GATE FOR UNIFIED RAM

Yang-Kyu Choi received the B.S. and M.S. degrees from Seoul National University, Seoul, Korea, in 1989 and 1991, respectively and the M.S. and Ph.D. degrees from the University of California, Berkeley, in 1999 and 2001, respectively. He is currently an Associate Professor with the Division of Electrical Engineering, School of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, Daejeon, Korea. From January 1991 to July 1997, he was with Hynix Semiconductor Inc., Ichon, Korea,

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where he developed 4-, 16-, 64-, and 256-M DRAM as a Process Integration Engineer. His research interests include multiple-gate MOSFETs, exploratory devices, novel memory devices, nanofabrication technologies for bioelectronics, as well as nanobiosensors. He has also worked on reliability physics and quantum phenomena for nanoscale CMOS. He is the author or a coauthor of over 80 papers. He is the holder of seven U.S. patents as well as 99 Korean patents. Dr. Choi received the Sakrison Award for the best dissertation from the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, in 2002. His biographic profile was published in the 57th Marquis Who’s Who in America. He was also the recipient of “The Scientist of the Month for July 2006” from the Ministry of Science and Technology in Korea.

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