Power Factor Correction Boost Converter Based on the ... - IEEE Xplore

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 3, MARCH 2012

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Power Factor Correction Boost Converter Based on the Three-State Switching Cell Juan Paulo Robles Balestero, Fernando Lessa Tofoli, Rodolfo Castanho Fernandes, Member, IEEE, Grover Victor Torrico-Bascopé, Member, IEEE, and Falcondes José Mendes de Seixas

Abstract—The need for solid-state ac–dc converters to improve power quality in terms of power factor correction, reduced total harmonic distortion at input ac mains, and precisely regulated dc output has motivated the investigation of several topologies based on classical converters such as buck, boost, and buck–boost converters. Boost converters operating in continuous-conduction mode have become particularly popular because reduced electromagnetic interference levels result from their utilization. Within this context, this paper introduces a bridgeless boost converter based on a three-state switching cell (3SSC), whose distinct advantages are reduced conduction losses with the use of magnetic elements with minimized size, weight, and volume. The approach also employs the principle of interleaved converters, as it can be extended to a generic number of legs per winding of the autotransformers and high power levels. A literature review of boost converters based on the 3SSC is initially presented so that key aspects are identified. The theoretical analysis of the proposed converter is then developed, while a comparison with a conventional boost converter is also performed. An experimental prototype rated at 1 kW is implemented to validate the proposal, as relevant issues regarding the novel converter are discussed. Index Terms—AC–DC converters, boost converter, harmonics, power factor correction (PFC), three-state switching cell (3SSC).

I. I NTRODUCTION

A

C–DC CONVERSION of electric power is widely used in several applications such as adjustable-speed drives, switch-mode power supplies, uninterrupted power supplies (UPSs), and battery energy storage. Conventionally, ac–dc converters, popularly referred to as rectifiers, are implemented using diodes and thyristors to provide uncontrolled and conManuscript received August 6, 2010; revised December 14, 2010, March 10, 2011, and May 16, 2011; accepted June 8, 2011. Date of publication June 20, 2011; date of current version October 25, 2011. This work was supported in part by the Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq), by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES), by the Fundação de Amparo Pesquisa do Estado de Minas Gerais (FAPEMIG), and by the Fundação de Amparo Pesquisa do Estado de São Paulo (FAPESP). J. P. R. Balestero is with the Federal Institute of Education, Science, and Technology of Santa Catarina, Chapecó 89812-160, Brazil (e-mail: [email protected]). F. L. Tofoli is with the Federal University of São João del-Rei, São João del-Rei 36307-352, Brazil (e-mail: [email protected]). R. C. Fernandes is with Jacto S/A, Pompéia 17580-000, Brazil (e-mail: [email protected]). G. V. Torrico-Bascopé is with GTB Power Electronics Research and Technology AB, 164 72 Kista, Sweden (e-mail: [email protected]). F. J. Mendes de Seixas is with the Department of Electrical Engineering, State University of São Paulo (UNESP), Ilha Solteira, Brazil (e-mail: falcon@ dee.feis.unesp.br). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2011.2160136

trolled dc power with unidirectional and bidirectional power flow. Major drawbacks include poor power quality in terms of injected current harmonics, resulting in voltage distortion and poor power factor (PF) at the input ac mains and slow varying rippled dc output at the load end, low efficiency, and large size of ac and dc filters. Reduction of harmonic content with the consequent increase of PF can be obtained by using either passive or active PF correction (PFC) techniques. Passive methods include the use of tuned LC filters, what represents a robust solution. However, increased size, weight, and volume result. Moreover, the passive filter may not respond adequately if the load PF comes to vary. On the other hand, active methods come as a more efficient solution by using controlled solid-state switches in association with passive elements such as resistors, inductors, and capacitors. In fact, the closed-loop operation of a static power converter dedicated to PFC assures satisfactory performance with high input PF and regulated dc output voltage over a wide operating range. Increased complexity and reduced robustness are distinct characteristics of this practice though. In order to meet the requirements in the proposed standards such as IEC 61000-3-2 [1] and IEEE Standard 519 [2] on the quality of the input current that can be drawn by low-power equipment, a PFC circuit is typically added as a front-end stage. The boost PFC circuit operating in continuous-conduction mode (CCM) is, by far, the popular choice for medium- and high-power applications. This is because the continuous nature of the boost converter’s input current results in low conducted electromagnetic interference (EMI) compared to other active PFC topologies such as buck–boost and buck converters. Several issues must be taken into account to determine which type of static power converter is the most recommended for a given application, such as robustness, power density, efficiency, cost, and complexity. Within this context, numerous boost-type topologies have been proposed in the last few years with the aim of improving the characteristics of the traditional converter used for PFC purposes, such as the reverse-recovery problem of the boost diode [3], [4] and the increase of the output voltage [5]. As the power rating increases, it is often required to associate converters in series or in parallel. In high-power applications, interleaving of two boost converters is very often employed to improve the performance and reduce the size of the PFC front end. Moreover, for high-current applications and voltage step-up, the currents through the switches become just fractions of the input current [6]. Interleaving effectively doubles the switching frequency and also partially cancels the input and output ripples, as the size of energy-storage inductors and

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differential-mode EMI filters in interleaved implementation can be reduced [7]. A three-state switching cell (3SSC) can be obtained by the association of two two-state switching cells (2SSCs) interconnected to a center-tapped autotransformer, from which a family of dc–dc converters can be derived. This concept was first introduced in [8], as the so-called cell type B is obtained. The first topology for PFC applications based on the 3SSC was introduced in [9]. It can be obtained by replacing the input source of the dc–dc boost converter presented in [8] by a typical single-phase diode bridge and an ac voltage source. The presence of the diode bridge causes conduction losses to increase because the current always flows through four semiconductor elements. Attempts to achieve high output voltage gain using the 3SSC and the dc–dc boost converter were performed in [10]–[12]. Although only two diodes and two capacitors are added to the original topology, the extension to PFC applications with high efficiency is limited by the presence of increased number of components in the current path during each operating mode. An isolated dc–dc boost converter was proposed in [13]. However, one coupled inductor, one transformer, and a singlephase diode bridge are added to the original converter, resulting in a topology with increased number of components and reduced robustness. A center-tapped PFC topology based on the 3SSC with an output split capacitor and high voltage gain was studied in [14] and [15]. Even though the authors claim that reduced conduction losses are achieved with the converter, the loss mechanism is not presented. However, one can say that the current still flows through four semiconductor elements during any operating mode. Moreover, there is a need for a centertapped low-frequency transformer at the input side, limiting its application to UPSs. Other typical applications of converters using the 3SSC for voltage step-up in fuel cell systems are described in [16] and [17]. An interesting three-level boost rectifier associated with the 3SSC is presented in [17], where voltage doubler characteristic is achieved. Reduced current stress through the semiconductor elements, reduced volume and weight of the magnetic components, and simple control strategy are distinct advantages of this proposal [17]. Even though the single-phase diode bridge is eliminated, four switches are necessary due to the bidirectional power flow. Since the current flows through a reduced number of components in both overlapping mode (OM) and nonoverlapping mode (NOM) if compared with the aforementioned approaches, reduced conduction losses are also expected. A three-phase version of the aforementioned topology was also studied in [19]. Within this context, this paper introduces a topological variation of the boost converter based on the 3SSC for PFC applications. Four switches and two 3SSCs are used, making this converter suitable for high-current and high-power applications. Moreover, the following advantages can be addressed to the use of the three-state cell: Inductors are designed for twice the switching frequency, with consequent reduction of size and weight; the current through the switches is half of the input current; part of the input power is delivered to the load by the

Fig. 1.

Proposed boost rectifier employing the 3SSC.

transformer instead of the main switches, consequently reducing conduction and commutation losses; lower cost switches can be used due to the possibility of parallelism of any number of cells; and the presence of the diode bridge is eliminated. Initially, the converter operation in both OM and NOM is described, where the main characteristics of the topology are discussed. The converter modeling considering the use of average-current-mode control will also be presented. An experimental prototype is then implemented, while the detailed discussion of experimental results is supposed to validate the theoretical assumptions and also demonstrate the merit of the proposal. II. P ROPOSED C ONVERTER First, let us discuss the idea that led to the conception of the proposed topology. As mentioned before, the conventional boost converter is the former choice for PFC applications basically due to its simple structure. However, as the power rating increases, the boost converter efficiency is compromised because conduction losses become appreciable due to the current flowing through three semiconductor elements simultaneously in any operating stage. With the aim of increasing the efficiency of the conventional boost converter, single-phase bridgeless boost rectifiers (also referred to as dual-boost converters) were introduced in [20] and [21], respectively. Conduction losses are then minimized by reducing the number of semiconductor devices that conduct current from the source to the load. At a first glance, one can say that both converters may lead to a solution with increased cost and complexity since two active switches are now employed. However, the drive circuit of the main switches in the symmetrical topology is less complex than that of the asymmetrical one because both switches are connected to the same reference node. However, it must be mentioned that this feature also eliminates the possibility of short circuit through one leg due to eventual malfunctioning of the main switches. Tradeoffs have also to be made between complexity and reduced conduction losses when considering the conventional boost converter or the aforementioned bridgeless topologies. The 2SSC is composed basically by the association of one controlled switch and one diode. Of course, the aforementioned bridgeless topologies employ two 2SSCs. If they are replaced by two 3SSCs instead, the topology shown in Fig. 1 will result, which is the scope of this work. The proposed approach can be seen as the association of the interleaving technique and the use of the 3SSC. The following advantageous characteristics can then be addressed to the introduced topology. 1) It has reduced size, weight, and volume of magnetics, which are designed for twice the switching frequency.

BALESTERO et al.: POWER FACTOR CORRECTION BOOST CONVERTER BASED ON THREE-STATE SWITCHING CELL

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switches S3 and S4 , boost diodes Db3 and Db4 , and antiparallel diodes Ds1 and Ds2 are supposed to replace their respective counterparts, i.e., S1 and S2 , Db1 and Db2 , and Ds3 and Ds4 .

Fig. 2.

Operating modes of the proposed boost converter.

2) The current stress through each main switch is equal to half of the total output current, allowing the use of switches with lower current rating. 3) Losses are distributed among the semiconductors, leading to better heat distribution and, consequently, more efficient use of the heat sinks. 4) Part of the input power, i.e., 50%, is directly transferred to the load through the diodes and the coupled inductors (autotransformers) and not through the main switches. As a consequence, conduction and switching losses are reduced. This is the main difference between the functionality of this approach and that of the interleaved boost topology. 5) The use of the 3SSC allows the parallel connection of switches, and therefore, inexpensive power devices and drives can be used. 6) Energy is transferred from the source to the load during most part of the switching period, which is a distinct characteristic of the proposed converter, since, in other boost-type converters, it only occurs during half of the switching period. As a consequence, reduction of current peaks and also conduction losses is expected. 7) The drive circuit of the main switches becomes less complex because they are connected to the same reference node. Two operating modes regarding the main switches can be obtained for the proposed topology. If the duty cycle D is higher than 0.5, OM occurs, where two switches remain turned on at the same time. Otherwise, if D < 0.5, the converter operates in NOM, while only one switch remains turned on. This situation is defined by the comparison between the rectified line voltage Vi(rect.) and the output voltage Vo as a function of the duty cycle, as shown in Fig. 2, for one period of the input voltage. It must also be mentioned that the input current ripple becomes null when D = 0.5, what represents the transition between OM and NOM. The detailed description of the operating stages considering the positive half cycle of the input voltage in both NOM and OM is given as follows. A. Operation in NOM (D < 0.5) 1) CCM: The converter operation can be defined according to four operating stages as shown in Fig. 3. The respective main theoretical waveforms are shown in Fig. 4. In order to describe the operating stages, the positive half cycle of the line voltage is considered. The behavior of the converter during the negative half cycle is analogous, although

First stage [t0 , t1 ] [Fig. 3(a)]: Initially, switch S1 is turned on, while switch S2 is turned off. The current through the boost inductor is divided into two parts. The first one flows through L2 and Db2 with energy being delivered to the load. The second one flows through L1 and S1 . Current sharing is maintained since the turns ratio for L1 and L2 is the same. The current through Lb increases linearly. Windings L1 and L2 have the same impedance, and the voltages across them are equal to half of the output voltage Vo . The return path of the current to the source occurs through antiparallel diodes Ds3 and Ds4 . This stage finishes when S1 is turned off. Second stage [t1 , t2 ] [Fig. 3(b)]: Switch S1 is turned off while switch S2 remains off. The voltage across inductor Lb is inverted. Diode Db1 is forward biased while Db2 remains conducting. The energy stored in Lb during the previous stage is then transferred to the load. The current flows through L1 L2 , according to the given polarity, what causes the magnetic flow in the core to be null. The current returns to the source analogously to the previous stage. This stage finishes when S2 is turned on. Third stage [t2 , t3 ] [Fig. 3(c)]: Due to symmetry of the circuit, this stage is similar to the first one, although switch S2 is turned on and S1 remains turned off. Diode Db1 keeps conducting, and Db2 is reverse biased. Fourth stage [t3 , t4 ] [Fig. 3(d)]: This stage is similar to the second one, as the same equivalent circuit and operating conditions are valid in this case. 2) DCM: This conduction mode occurs when the current through inductor Lb becomes null during part of the switching period. Additionally, there will be no energy transfer from the input source to the load while this situation persists. The converter operation can be defined according to six operating stages, while the respective main theoretical waveforms are shown in Fig. 5. It must be mentioned that some of the equivalent circuits are too simple or identical to those previously described in Section II-A1 and will not be discussed in detail. First stage [t0 , t1 ] [Fig. 3(a)] and second stage [t1 , t2 ] [Fig. 3(b)]: They are identical to the first and second stages in NOM-CCM, respectively. Third stage [t2 , t3 ]: Boost diodes Db1 and Db2 are reverse biased, while main switches S1 and S2 are turned off. The current through Lb reaches zero, and energy transfer from the source to the load is ceased. This stage finishes when S2 is turned on. Fourth stage [t3 , t4 ] [Fig. 3(c)] and fifth stage [t4 , t5 ] [Fig. 3(d)]: They are identical to the third and fourth stages in NOMCCM, respectively. Sixth stage [t5 , t6 ]: This stage is identical to the third one. 3) CRM: This mode is also called boundary conduction mode because it represents the intermediate operation between CCM and discontinuous-conduction mode (DCM). The analysis of the critical conduction mode (CRM) is based on the study developed for the previous conduction modes and is required so

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Fig. 3. Operating stages of the proposed boost converter in NOM-CCM considering the positive half cycle of the input voltage. (a) First stage. (b) Second stage. (c) Third stage. (d) Fourth stage.

Fig. 4. Main theoretical waveforms for NOM-CCM.

that the static characteristic of the converter operating in NOM is determined. The current and voltage waveforms regarding the boost inductor are shown in Fig. 6. In this case, the minimum current through Lb is null, i.e., the current through Lb is equal to zero for a single time instant. The ripple current through Lb is then equal to the maximum current IM . 4) Output Characteristic of the Converter: The static gain expressions for the converter operating in CCM, DCM, and CRM are given respectively by V0 1 = Vi(rect.) 1−D 2 · D2 + γ = γ + D2 1 4 √ = = 1 − Dcrit 3± 1−8·γ

GCCM_NOM =

(1)

GDCM_NOM

(2)

GCRM_NOM

Fig. 5.

Main theoretical waveforms for NOM-DCM.

Fig. 6.

Main theoretical waveforms for NOM-CRM.

(3)


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Fig. 8. Ripple current through the boost inductor in NOM.

means that the CCM region is wider for the proposed converter. That is, for a given operating point, the boost inductance calculated for the proposed converter becomes one-fourth of that required for the classic boost converter. 5) Filter Elements: The ripple current through the boost inductor (ΔILb ) is given as ΔILb =

(1 − 2 · D) · D · Ts · Vo . 2 · Lb

(5)

Expression (5) can be normalized so that the ripple current is obtained as β= Fig. 7. Comparison between static gain curves. (a) Conventional boost converter. (b) Boost converter based on the 3SSC in NOM.

where γ=

2 · Lb · Io Vi(rect.) · Ts

(4)

Io is the output current (in amperes), Ts is the switching period (in seconds), and Dcrit is the critical duty cycle. The procedure used to obtain such expressions is the same as that employed in [9] and will not be described here in detail. Expression (1) clearly shows that the static gain for the proposed converter in the aforementioned converter is the same as that of the conventional boost converter. From (1)–(3), it is possible to determine the static gain of the proposed converter operating at D < 0.5, as the obtained curves are shown in Fig. 7. Analogous to the conventional boost converter, the output voltage is a function of the load current in DCM, and this operating region must be avoided. It is worth to mention that the maximum static gain in CRM occurs at γ = 0.0625 and D = 0.25 for the proposed converter [Fig. 7(b)]. Considering the classic boost converter, the maximum gain in CRM is verified when γ = 0.25 and D = 0.5 [Fig. 7(a)]. In practical terms, it

2 · Lb · ΔILb = (1 − 2 · D) · D. Ts · Vo

(6)

Expression (6) is plotted in Fig. 8, where one can see that the maximum ripple current occurs at D = 0.25 and β = 0.125. By choosing arbitrarily the ripple current, the boost inductance can be determined as Lb =

(1 − 2 · D) · D · Ts · Vo Ts · Vo =β· . 2 · ΔILb 2 · ΔILb

(7)

Considering the maximum ripple current which represents the worst case, the inductance can be obtained by Lb =

Ts · Vo . 16 · ΔILb

(8)

The critical inductance, whose value assures operation in CCM, is given by Lcrit =

Vi(rect.) · Ts . 32 · Io

(9)

The output capacitor can be determined as C≥

1 Io · (1 − 2 · D) · D · 2 ΔVo · fs · (1 − D)

(10)

whereΔVo is the output voltage ripple (in volts) and fs is the switching frequency (in hertz).

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Fig. 9. Operating stages of the proposed boost converter in OM-CCM considering the positive half cycle of the input voltage. (a) First stage. (b) Second stage. (c) Third stage. (d) Fourth stage.

Fig. 10. Main theoretical waveforms for OM-CCM.

B. Operation in OM (D > 0.5) The converter operation can be defined according to four operating stages as shown in Fig. 9, while the respective main theoretical waveforms are shown in Fig. 10. In order to describe the operating stages, the positive half cycle of the line voltage is considered. The behavior of the converter during the negative half cycle is analogous, although switches S3 and S4 , boost diodes Db3 and Db4 , and antiparallel diodes Ds1 and Ds2 are supposed to replace their respective counterparts, i.e., S1 and S2 , Db1 and Db2 , and Ds3 and Ds4 . 1) CCM: First stage [t0 , t1 ] [Fig. 9(a)]: Initially, during the positive half cycle of the line voltage, switch S1 is turned on, while switch S2 also remains turned on. Boost diodes Db1 and Db2 are reverse biased. One part of the boost inductor current flows through L1 and S1 , and the remaining one flows through L2 and S2 . Considering Kirchhoff’s law

and the returning path, current flows through L3 −Ds3 and L4 −Ds4 . By adopting the same turns ratio for L1 and L2 , current sharing is maintained. The opposite polarity between the windings causes the voltage across the windings to be null, what represents a short circuit. Similar to the first autotransformer, the voltage across L3 and L4 is also null. Moreover, boost inductor Lb stores energy, and the current through it increases linearly. During this stage, only the output capacitor Co provides power to the load, and it finishes when S2 is turned off. Second stage [t1 , t2 ] [Fig. 9(b)]: Switch S2 is turned off, and S1 remains turned on. The voltage across the boost inductor is inverted. Diode Db2 is forward biased while Db1 is reverse biased. The boost inductor current is divided into two parts. Energy transfer then occurs from L1 −S1 and L2 −Db2 to the load. Moreover, the current decreases linearly, transferring the energy previously stored in inductor Lb and also energy from the source to the load. Since L1 and L2 have the same turns ratio, current sharing is maintained. Analogous to the first stage, the current returns to the source. This stage finishes when switch S2 is turned on. Third stage [t2 , t3 ] [Fig. 9(c)]: This stage is similar to the first one, although switch S2 will be turned on while switch S1 remains also turned on. Boost diodes Db1 and Db2 are also reverse biased. Similar to the first stage, only the output capacitor provides energy to the load. Fourth stage [t3 , t4 ] [Fig. 9(d)]: This stage is similar to the second one, although switch S1 is turned off while switch S2 remains turned on. Diode Db1 is forward biased, whereas Db2 is reverse biased. In this way, energy is transferred from the input source and the boost inductor to the load. 2) DCM: This conduction mode occurs when the current through inductor Lb becomes null during half of the switching period. The converter operation can be defined according to six operating stages as shown in Fig. 11, while the respective main theoretical waveforms are shown in Fig. 11. It must be mentioned that some of the equivalent circuits are identical to those previously described in Section II-A1 and will not be discussed in detail once again.


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Fig. 11. Main theoretical waveforms for OM-DCM.

Fig. 12. Main theoretical waveforms for OM-CRM.

First stage [t0 , t1 ] [Fig. 9(a)] and second stage [t1 , t2 ] [Fig. 9(b)]: They are identical to the first and second stages in OM-CCM, respectively. Third stage [t2 , t3 ]: At the beginning of this stage, diode Db2 is reverse biased, and diode Db1 is also reverse biased. Even though a gating signal is applied to switch S1 , there is no current flowing through it. Switch S1 remains turned off as well. Thus, the current through Lb becomes null, and there is no power transfer from the input source to the load. Output capacitor Co provides energy to the load instead. This stage finishes when switch S2 is turned on. Fourth stage [t3 , t4 ] [Fig. 9(c)] and fifth stage [t4 , t5 ] [Fig. 9(d)]: They are identical to the third and fourth stages in OMCCM, respectively. Sixth stage [t5 , t6 ]: This stage is identical to the third one. 3) CRM: The analysis of the CRM is based on the study developed for the previous conduction modes and is required so that the static characteristic of the converter operating in OM is determined. The current and voltage waveforms regarding the boost inductor are shown in Fig. 12. In this case, the minimum current through Lb is null, i.e., the current through Lb is equal to zero for a single time instant. The current ripple through Lb is then equal to the maximum current IM .

Fig. 13. Comparison between static gain curves. (a) Conventional boost converter. (b) Boost converter based on the 3SSC in OM.

4) Output Characteristic of the Converter: The static gain expressions for the converter operating in CCM, DCM, and CRM are given, respectively, by V0 1 = Vi(rect.) 1−D (2 · D − 1)2 +2 = γ 1 4 √ = = 1 − Dcrit 1± 1−8·γ

GCCM_OM =

(11)

GDCM_OM

(12)

GCRM_OM

(13)

where γ=

2 · Lb · Io . Vi(rect.) · Ts

(14)

Analogous to the NOM, the static gain in CCM is the same as that of the conventional boost converter. From (11)–(13), it is possible to determine the static gain of the proposed converter operating at D > 0.5, as the generic curves are shown in Fig. 13. Analogous to the conventional boost converter, the output voltage is dependent on the load current in DCM, and this operating region must be avoided. It is worth to mention that the maximum static gain in CRM occurs at γ = 0.0625 and D = 0.75 for the proposed converter [Fig. 13(b)]. Considering

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TABLE I D ESIGN S PECIFICATIONS

III. D ESIGN P ROCEDURE The specifications of the converter are listed in Table I and were used in the implementation of an experimental prototype. Some important calculations are performed in order to evidence the loss mechanism of the converter. It is also worth to mention that both conduction and commutation losses are estimated under rated load condition.

Fig. 14. Ripple current through the boost inductor in OM.

the classic boost converter [Fig. 13(a)], the maximum gain in CRM is verified when γ = 0.25 and D = 0.5. In practical terms, it means that the CCM region is wider for the proposed converter. Moreover, for a given operating point, the boost inductance calculated for the proposed converter becomes one-fourth of that required for the classic boost converter. Therefore, these are distinct advantages of the 3SSC boost topology operating in OM. 5) Filter Elements: The ripple current through the boost inductor (ΔILb ) is given as ΔILb =

(2 · D − 1) · (1 − D) · Ts · Vo . 2 · Lb

(15)

Expression (15) can be normalized so that the maximum ripple current is obtained as β=

2 · Lb · ΔILb = (2 · D − 1) · (1 − D). Ts · Vo

(2 · D − 1) · (1 − D) · Ts · Vo Ts · Vo =β· . 2 · ΔILb 2 · ΔILb

Ts · Vo . 16 · ΔILb

(17)

(18)

The critical inductance, whose value assures operation in CCM, is given by Lcrit =

Vi(rect.) · Ts . 32 · Io

(19)

The output capacitor can be determined as C≥

1 Io · (2 · D − 1) · . 2 ΔVo · fs

400 = 1.286. α= √ 2 · 220

(21)

The angle that represents the transition between OM and NOM is α θ1 = sin−1 = 0.6982 rad. (22) 2 The output current is Io =

Po 1000 = 2.5 A. = Vo 400

(23)

B. Boost Inductor

For the maximum ripple current, the inductance can be obtained by Lb =

Parameter α is the ratio between the output voltage and the peak input voltage and calculated as

(16)

Expression (16) is plotted in Fig. 14, where one can see that the maximum ripple current occurs at D = 0.75 and β = 0.125. By choosing arbitrarily the ripple current, the boost inductance can be determined as Lb =

A. Preliminary Calculation

(20)

The boost inductance is given by (18) as Lb =

400 ∼ = 630 μH. 16 · 1.325 · 30 · 103

(24)

The rms and peak currents through the boost inductor are given respectively by √ √ 2 · α · Io 2 · 1.286 · 2.5 = = 4.686 A (25) ILb(rms) = η 0.97 ILb(pk) =

2 · 1.286 · 2.5 2 · α · Io = = 6.627 A. η 0.97

(26)

The core loss in the boost inductor can be obtained from 2 PLb(core) = ΔB 2.4 · KH · fLb + KE · fLb · Ve = 0.036 W (27) where ΔB = 0.04 is the magnetic flux variation, KH = 4 · 10−5 is the hysteresis loss coefficient, fLb = 2 · fs = 60 kHz is the operating frequency of the boost inductor, KE = 4 · 10−5 is the eddy-current loss coefficient, and Ve = 42.5 cm3 is the core volume.


The copper loss in the boost inductor is given by PLb(copper) =

ρ · lt · NLb ·

2 ILb(rms)

nLb · Sf

= 0.976 W

(28)

where ρ = 2.078 · 10−6 Ω · m is the copper resistivity at 70 ◦ C, lt = 11.6 cm is the average length of one turn, NLb = 30 is the number of turns of the boost inductor, nLb = 5 is the number of wires in parallel, and Sf = 0.003255 cm is the cross-sectional area of copper wire AWG22. C. Autotransformers

MOSFET 5015VBR manufactured by advanced power technology was then chosen as the main switch, whose characteristics are as follows: drain-to-source voltage VDS = 500 V, diode forward voltage VS(F ) = 1.3 V, drain current ID = 32 A, onresistance RDS(on) = 0.15 Ω, rise time tr = 14 ns, and fall time tf = 11 ns. The conduction loss regarding each main switch is 2 PS1(cond.) = VS1(F ) · IS1(avg) +RDS(on) · IS1(rms) = 1.539 W. (38) The switching loss during turn-on and turn-off for a single switch is

The maximum voltage across the windings is VT 1

Vo = 200 V. = 2

(29)

The rms and peak currents through transformer T1 are given respectively by √ √ 2 · α · Io 2 · 1.286 · 2.5 IT 1(rms) = = = 2.343 A (30) 2·η 2 · 0.97 1.286 · 2.5 α · Io IT 1(pk) = = = 3.314 A. (31) η 0.97 The core loss in each autotransformer can be obtained from PT 1(core) = ΔB 2.4 · KH · fT 1 + KE · fT2 1 · Ve = 1.719 W (32) where ΔB = 0.15 is the magnetic flux variation, KH = 4 · 10−5 is the hysteresis loss coefficient, fT 1 = 2 · fs = 60 kHz is the operating frequency of the transformer, KE = 4 · 10−10 is the eddy-current loss coefficient, and Ve = 42.5 cm3 is the core volume. The copper loss in the windings of transformer T1 is given by PT 1(copper) =

2 · ρ · lt · NT 1 · IT2 (rms) nT 1 · Sf

= 0.976 W

(33)

where ρ = 2.078 · 10−6 Ω · m is the copper resistivity at 70 ◦ C, lt = 11.6 cm is the average length of one turn, NT 1 = 24 is the number of turns of the 1:1 transformer, nT 1 = 2 is the number of wires in parallel, and Sf = 0.003255 cm is the crosssectional area of copper wire AWG22. D. Main Switches

PS1(sw.) =

fs · (tr + tf ) · IS1(avg) · VS1 = 0.118 W. (39) 2

E. Boost Diodes and Antiparallel Diodes The reverse voltage across one boost diode is VDb1 = Vo = 400 V.

(40)

The average current IDb1(avg) , the rms current IDb1(rms) , and the peak current IDb1(pk) through the diode are given, respectively, by α · Io = 0.828 A 4·η √ α · Io = 1.461 A = 2·η

IDb1(avg) =

(41)

IDb1(rms)

(42)

IDb1(pk) =

α · Io = 3.314 A. η

(43)

Diode MUR460 was then chosen as the boost diode, whose characteristics are as follows: reverse voltage VD(rev.) = 500 V, forward voltage VD(F ) = 1.28 V, average forward current IF = 40 A, and reverse-recovery time trr = 75 ns. Estimating the intrinsic resistance of the diode from the curves given in the datasheet as RD = 33 mΩ, the conduction loss regarding each boost diode becomes 2 = 1.13 W. PDb1 = VDb1(F ) · IDb1(avg) + RDb1 · IDb1(rms) (44)

The switching losses regarding the boost diodes are given as

The threshold voltage across one main switch is VS1 = Vo = 400 V.

(34)

The average current IS1(avg) , the rms current IS1(rms) , and the peak current IS1(pk) through the switch are given, respectively, by −α · Io sin(α) · = −0.787 A η (π · α) (2 · α − sin(α)) α · Io · = 1.855 A = 2·η α α · Io = 3.314 A. = η

IS1(avg) =

(35)

IS1(rms)

(36)

IS1(pk)

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(37)

PS1(sw.) =

1 VD(F )P − VD(F ) · IDb1(avg) · trise · fs 2 + VDb1 · Qrr · fs

= 0.016 W

(45)

where VD(F )P = 1.3 V is the maximum value assumed by the forward voltage, trise = 1.5 ns is the rise time of the current through the diode, and Qrr = 1.355 nC is the amount of charge stored in the intrinsic capacitance of the boost diode. Switching losses regarding the antiparallel diodes of the main switches are not supposed to be neglected and were estimated as 0.248 W for each component by using (45).

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Fig. 15. Experimental prototype. TABLE II P OWER S TAGE E LEMENTS

IV. E XPERIMENTAL R ESULTS Numerous ac–dc boost-based topologies have been employed over the years for PFC applications, where low-distorted input currents and near-unity-PF operation are desired issues. Moreover, several dedicated control techniques have also been proposed. Typical strategies are hysteresis control [21], average-current-mode control [22], and peak current control [23]. More recently, on-cycle control [24] and self-control [25] have also been employed. To emulate the behavior of a pure resistance, averagecurrent-mode control is one of the most popular techniques mainly due to the availability of dedicated commercial ICs [22] and will be chosen for this work. An experimental prototype was built, whose picture is shown in Fig. 15. The converter was designed according to the parameters listed in Table I, and the components specified in Table II were used. PFC is shown in Fig. 16, where it is possible to notice the regions in which the duty cycle is less than 0.5 or greater than 0.5, as predicted by Fig. 2. When the output power is increased from 650 W to 1 kW in Fig. 16(b), the harmonic content of input current Ii is slightly increased. At rated power, the total harmonic distortion of the input current (T HDI ) is 12.012%, and the PF is 0.992. This occurs due to the existent asymmetry in the gating signals that drive the main switches. Moreover, tradeoffs have to be made between reduced harmonic content of the input current and regulated output voltage when designing the control system of the converter. In order to verify if the proposed converter is in compliance with standard IEC 61000-3-2, the harmonic content of the current in Fig. 16(b) was compared with that established for

Fig. 16. Input voltage and input current. (a) Vi = 160 V and Po = 650 W. (b) Vi = 220 V and Po = 1 kW. TABLE III L IMITS I MPOSED BY S TANDARD IEC 61000-3-2 FOR C LASS -A E QUIPMENT

class-A equipment. According to Table III, the limits imposed by the aforementioned standard are strictly respected. Fig. 17 shows a comparison between the input current and the current through one of the main switches, namely, IS1 , considering an appropriate scale. First, one can see that the peak current through the switch is half that of the input current. Moreover, it is possible to notice that, depending on the input voltage half cycle, the current flows through either the main switch or the antiparallel diode. That is, the MOSFETs operate at high frequency according to the pulsewidth modulation, while the diodes operate at low frequency. The same behavior is expected for the remaining switches. It is worth to mention that switches S1 −S3 are driven with the same gating signal, while


Fig. 17. Input current and current through switch S1 .

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Fig. 19. Current and voltage waveforms of boost diode Db1 .

Fig. 20. Efficiency as a function of the output power.

The experimental prototype was evaluated over a wide load range, and the efficiency curve of the converter operating at 30 kHz is shown in Fig. 20. Energy transfer from the source to the load occurs during almost the entire switching period for the 3SSC topology. On the other hand, in the conventional boost converter, it does only occur during part of the switching period, namely, when the main switch is off and the output capacitor is charged. It certainly contributes to the reduction of the current peak in the switches, causing efficiency to increase. The efficiency is higher than 95% over the entire output power range, demonstrating the merit of the proposed converter. This is not observed in typical boost topologies that are not based on the 3SSC due to the aforementioned reasons. V. C ONCLUSION Fig. 18. Currents through switches S1 and S2 . (a) NOM (D < 0.5). (b) OM (D > 0.5).

switches S2 −S4 are driven by a given gating signal which is 180◦ phase shifted from the first one. The detailed view of the currents through main switches S1 and S2 is shown in Fig. 18, where operation in NOM and OM becomes clear. Good current sharing between the switches is also verified. The current and voltage waveforms regarding the boost diode operation are shown in Fig. 19, where it can be seen that the aforementioned waveforms are in accordance with the theoretical analysis.

A bridgeless single-phase boost converter based on the 3SSC has been presented. In this approach, the benefits of both bridgeless and three-state cell are incorporated to the converter. In the bridgeless topology, conduction losses are minimized because the current always flows through two power semiconductors in series instead of three as in the conventional boost converter. When the 3SSC is employed, the current is distributed among the semiconductors. Furthermore, only part of the energy from the input source flows through the active switches, while the remaining part is directly transferred to the load without being processed by these switches, i.e., this energy is delivered to the load through passive components, such as the diodes and the transformer windings.

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The proposed topology can be seen as the association of the converter introduced in [9] and the interleaving technique, since it can be extended to a generic number of legs per winding of the autotransformers. Despite the increase in the number of semiconductors, the voltage and current levels in these devices are reduced, enabling the use of inexpensive switches and simplified command circuits because the isolated drive is not required. In front of these characteristics, its application is recommended for high power levels, analogous to the interleaved boost converter. In addition, the overall losses are distributed among all semiconductors, reducing the heat sink efforts. The reactive components operate with twice the switching frequency, with significant reduction in weight and volume of such components. Considering the operation in NOM (D < 0.5) and the same ratings, the following characteristics can be addressed to the 3SSC-based converter if compared with the conventional boost topology. 1) It has increased number of semiconductor elements. 2) The operating area in CCM is wider. 3) The ripple current through the boost inductor is reduced, as well as the currents through the switches. 4) The reactive elements are designed for twice the switching frequency, causing the required critical inductance to be smaller, for instance. 5) Only 50% of the power is delivered to the load through the main switches due to the magnetic coupling between the transformer windings. The same analysis can be performed for the converter in OM (D > 0.5), as the following issues result. 1) The input current is continuous, while the current through the output stage, composed of the output capacitor in parallel with the load, is discontinuous. 2) The operating area in DCM is narrower. 3) The maximum ripple current through the boost inductor is lower. 4) The size of reactive elements is reduced because they are designed for twice the switching frequency. 5) The current ripple at the point that represents the transition between NOM and OM (D = 0.5) is almost null. R EFERENCES [1] Amendments for Equipment With AC Mains Power: Electromagnetic Compatibility (EMC)—Part 3-2: Limits—Limits for Harmonic Current Emissions (Equipment Input Current ≤ 16 A per Phase), IEC 61000-32, 1995. [2] IEEE Recommended Practices and Requirements for Harmonic Control in Electrical Power Systems, IEEE Std. 519-1992, 1993. [3] W. Y. Choi, J. Kwon, E. H. Kim, J. J. Lee, and B. H. Kwon, “Bridgeless boost rectifier with low conduction losses and reduced diode reverserecovery problems,” IEEE Trans. Ind. Electron., vol. 54, no. 2, pp. 769– 780, Apr. 2007. [4] J. M. Kwon, W. Y. Choi, and B. H. Kwon, “Cost-effective boost converter with reverse-recovery reduction and power factor correction,” IEEE Trans. Ind. Electron., vol. 55, no. 1, pp. 471–473, Jan. 2008. [5] F. L. Tofoli, E. A. A. Coelho, L. C. de Freitas, V. J. Farias, and J. B. Vieira, Jr., “Proposal of a soft-switching single-phase three-level rectifier,” IEEE Trans. Ind. Electron., vol. 55, no. 1, pp. 107–113, Jan. 2008. [6] Y. Jang and M. M. Jovanovic, “Interleaved boost converter with intrinsic voltage-doubler characteristic for universal-line PFC front end,” IEEE Trans. Power Electron., vol. 22, no. 4, pp. 1394–1401, Jul. 2007.

[7] D. J. Perreault and J. G. Kassakian, “Distributed interleaving of paralleled power converters,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 44, no. 8, pp. 728–734, Aug. 1997. [8] G. V. Torrico-Bascopé and I. Barbi, “Generation of a family of nonisolated DC–DC PWM converters using new three-state switching cell,” in Proc. IEEE Power Electron. Spec. Conf., 2000, vol. 2, pp. 858–863. [9] G. V. Torrico-Bascopé and I. Barbi, “A single phase PFC 3 kW converter using a three-state switching cell,” in Proc. Power Electron. Spec. Conf., 2004, vol. 5, pp. 4037–4042. [10] G. V. Torrico-Bascopé, S. A. Vasconcelos, R. P. Torrico-Bascopé, F. L. M. Antunes, D. S. de Oliveira, Jr., and C. G. C. Branco, “A high stepup dc–dc converter based on three-state switching cell,” in Proc. IEEE Int. Symp. Ind. Electron., 2006, pp. 998–1003. [11] G. V. Torrico-Bascopé, R. P. Torrico-Bascopé, D. S. de Oliveira, Jr., F. L. M. Antunes, S. V. Araújo, and C. G. C. Branco, “A generalized high voltage gain boost converter based on three-state switching cell,” in Proc. 32nd Annu. Conf. Ind. Electron., 2006, pp. 1927–1932. [12] S. V. Araújo, R. P. Torrico-Bascopé, G. V. Torrico-Bascopé, and L. Menezes, “Step-up converter with high voltage gain employing threestate switching cell and voltage multiplier,” in Proc. Power Electron. Spec. Conf., 2008, pp. 2271–2277. [13] R. P. Torrico-Bascopé, C. G. C. Branco, G. V. Torrico-Bascopé, C. M. T. Cruz, F. A. A. de Souza, and L. H. S. C. Barreto, “A new isolated DC–DC boost converter using three-state switching cell,” in Proc. Appl. Power Electron. Conf. Expo., 2008, pp. 607–613. [14] R. A. Câmara, C. M. T. Cruz, and R. P. Torrico-Bascopé, “Center tapped preregulator based on three-state switching cell for UPS applications,” in Proc. Power Electron. Spec. Conf., 2008, pp. 2441–2446. [15] R. A. Câmara, C. M. T. Cruz, and R. P. Torrico-Bascopé, “Boost based on three-state switching cell for UPS applications,” in Proc. Brazilian Power Electron. Conf., 2009, pp. 313–318. [16] P. Klimczak and S. Munk-Nielsen, “Boost converter with three-state switching cell and integrated magnetics,” in Proc. Appl. Power Electron. Conf. Expo., 2009, pp. 1378–1383. [17] S. V. Araújo, R. P. Torrico-Bascopé, and G. V. Torrico-Bascopé, “Highly efficient high step-up converter for fuel-cell power processing based on three-state commutation cell,” IEEE Trans. Ind. Electron., vol. 57, no. 6, pp. 1987–1997, Jun. 2010. [18] R. A. Câmara, R. N. A. L. Silva, G. A. L. Henn, P. P. Praça, C. M. T. Cruz, and R. P. Torrico-Bascopé, “Voltage doubler boost rectifier based on three-state switching cell for UPS applications,” in Proc. Brazilian Power Electron. Conf., 2009, pp. 458–463. [19] R. A. Câmara, P. P. Praça, C. M. T. Cruz, R. P. Torrico-Bascopé, C. E. A. Silva, D. S. de Oliveira, Jr., and L. H. S. C. Barreto, “Threephase voltage doubler rectifier based on three-state switching cell for uninterruptible power supply applications using FPGA,” in Proc. Appl. Power Electron. Conf. Expo., 2010, pp. 837–843. [20] R. Martinez and P. N. Enjeti, “A high-performance single-phase rectifier with input power factor correction,” IEEE Trans. Power Electron., vol. 11, no. 2, pp. 311–317, Mar. 1996. [21] J. W. Lim and B. H. Kwon, “A power factor controller for single-phase PWM rectifiers,” IEEE Trans. Ind. Electron., vol. 46, no. 5, pp. 1035– 1037, Oct. 1999. [22] P. C. Todd, UC3854 Controlled Power Factor Correction Circuit Design. Merrimack, NH: UNITRODE, 1999. [23] L. Rossetto, G. Spiazzi, and P. Tenti, “Control techniques for power factor correction converters,” in Proc. PEMC, Sep. 1994, pp. 1310–1318. [24] K. M. Smedley and S. Cuk, “One-cycle control of switching converters,” IEEE Trans. Power Electron., vol. 10, no. 6, pp. 625–633, Nov. 1995. [25] D. Borgonovo, J. P. Remor, I. Barbi, and A. J. Perin, “A self-controlled power factor correction single-phase boost pre-regulator,” in Proc. IEEE 36th Power Electron. Spec. Conf., 2005, pp. 2351–2357.

Juan Paulo Robles Balestero was born in Jales, São Paulo, Brazil, on February 20, 1978. He received the B.Sc. and M.Sc. degrees in electrical engineering from the State University of São Paulo (UNESP), Ilha Solteira, Brazil, in 2004 and 2006, respectively. He is currently a Professor with the Federal Institute of Education, Science, and Technology of Santa Catarina, Chapecó, Brazil. His research interests include dc–dc converters and converter topologies.


Fernando Lessa Tofoli was born in São Paulo, Brazil, on March 11, 1976. He received the B.Sc., M.Sc., and Ph.D. degrees in electrical engineering from the Federal University of Uberlândia, Uberlândia, Brazil, in 1999, 2002, and 2005, respectively. He is currently a Professor with the Federal University of São João del-Rei, São João del-Rei, Brazil. His research interests include power-quality-related issues, high-power-factor rectifiers, and soft switching techniques applied to static power converters.

Rodolfo Castanho Fernandes (M’05) was born in Álvares Machado, São Paulo, Brazil, in 1986. He received the B.S. and M.Sc. degrees in electrical engineering from the State University of São Paulo (UNESP), Ilha Solteira, Brazil, in 2008 and 2010, respectively. He is currently an R&D Electronic Engineer with Jacto S/A, Pompéia, Brazil. His research interests include onboard power electronic applications, multipulse converters, active power factor correction techniques, and power quality. Mr. Fernandes has been a member of the Brazilian Power Electronics Society (SOBRAEP) since 2005.

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Grover Victor Torrico-Bascopé (M’04) received the B.Sc. degree in electrical engineering from San Simón University, Cochabamba, Bolivia, in 1993 and the M.Sc. and Dr. degrees in electrical engineering from the Federal University of Santa Catarina, Florianópolis, Brazil, in 1996 and 2001, respectively. Since July 2009, he has been a Senior Design Engineer with GTB Power Electronics Research and Technology AB, Kista, Sweden, where he is a Consultant and is offering new high-efficiency (HE) circuit topologies to the power electronic industry. He has published more than 20 technical papers and is the holder of two patents. His main research areas are in industrial power electronics and creating new platforms with HE topologies for high-power and green energy applications.

Falcondes José Mendes de Seixas was born in Jales, São Paulo, Brazil, in 1965. He received the B.S. degree in electrical engineering from the Engineering School of Lins, Lins, Brazil, in 1988 and the M.S. and Ph.D. degrees in electrical engineering from the Federal University of Santa Catarina, Florianópolis, Brazil, in 1993 and 2001, respectively. He is currently an Assistant Professor with the Department of Electrical Engineering, State University of São Paulo (UNESP), Ilha Solteira, Brazil. His research interests include power factor correction, switching-mode power supplies, and multipulse transformer applications.