Practical Medium Voltage Converter Topologies for High Power ...

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successfully in the industrial applications for high power drives [3]. A simplified schematic of a medium voltage drive based on a NPC inverter and a photograph.

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Practical Medium Voltage Converter Topologies

Practical Medium Voltage Converter Topologies for High Power Applications Peter K. Steimer

Madhav D. Manjrekar

R&D Drives & Power Electronics ABB Industrie AG 5300 Turgi, Switzerland E-mail: [email protected]

R&D Power Electronics Systems ABB Industrial Systems, New Berlin, WI 53151-2858, USA E-mail: [email protected]

Multilevel power conversion has been receiving increasing attention in the past few years for high power applications [1]. Numerous topologies and modulation strategies have been introduced and studied extensively for utility and drive applications in the recent literature. These converters are suitable in high voltage and high power applications due to their ability to synthesize waveforms with better harmonic spectrum and attain higher voltages with a limited maximum device rating. Trends in power semiconductor technology indicate a trade-off in the selection of power devices in terms of switching frequency and voltage sustaining capability. New multi-level, high power converter topologies have been proposed using a hybrid approach involving Integrated Gate Commutated Thyristors (IGCT) and Insulated Gate Bipolar Transistors (IGBT) operating in synergism. This paper is further developing and optimizing this approach presenting a hybrid ninelevel inverter operating at a 4160 V system voltage. Excellent current and voltage waveforms can be achieved even in weak network conditions. Additionally it is shown, that the multi-level conversion system can further be simplified by utilizing series connected H-bridges without the need of supply transformers and rectifiers.

applications [1]. Numerous topologies and modulation strategies have been introduced and studied extensively for utility and drive applications in the recent literature. These converters are suitable in high voltage and high power applications due to their ability to synthesize waveforms with better harmonic spectrum and attain higher voltages with a limited maximum device rating.

Abstract-

In the family of multilevel inverters the three-level topology, called Neutral Point Clamped (NPC) inverter, is one of the few topologies that has received a reasonable consensus in the high power community [2]. These NPC inverters have also been implemented successfully in the industrial applications for high power drives [3]. A simplified schematic of a medium voltage drive based on a NPC inverter and a photograph of its industrial implementation is presented in Figures 1 and 2.

IM

Figure 1: Simplified schematic of the industry-standard medium voltage drive based on NPC inverter.

I. INTRODUCTION Multilevel power conversion has been receiving increasing attention in the past few years for high power

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As may be seen from Figure 1, the conventional three-level inverter comprises four switches per phase with a diode clamp connected to the mid-point of the dc

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link. By closing two of the four switches, the load can be either connected to the top, middle or bottom of the dc link, thereby generating a three-level voltage waveform at the phase leg output. The LC sine filter connected at the output is used to filter out the high

Figure 2: Photograph of the commercially available medium voltage drive based on NPC inverter. frequency switching components in the output voltage. The dc link capacitors are charged with a twin diodebridge rectifier configuration. The ∆/Y/∆ phase-shifting transformer feeding the diode bridges generates a twelve-pulse current waveform at the utility side. This transformer also converts the utility voltage to needed input voltage level.

As shown in Figure 3, the output of the NPC inverter is directly connected through an LCL filter to the 4160V utility network. Optionally the utility side reactor can be replaced by a feeder transformer which adjusts to higher utility voltages by employing an appropriate turns-ratio. The voltages on the dc link capacitors are maintained at their nominal values by drawing necessary real power from the utility. One of the primary concerns for a successful operation is meeting the harmonic requirements given by IEEE 519-1992 even at very low short-circuit ratio. Hence, the LCL filter connected at the output of the inverter needs to be adequately sized as to meet the stringent current and voltage requirements. At multi-megawatt power levels, where inherently lower short circuit ratios are existing, the dimensioning of such filters becomes a important issue. To meet the IEEE 519 limits by means of an NPC inverter and an optimally sized filter the approach of optimized pulse patterns is used. By means of optimized pulse pattern low order harmonics are eliminated by the converter and the remaining high order harmonics are eliminated by the passive filter.

II. NPC-INVERTER AND PASSIVE FILTER The NPC medium voltage power circuit, including sine filter, as shown on the motor side, could also be used on the line side to serve as an active rectifier unit for high power industry (MV drives) and utility applications (interties, static VAr compensators). A simplified schematic of such a active rectifier topology, employed on the utility interface side, is shown in Figure 3.

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Figure 3: Active rectifier based on a NPC medium voltage IGCT inverter with passive filter

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To calculate the optimised pulse pattern the investigation is started with the following basic waveform (see Figure 4): φ

Result after using goniometric equations to separate each harmonic: U (ϕ 11 , ϕ 12 , ϕ 21 , ϕ 22 , ϕ 31 , ϕ 32 , ϕ 41 , ϕ 42 , ϕ 51 , t ) =

φ

4 Ud 1 ⋅ ⋅ ∑ ⋅ sin( n ⋅ π2 ) ⋅ π 2 n =1,3,5,.. n 2 ⋅ cos(n ⋅ ϕ 11 ) ⋅ cos(n ⋅ ωt ) +    − 2 ⋅ cos(n ⋅ ϕ 12 ) ⋅ cos(n ⋅ ωt ) +  + 2 ⋅ cos(n ⋅ ϕ 21 ) ⋅ cos(n ⋅ ωt ) +    − 2 ⋅ cos(n ⋅ ϕ 22 ) ⋅ cos(n ⋅ ωt ) +    + 2 ⋅ cos(n ⋅ ϕ 31 ) ⋅ cos(n ⋅ ωt ) +  − 2 ⋅ cos(n ⋅ ϕ ) ⋅ cos(n ⋅ ωt ) +  32   + 2 ⋅ cos(n ⋅ ϕ 41 ) ⋅ cos(n ⋅ ωt ) +    − 2 ⋅ cos(n ⋅ ϕ 42 ) ⋅ cos(n ⋅ ωt ) +  + 2 ⋅ cos(n ⋅ ϕ 51 ) ⋅ cos(n ⋅ ωt )   

Figure 4: Basic waveform for optimised pulse pattern investigations This waveform can be represented by means of its harmonic content as follows: 4 U 1 U (ϕ , t ) = ⋅ d ⋅ ∑ ⋅ sin(n ⋅ π2 ) ⋅ π 2 n =1,3, 5,.. n ⋅ [cos(n ⋅ (ωt + ϕ ) + cos(n ⋅ (ωt − ϕ )]

Based on this equation the basic equation for a waveform with multiple notches can be defined. The angles for a pattern with eight notches per half period, defined by nine free selectable switching angles is therefore defined as follows:

Derived general definition of the amplitude of the nth harmonic: 2 ⋅ cos(n ⋅ ϕ 11 ) +    − 2 ⋅ cos(n ⋅ ϕ 12 ) +  + 2 ⋅ cos(n ⋅ ϕ 21 ) +    − 2 ⋅ cos(n ⋅ ϕ 22 ) +  4 U 1 Uˆ n = ⋅ d ⋅ ⋅ sin(n ⋅ π2 ) ⋅ + 2 ⋅ cos(n ⋅ ϕ 31 ) +    π 2 n − 2 ⋅ cos(n ⋅ ϕ 32 ) +    + 2 ⋅ cos(n ⋅ ϕ 41 ) +  − 2 ⋅ cos(n ⋅ ϕ 42 ) +    + 2 ⋅ cos(n ⋅ ϕ 51 ) 

U (ϕ 11 , ϕ 12 , ϕ 21 , ϕ 22 , ϕ 31 , ϕ 32 , ϕ 41 , ϕ 42 , ϕ 51 , t ) = 4 Ud 1 ⋅ ⋅ ⋅ sin(n ⋅ π2 ) ⋅ π 2 n =∑ 1, 3 , 5 ,.. n

[cos(n ⋅ (ωt + ϕ 11 ) + cos(n ⋅ (ωt − ϕ 11 )] +    − [cos(n ⋅ (ωt + ϕ 12 ) + cos(n ⋅ (ωt − ϕ 12 )] +  + [cos(n ⋅ (ωt + ϕ 21 ) + cos(n ⋅ (ωt − ϕ 21 )] +    − [cos(n ⋅ (ωt + ϕ 22 ) + cos(n ⋅ (ωt − ϕ 22 )] +    + [cos(n ⋅ (ωt + ϕ 31 ) + cos(n ⋅ (ωt − ϕ 31 )] +  − [cos(n ⋅ (ωt + ϕ ) + cos(n ⋅ (ωt − ϕ )] +  32 32   + [cos(n ⋅ (ωt + ϕ 41 ) + cos(n ⋅ (ωt − ϕ 41 )] +    − [cos(n ⋅ (ωt + ϕ 32 ) + cos(n ⋅ (ωt − ϕ 42 )] +  + [cos(n ⋅ (ωt + ϕ 41 ) + cos(n ⋅ (ωt − ϕ 51 )]   

This basic equations to describe the harmonics have been used to calculate the optimised pulse pattern, with the target of controlling the fundamental voltage and eliminating the 5th, 7th, 11th, 13th, 17th, 19th, 23rd and 25th.

By using goniometric equations the upper equations can be transformed in an equation, where each harmonic is shown separately. Based on this equation each harmonic, including the fundamental can be described by one equation. The amplitude of the nth harmonic can be described in a general form:

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In Figure 5 the switching angles are shown for a modulation index range from of 0.91 (which is the point of operation with 10% utility undervoltage) upto 1.11 (which is the point of operation with 10% utility overvoltage). The nominal point of operation is assumed to be at a modulation index of 1.01. The maximum possible modulation index is 1.14, which assumes, that appr. 3% are available as control margin.

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1.5708

Practical Medium Voltage Converter Topologies



1.5 0.91

1.11

φ11_optk



φ12_optk



φ21_optk φ22_optk

The reactor on the inverter side is defined in such a way, that the inverter ripple current remains acceptable The utility side reactor should be selected to sufficiently limit any short-circuit currents The filter capacitor is selected in such a way, that the resonance frequency stays close to nine times the fundamental in every operation point.

1

φ31_optk φ32_optk φ41_optk

By means of the presented solution based on the combination of a NPC inverter, switching with a frequency corresponding to a PWM carrier close to 1kHz, and a passive filter the IEEE 519 requirements can be met. The total harmonic distortion of the utility current will in practice be in the range of 1.5 to 2%. See Figure 6 and 7.

0.5

φ42_optk φ51_optk

0.101

0 0

0.9 0.85

1 modk

1.1

0.05 1.15

Figure 5: Optimised switching angles as a function of the modulation index for elimination of the 5th, 7th, 11th, 13th, 17th 19th, 23rd and 25th harmonics This results in the following half DC voltage level for a 4160V output voltage: 1 4160V ⋅ 2 Udc _ igct _ N = ⋅ = 3365Vdc mod ind _ N 3 which has been the base for all the calculations.

2

0.04

50

sp_i1n IEEE519n 0.02

0

0

0

0

20

40

2

60

80

100 100

n

Figure 7: Utility current harmonics at the utility side meeting IEEE 519 requirements (SCR < 20)

1 0.015 2

0.5

50

0.01 sp_u1n

0 - 0.5

0

-1 0.005

0.01 0.015 Time [sec] U_wr [V]

0 0 2

0.02

20

40

60 n

80

100 100

Figure 8: Utility voltage harmonics meeting IEEE 519 requirements (SCR < 20). Total THD less than 1%.

i1R [A]

Figure 6: NPC inverter voltage waveform (red) and utility current waveform (blue) with passive filter For the dimensioning of the sine filter the following points have to be considered:

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0

In the case of a weak grid, as assumed in the investigations with a short-circuit ratio of 20, the voltage distortion seen at the utility connection is of

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interest too. The corresponding results for a SCR of 20 is shown in Figure 8.

simplified schematic of the power circuit of the proposed system is shown in Figure 11.

The NPC medium voltage IGCT inverter in combination with a passive filter can meet stringent IEEE 519 requirements. In regards of further improvements the elimination of any line-side capacitors (risk of resonance or active resonance control needed) and increased efficiency would be of significant interest. III. NPC-INVERTER AND ACTIVE FILTER Basics power semiconductor physics indicate a trade-off in the selection of power devices in terms of switching frequency and voltage sustaining capability [4]. Normally, voltage blocking capability of faster devices such as Insulated Gate Bipolar Transistors (IGBT) and the switching speed of high voltage latching devices such as Integrated Gate Commutated Thyristors (IGCT) [5] is found to be limited. The IGBT has its strength at 600V upto 1700V, with PWM frequencies in the range of multiple kHz. The IGCT, or any other medium voltage semiconductor, has its strength at 4500V upto 6000V with PWM frequencies up to 1kHz.

Figure 9: 6kV / 3000A IGCT – the preferred medium voltage power semiconductor

In Figure 9 a picture of a 6kV/3000A IGCT, the preferred switch for any medium voltage application, is shown. In Figure 10 a picture of a newest generation 1700V / 6 x 240A IGBT (LoPak5), the preferred switch for any low voltage application, is shown. Therefore the concept of the hybrid inverter is based on the combination of • a high-power NPC medium voltage IGCT inverter, mainly for power transfer, and • multiple low-power 2-level (Hbridge), low voltage IGBT inverters, mainly for series active filter tasks. To minimize the amount of components the hybrid converter, see [6] and [7] and its control strategies [8] have been further developed. As major improvement the supply section (transformer, rectifier) of the series low voltage IGBT inverters has been eliminated. It will be shown, that the voltage of the “flying” low voltage IGBT inverters can be controlled without the need of any additional supply circuit. A

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Figure 10: 1700A / 6 x 240A IGBT - the preferred low voltage power semi-conductor

Figure 11: Hybrid converter system with NPC based medium voltage IGCT inverter and low voltage IGBT based series active filters

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The equivalent vector space representation of the proposed hybrid multilevel inverter results by superimposing the vector spaces of the small H-bridge inverters (red thin-lined hexagons) on the vector nodes of the big three-level inverter (blue thick-lined hexagon). The corresponding result is shown in Figure 12.

Figure 12: Vector space representation of the proposed hybrid multilevel inverter 1

1

urefi carr1i

0.5

carr2i carr3i carr4i

For the following investigations it is assumed, that the DC-links of the series active filters are controlled by their own. The DC-Link of the NPC-inverter is controlled over the main transformer and may be the connection point for any other loads, i.e. the motor-side NPC-inverter of a medium voltage drive as shown in Figure 1. The DC link voltages of such a hybrid converter systems are configured in a 3:1 ratio (half NPC-voltages versus H-bridge voltages). To get the system running without any supply on the low voltage IGBT inverters, it has to be avoided, that any real power has to be transferred over the series IGBT inverters. This means, that in average all real power has to be transmitted over the larger NPC medium voltage IGCT inverter. To achieve this the DC-link voltage of the IGCT inverter has to be set high enough. The proposed DC-link voltages for the NPC inverter (half DC link voltage) and for the H-bridges are as follows: Udc _ igct _ N = 3000Vdc Udc _ igbt _ N = 1000Vdc Because the relevant DC-link voltage available to generate the needed output voltage is the sum of the NPC inverter voltages (3000 Vdc) and the IGBT inverter voltage (1000Vdc), this topology reduces actually the DC voltage requirements for the NPC medium voltage IGCT inverter (from 33365Vdc down to 3000Vdc) and requires a DC link voltage of 1000Vdc for the series 2-level 1700V IGBT inverters. The proposed hybrid approach therefore realizes a multilevel inverter using IGCTs and IGBTs operating at the optimal DC-link voltages in synergism.

0

In Figure 13 and 14 the hybrid modulation concept is shown for the nominal operation point with a modulation index of 0.85, referenced to 4000Vdc, with a carrier frequency of 39 times the fundamental frequency.

carr5i carr6i carr7i 0.5 carr8i

−1

1

0 0

0.005

0.01 t( i )

0.015 0.01667

Figure 13: Reference (with –12% 3rd harmonic) and carrier (f_carr = 39 x f1) for hybrid converter control

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1

0.05 2

0.04

50

uWR i uWR1 i

0

sp_i1n IEEE519n

0.02

0

0

1

0

0.005

0.01

0.015

t( i)

0

1

20

40

60

80

100 100

n

Figure 15: Utility current harmonics at the utility side meeting IEEE 519 requirements (SCR < 20), fcarr = 39 x f1

uIGCT i uIGBT i

0 2

1

0

0.005

0.01

0.015

0.015 2

t( i)

Figure 14: Created output voltage and selection of the IGCT and IGBT switching signals (lower Figure)

50

0.01 sp_u1n

This selection of the DC link voltages and the 3:1 ratio allows the realization of a 9-level inverter with the targeted benefits, that the passive filter can be eliminated and no supply for the active filter bridges is needed. Using appropriate modulation strategy, it will be possible to synthesize stepped waveforms with voltage levels 4kV, -3kV, -2kV, -1kV, 0, +1kV, +2kV, +3kV, +4kV using only one three-level inverters combined with 3 Hbridge converters, in total 24 power semiconductors. To control the DC-link voltages of the floating series IGBT inverters the 3rd harmonic included in the reference signal used for the modulation has to be controlled accordingly. By this simple means the hybrid converter system without supply of the IGBT DC-link can be controlled in a robust manner. If utilized in connection with a weak utility connection the interest in regards of created voltage distortion at the point of connection is increasing. In this respect the hybrid converter solution with the selected carrier frequency results in total THD for the utility voltage at the PCC of less than 3% at a SCR = 20.With this modulation concept of the hybrid inverter a THD of the utility current of appr. 2-3% will be achieved in practice (utility interfacing inductance = 0.12p.u.).

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0

0 0

0 2

20

40

60 n

80

100 100

Figure 16: Utility voltage harmonics at SCR=20. Total THD is less than 3%. By increasing the carrier frequency, the THD of the utility current can be further improved and the voltage harmonics at the point of common coupling can be moved to higher frequencies. If this higher harmonics in the utility voltage should be further reduced, this can easily be done by installing small RC circuits at the utility side of the utility interfacing inductance to create a high frequency, passive filter. The operation of the hybrid converter has been verified by laboratory tests [7] and by means of detailed system simulations. In Figure 17 the achieved results with a carrier frequency of fc=39 xf1 are shown. As can be seen, the capacitor voltage of the IGBT inverter (see u_IGBT) stays constant, without any supply.

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TABLE I: Comparison of topologies

1.5

SCR =20 1

NPC inverter and passive filter

0.5

η

I_THD

U_THD f_pwm

1)

1)

2)

1.5-2%

< 1.2%,

IGCT: Appr. 1080 Hz 98.7%

< 3%

IGCT: Appr. 600 Hz 99.2% IGBT: 2760 Hz (with f_carr = = 39xf1)

meets IEEE519

3)

0

NPC inverter and series active filter without supply

- 0.5 -1

2-3% meets IEEE519

- 1.5 0.015

U_igct [1] u_igbt [1]

0.02 Time [sec] i1R [1]

0.025

0.0

u1R [1]

Figure 17: System simulation results of a hybrid converter system at nominal operation point u1R: i_R: u_IGCT u_IGBT: f_igct: f_igbt:

REFERENCES

utility voltage phase R utility current phase R output voltage of IGCT inverter output voltage of series IGBT appr. 5 x f1 appr. 23 x f1

[1]

IV. CONCLUSIONS Based on the shown performance it can be concluded, that with the hybrid converter system • based on a powerful IGCT NPC-inverter • based on a series active filters realized by one IGBT H-bridge inverter per phase • without any supply of the series active filters a competitive line-friendly concept has been presented. It has been shown, that the hybrid converter system based on a NPC inverter with medium voltage power semiconductors (i.e. 6kV IGCTs) and with series IGBT inverters with low voltage IGBTs (i.e. 1700V IGBTs) can be controlled in such a manner, that • IEEE 519 requirements can be met, • low distortion of the utility voltage even in case of a weak grid can be achieved, • the supply infrastructure for the series IGBT converters can be avoided and • an excellent efficiency can be achieved.

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Remarks: 1) THD include sum up to the 100th harmonic, realistic values are given including control and limited DC-link energy storage influence. 2) As PWM frequency a number corresponding to the maximum device stress is given. 3) Losses of utility side inductance (transformer) not included

J.S. Lai and F.Z. Peng, “Multilevel converters – A new breed of power converters,” in Conf. Rec. IEEE-IAS Annu. Meeting, 1995, pp. 2348–2356. [2] A.Nabae, I. Takahashi, and H. Akagi, “A new neutral point clamped PWM inverter,” IEEE Trans. Ind. Applicat., vol. IA– 17, pp. 518–523, Sept./Oct. 1981. [3] Information about ACS1000 medium voltage drive product at http://www.abb.com/motor&drives [4] B.J. Baliga, Power Semiconductor Devices. Boston, MA: PWS, 1996. [5] P. Steimer, H.E. Gruning, J. Werninger, E. Carroll, S. Klaka, and S. Linder, “IGCT – A new emerging technology for high power low cost inverters,” in Conf. Rec. IEEE-IAS Annu. Meeting, 1997, pp. 1592–1599. [6] M.D. Manjrekar and T.A. Lipo, “A Hybrid Multilevel Inverter Topology for Drive Applications,” IEEE-APEC’98 Conference Proceedings, pp. 523-529, 1998. [7] M.D. Manjrekar, P.K. Steimer, and T.A. Lipo, “Hybrid multilevel power conversion system: A competitive solution for high– power applications,” IEEE Trans. Ind. Applicat., vol. IA–36, pp. 834–841, May/June 2000. [8] R. Lund, M.D. Manjrekar, P. Steimer, T.A. Lipo, “Control Strategies for a Hybrid Seven-level Inverter,” EPE’99, Switzerland.

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