Preface to the special issue of Solid State Electronics ...

Preface to the special issue of Solid State Electronics EUROSOI/ULIS 2017

This special issue is devoted to selected papers presented at the EuroSOI-ULIS2017 international conference, held in Athens on 3-5 April 2017. EuroSOI-ULIS2017 Conference was mainly devoted to Si devices, which constitute the basic building blocks of any microelectronic circuit. It included advanced Si technologies, novel nanoscale devices, advanced electronic materials and device architectures, mechanisms involved, test structures, substrate materials and technologies, modeling/simulation and characterization. Both CMOS and beyond CMOS devices were presented, covering the More Moore domain, as well as new functionalities in silicon-compatible nanostructures and innovative devices, representing the More than Moore domain (on-chip sensors, biosensors, energy harvesting devices, RF passives, etc.). The EuroSOI/ULIS 2017 Conference was attended by around hundred participants from all over the world. Both invited, oral and poster presentations were included in the program. The oral program was composed of twelve different sessions, with a total of six invited and 41 contributed presentations. The poster session with 27 papers was also a very important session of the Conference, with many interesting papers and fruitful discussions among participants. Other activities of the Conference included the best poster competition, the best micro- and nanoimage competition and the best oral paper award sponsored by the Sinano Institute (www.sinano.eu. The Welcome Reception was held in the neoclassical building “Kostis Palamas” in Athens, while the Conference Dinner in Dionysos Zonar’s restaurant, located in a prominent position on the outskirts of the Acropolis of Athens, having a panoramic view of the sacred rock of the Acropolis and the Odeon of Herodes Atticus (Herodion. The EuroSOI/ULIS2017 Conference was followed on the 4th and 5th of April 2017 by the NEREID Workshop, in which around 50 invited experts participated. NEREID is a support action funded by the European Commission on the “Nanoelectronics Roadmap for Europe: Identification and dissemination”. In this special issue a total of 14 papers were accepted for publication following the normal peer review process of Solid State Electronics. The list of accepted papers is as follows: 1. The Prospects of Transition Metal Dichalcogenides for Ultimately Scaled CMOS, Thiele et al. 2. A review of the Z2-FET 1T-DRAM memory: Operation mechanisms and key parameters, Cristoloveanu et al.

3. Indium Oxide Nanoparticles for RRAM devices compatible with CMOS back-end-offline, Leon Perez et al. 4. Detailed characterization of Si Gate-All-Around Nanowire MOSFETs at cryogenic temperatures, Boudier et al. 5. Kink effect in ultrathin FDSOI MOSFETs, Park et al. 6. Insight into carrier lifetime impact on band-modulation devices, Parihar et al. 7. Multi-Subband Ensemble Monte Carlo simulations of scaled GAA MOSFETs, Donetti et al. 8. Static and Low Frequency noise characterization of ultra-thin body InAs MOSFETs, Karatsoni et al 9. Silicon tunnel FET with average subthreshold slope of 55mV/dec at low drain currents, Narimari et al. 10. Out-of-Equilibrium Body Potential Measurements in Pseudo-MOSFET for Sensing Applications, Benea et al. 11. Three-dimensional vertical Si nanowire MOS capacitor model structure for the study of electrical versus geometrical Si nanowire characteristics, E. Hourdakis and A. G. Nassiopoulou 12. Electrical characteristics of silicon percolating nanonet-based Field Effect Transistors in the presence of dispersion, Cazimajou et al. 13. Second Harmonic Generation Characterization of SOI Wafers: Impact of Layer Thickness and Interface Electric Field, Damianos et al. 14. An innovative large scale integration of silicon nanowire-based field effect transistors, Legallais et al. I would like to acknowledge all authors for their valuable contribution to this Special Issue. The Guest Editor Androula G. Nassiopoulou