May 8, 2006 - 3. SEMICONDUCTOR LTD. Passive RFID tag examples. RFID tag Sticker. SmartCode. RFID tag Micro-chip. Plastic encapsulated RFID tag.
Process Platform for Passive RFID Tags Based on CMOS VLSI process May 08 2006 Ira Naot, Sharon Levin, Ishai Nave, Yossi netzer, Shye Shapira,
Passive RFID tag
Passive RFID tag examples
Passive RFID Challenges RFID tag Micro-chip
• “Answer-back” to an active reader
Tower Semiconductor Ltd
• Store information transmitted by reader
• Cost • Highly Integrated System
• Wide-spread use on low-cost products Low-cost is a must!!
• Power generation and Usage Rectifier
Antenna
( No power supply)
Plastic encapsulated RFID tag
Charge Pump
Intermec
Logic
Transponder switch
RFID tag Sticker SmartCode
• Integrated Non-volatile memory • Large voltage variations
De-Modulator NVM
• Harsh ESD Environment RFID tag on back of shipping label Symbol Technology
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Cost / Integration Challenge
Power Challenge – power supply
• Target price is few cents for complete tag
• Limited available power at antenna:
• Generate Vdd using in-chip charge-pump Vdd supply
• For efficient rectification:
• System-on-chip, one chip solution (reduce BOM, simplify assembly)
Must have Low Vf devices
• Fabrication based on standard CMOS VLSI process
Converted to DC Vf
• Use deep sub-micron process, reduce logic and NVM area, more dies per wafer, reduce die price
Chip Bulk
Typical Charge-Pump Schematic 5
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Standard Vt NMOSFET vs. Native NMOS Transistor
Standard Diode vs. Integrated-Schottky-diode Diode I/V Comparison
0.0012 0.001
•Solutions at Tower: •Integrated Schottky diode (See poster) •Native (Zero-Vt) MOSFET 7
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Power Challenge – Power usage •Optimized low-leakage devices for “state-holding” registers •Utilizing 0.18 micron devices for optimal Vdd range and low leakage
Std Vt Native M O SFET
5.0E-04
4.0E-04
0.0006
3.0E-04
[A ]
Id Id [A]
0.0008
[A /um
Current 2] 2] Current [A/um
Junction Diode Integrated Schottky
•Requirements •Must have low forward voltage •Maximize ratio of forward to reverse currents •Minimize parasitic capacitances (for minimal RF power dissipation) •Integrated in chip fabrication •No added process steps/masks •Challenge: •Standard CMOS devices have Vf > 0.5V
•Logic for low power, Allowed Vdd range of 1.0V to 2.2V
Id/Vg Curves, W /L=10/0.5, Vd=0.1V 6.0E-04
0.0014
SEMICONDUCTOR LTD.
Efficient Rectification Device Requirements
(Typically 50 to 500 µW)
•T.S.L. Meeting RFID challenge:
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2.0E-04
0.0004 0.0002
1.0E-04
0 0
0.2
0.4
0.6
0.8
1
0.0E+00
1.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Vg [V]
Applied bias [V]
0.18µm logic cells, Tower Semiconductor Ltd.
Data: Tower Semiconductor Ltd.
Data: Tower Semiconductor Ltd. 8
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Existing ESD solutions in VLSI
ESD Challenges in passive RFID
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Tower RFID platform •Custom Solution for RFID:
• Inherent risk of ESD in RFID tags: • Attached antenna • Plastic/paper sticker
To Internal Circuit
• Ideal ESD protection device: VLSI circuit of RFID tag
