17 May 2010 ... Patent. Jul. 26, 2011. Sheet 10 0f 11. US 7,987,338 B2. E390. E390. E20
anmweo .... performance DSP implementations may support paral.
US007987338B2
(12) United States Patent Doerr et a].
(54)
PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS USING SHARED MEMORY OF COMMUNICATION ELEMENTS
(56)
(US); Craig M. Chase, Austin, TX (US)
U.S. PATENT DOCUMENTS 4,739,476 A
4/1988 Fiduccia
(Continued) FOREIGN PATENT DOCUMENTS EP
European Search Report and Search Opinion for Application No.
Subject to any disclaimer, the term of this patent is extended or adjusted under 35
101645307, mailed Oct. 1,2010; 5 pages.
This patent is subject to a terminal dis claimer.
(21) App1.No.: 12/7s1,314
(Continued)
Sep. 9,2010
Related U.S. Application Data
A processing system comprising processors and the dynami
cally con?gurable communication elements coupled together in an interspersed arrangement. The processors each com prise at least one arithmetic logic unit, an instruction process
ing unit, and a plurality of processor ports. The dynamically con?gurable communication elements each comprise a plu
No. 10/602,292, ?led on Jun. 24, 2003, noW Pat. No.
rality of communication ports, a ?rst memory, and a routing engine. For each of the processors, the plurality of processor ports is con?gured for coupling to a ?rst sub set of the plurality
Provisional application No. 60/391,734, ?led on Jun.
26, 2002. Int. Cl.
G06F 15/76 G06F 15/80
(52) (58)
ABSTRACT
Continuation of application No. l2/028,565, ?led on Feb. 8, 2008, Which is a continuation of application
7,415,594.
(51)
(74) Attorney, Agent, or Firm *Meyertons Hood Kivlin KoWert & GoetZel, P.C.; Jeffrey C. Hood; Joel L. Stevens
(57) Prior Publication Data
US 2010/0228925 A1
(60)
Primary Examiner * Aimee J Li
May 17, 2010
(65)
(63)
5/1988
TX (US)
U.S.C. 154(b) by 0 days.
(22) Filed:
0266300
OTHER PUBLICATIONS
(73) Assignee: Coherent LogiX, Incorporated, Austin, Notice:
*Jul. 26, 2011
References Cited
(75) Inventors: Michael B. Doerr, Dripping Springs, TX (US); William H. Hallidy, Austin, TX (US); David A. Gibson, Austin, TX
US 7,987,338 B2
(10) Patent N0.: (45) Date of Patent:
(2006.01) (2006.01)
U.S. Cl. ............. .. 712/11; 712/15; 712/16; 712/225 Field of Classi?cation Search .................. .. 712/10,
of dynamically con?gurable communication elements. For each of the dynamically con?gurable communication ele ments, the plurality of communication ports comprises a ?rst subset of communication ports con?gured for coupling to a subset of the plurality of processors and a second subset of communication ports con?gured for coupling to a second subset of the plurality of dynamically con?gurable commu nication elements.
712/11,12,14,15,16,17,225; 710/52, 710/53, 54, 56, 58, 59 See application ?le for complete search history.
20\
24 Claims, 11 Drawing Sheets
US 7,987,338 B2 Page 2 US. PATENT DOCUMENTS 5,630,162 A 5,689,719 A
5/1997 Wilkinson et al. 11/1997 Miura et al.
Search Report and Search Opinion for Application No. 101689420 2211/2239667, mailed Oct. 8, 2010. 7 pages.
Karl-Erwin Grosspietsch and Erik Maehle; “Routing to Support Communication in Dependable Networks”; Proceedings of the 10th Euromicro Workshop on Parallel, Distributed and Network-based
OTHER PUBLICATIONS
Shashi Kumar, Axel Jantsch, Juha-Pekka Soininen, Martti Forsell,
Mikael Millberg, Johny Oberg, Kari Tiensyrja, and Ahmed Hemani; “A Network on Chip Architecture and Design Methodology”; Pro ceedings of the IEEE Computer Society Annual Symposium on VLSI, 2002; 8 pages.
Processing, Canary Islands, Spain, Jan. 9-11, 2002; 7 pages. Search Report and Search Opinion for Application No. 10166234 .4 2211/2237165, mailed Oct. 8, 2010. 7 pages. F. Capello and C. Germain; “Toward High Communication Perfor mance Through Compiled Communications on a Circuit Switched
Interconnection Networ ”; Proceedings of First IEEE Symposium, Raleigh, NC, Jan. 22-25, 1995; 10 pages.
US. Patent
Jul. 26, 2011
Sheet 1 0f 11
DCP
DCP
DCP
DCP
DCP
DCP
DCP
US 7,987,338 B2
DCP
DCP
DCC
DCP
DCP
DCP
DCP
DCP
DCP
DCP
DCP
DCP
FIG. 1
DCC
DCP
DCC
— DCP
DCC
DCP —
§CC DCP DCé — DCP
DCC
FIG. 2
DCP —
US. Patent
Jul. 26, 2011
Sheet 3 of 11
DCP
US 7,987,338 B2
/ 400
Address Ports 403
DCP
DCC Port Addresses Detected DCP
Input Ports 401
Output Ports _
402
Communication Controller
m
Routing Logic
DCC
Program Load Path DCC
43_5
Input Ports
Output
404
Latch
@ w
V
Input Registers
Output Registers
454
455
FIG. 4
Output Ports 405
US. Patent
Jul. 26, 2011
Sheet 4 0f 11
DCP ALU
DCP ALU
phase
phase
1
2
US 7,987,338 B2
DCP
DCP
X-BAR
X-BAR
DCP
DCP
WRITE to
READ from
WRITE to
READ from
WRITE to
READ from
SRAM
SRAM I SRAM I SRAM I SRAM | SRAM I P
' PHASE D
PHASE ' PHASE ' PHASE ' PHASE A B c D CLOCK CYCLE 500
FIG. 5
PHASE A
TIME
US. Patent
Jul. 26, 2011
Sheet 7 0f 11
US 7,987,338 B2
Con?gure pathway @
i
Configure nodes as
synchronous/ transparent m
i Transmit data word
Data word
M
Wait for clock
@
Propagate to next Yes
D66
Another transfer/same dest?
m
Yes
Another
transfer/different dest?
m
FIG. 8
