Q SiGe RF Transceiver

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The simplified schematic of the differential down- conversion mixer is shown on Fig. 4. The architecture of the mixer is based on the double-balanced Gilbert-cell.
A 5.2 GHz 3.3V I/Q SiGe RF Transceiver Jean-Olivier Plouchart, Herschel Ainspan, Mehmet Soyuer

Abstract A 5.2 GHz I/Q RF transceiver using a 0.5−µm SiGe BiCMOS technology is designed and measured. The receiver exhibits a 11.7 dB down-conversion gain, a DSB noise figure of 7.5 dB, an input IP3 of –11.2 dBm, and an amplitude imbalance of 0.33 dB for a 300 MHz IF. For the transmitter an up-conversion gain of 14.7 dB, an output 1dB compression point of –23 dBm, an amplitude imbalance of 0.5 dB, and a 7 GHz 3 dB bandwidth were measured. The power consumption is 122mW for the receiver and 114 mW for the transmitter at 3.3V power supply. Introduction In January 1997 the FCC allocated, 300MHz of bandwidth around 5 GHz, specifically dedicated for short range, highspeed digital communications using unlicensed devices. The successful implementation of such a system will require the availability of low-cost high performance transceivers operating in the 5.15-5.35 GHz band. Recently, a Si 5 GHz RF transceiver was reported using a classical heterodyne architecture (1). Another architecture, allowing potentially higher level of integration is the I/Q architecture. We report for the first time a 5.2 GHz I/Q RF transceiver. This RF transceiver uses SiGe technology. SiGe HBT BiCMOS Process Technology The 5.2 GHz I/Q RF transceiver was designed in IBM’s 200-mm SiGe BiCMOS technology without any process modification. This three level-metal (Al) technology features a Si/SiGe HBT with an emitter width of 0.5-µm and a cutoff frequency (fT) and maximum oscillation frequency (fMAX) in excess of 45 GHz and 60 GHz, respectively. Noise is also a very important parameter for telecommunications. The minimum noise figure (NFmin) is commonly used to characterize the noise performance of a technology. The minimum noise figure of the Si/SiGe HBT was measured using a source-pull automatic tuner system for different transistor geometries. As shown in Fig. 1, the minimum noise figure is close to that of a 0.5µm MESFET technology, and thanks to lower parasitics, is better than that of GaAs HBT technology (2, 3, 4, 5). The SiGe BiCMOS technology features also NMOS and PMOS devices with a nominal Leff of 0.35 µm, polysilicon and diffused resistors, high-density MOS and high-Q metal-insulator-metal (MIM) capacitors, varactor diodes and inductors (6). The substrate resistivity is about 10-20 Ω-cm.

Minimum Noise Figure (dB)

IBM T.J. Watson Research Center P.O. BOX 218, Yorktown Heights, NY 10598 Tel: (914) 945 –2607. Fax: (914) 945-1974 E-mail: [email protected]

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SiGe HBT (TEMIC) (3) SiGe HBT (IBM) [This Work]

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GaAs HBT (TRW) (2)

2 0.5um GaAs MESFET (TriQuint) (4)

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0.3um GaAs PHEMT (HP) (5)

0 0

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Frequency (GHz) Fig. 1 – Comparison of the minimum noise figure of different technologies.

Design of the I/Q RF transceiver As shown in Fig. 2, the chip integrates a differential LNA, two down-conversion mixers, two up-conversion mixers, a differential adder, an output buffer, four LO-buffers, and four IF buffers. The frequency synthesizer, the 90-degree phase-shifters, the power amplifier and the switch are external components. The results on the power transistor, the monolithic differential VCO, and on the high-speed radio system including baseband processing were previously reported (7, 8, 9). The transceiver can be used in two different ways. The first way is to use the image rejection property of the I/Q architecture by using a 90o IF phase shifter. The 0o and 90o IF signals are added after 90o phase shifting to reject the IF or RF image. The channel is then selected by a SAW filter, and a classical IF architecture can be used to convert the IF signal to baseband. The benefit of this architecture is that we do not need image rejection filters between the LNA and the down-conversion mixer, and between the up-conversion mixer and the power amplifier, since the image rejection is done by the I/Q architecture. The second way is to use it as the RF front-end of a Weaver transceiver (10, 11). In that case, an I/Q IF conversion to baseband stage is required for each RF conversion to IF stage. The benefit of this architecture is that no 90o IF phase-shifters are needed, since the imagerejection is done at baseband. Also, very high-level of integration can be achieved if on-chip active filtering can be implemented (10). In that case, only the external front-end band-pass filter is needed.

LO

Oo

IF

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9Oo

Integrated on Chip

PAmp

IF

PLL LO

Switch

0/90 LO IF

9Oo 300 MHz

LNA

Fig. 4 – Schematic of the differential down-conversion mixer

Oo IF LO

Fig. 2 – Schematic of the 5.2 GHz RF transceiver.

The simplified schematic of the LNA is shown on Fig. 3. It is a fully differential topology, based on cascode architecture. The LNA is biased with a total current of only 4 mA. To peak the gain and get enough voltage headroom for high linearity, inductors were used for the collector loads. The input differential pair was degenerated to improve the linearity of the LNA. Instead of emitter resistors, inductors were used to get better voltage headroom and noise figure. The emitter and input base inductors were also used to optimize the matching of the LNA (12, 13). The spiral inductors used have a Q of 8 around 5 GHz (14). The differential output of the LNA is connected to the differential inputs of both down conversion mixers through decoupling capacitors.

Fig. 3 – Schematic of the fully differential LNA.

The simplified schematic of the differential downconversion mixer is shown on Fig. 4. The architecture of the mixer is based on the double-balanced Gilbert-cell architecture. The total DC biased current for the Gilbert-cell is 6.3 mA. The input differential pair is degenerated by two emitter inductors to improve the linearity. The single ended input of the LO buffer is 50 ohms matched. The signal is first amplified then converted to a differential signal, so that only –10 dBm of input LO power is needed.

The output of the mixer is connected to the output emitter follower buffer through decoupling capacitors. The decoupling capacitor is large enough to achieve an 8 MHz cut-off frequency for the high-pass filter. For the I/Q transmitter part, both up-conversion mixers and output buffer are shown on Fig. 5. The architecture of the mixers is also based on Gilbert-cell, but the input differential pair is resistor degenerated instead of inductor degenerated because on-chip inductors do not have a high enough impedance at the IF frequency. The LO buffer and the IF buffer were designed to convert the single-ended input to differential signal and drive the Gilbert-cell and the differential pair respectively. The ouput buffer is a differential pair driving an on-chip 50Ω resistor to avoid multiple reflections.

Fig. 5 – Schematic of the differential up-conversion mixers and output buffer.

Layout and isolation of the I/Q RF transceiver The layout was also optimized for the electrical isolation between the LNA, the down-conversion mixers and the I/Q transmitter. A separate ground was used for each function. On chip decoupling capacitors were used for the decoupling of Vcc for each function. Also each function is surrounded by a ring of substrate contacts, itself surrounded by a ring of deep trench oxide.

Vcc

Gnd

Vcc

Gnd

only 0.33 dB at 5.2 GHz. The measured LO ouput power at the RF port was only –63.5 dBm thanks to the isolation techniques used. This is a single ended measurement, and the isolation should be even higher because of the differential architecture of the receiver. The power dissipation is 122 mW at 3.3 V power-supply. The measurements are summarized in Table 1.

150 µm

Substrate contact ring

Table 1 – Measured Receiver performance at 5.2 GHz, with an LO power of –10 dBm and an IF of 300 MHz.

Deep trench ring

Fig. 6 – Layout isolation techniques.

The width of the substrate contact ring is 10µm, and the spacing between each function is 150µm. The thickness of the deep-trench oxyde is 6µm. The chip integrates 10 spiral inductors, 218 bipolar transistors, and 199 resistors and capacitors, on a 2.07x2.77mm2 area. Most of the circuit is fully differential for improved noise rejection. Measurement results The measurements are done on-wafer. For the biasing of the circuit an eight-pin DC Cascade probe is used with low series inductor and 10 nF decoupling capacitor. For the receiver, one input of the LNA was connected to the signal generator while the other input was connected to a 50Ω termination. The single-ended input of the LO buffer was connected to another signal generator. One output of the IF buffer was connected to the spectrum analyzer. An input matching of –8.6 dB was measured at 5.2 GHz. A downconversion gain of 11.7 dB was measured for a 5.2 GHz RF and 300 MHz IF. For the linearity, an input 1dB compression of –18.5 dBm (Fig. 7), and an input third order intercept point of –11.2 dBm were measured.

Conversion Gain [dB]

12

11.5

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10 -35

-30

-25

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Input powe r [dBm]

Fig. 7 – Down conversion gain versus input power for the receiver.

The Double Side Band noise figure of the receiver was measured using a noise figure meter. Despite the 50Ω resistor on one of the input of the LNA a DSB noise figure of only 7.5 dB was measured. As predicted by simulations, a 3dB improvement can be obtained by using a 180o phase shift balun power divider. This power divider can be designed on a board. The measured amplitude imbalance at 300 MHz between the two down conversion mixers was

Down-Conversion Gain [dB] DSB Noise Figure [dB] S11 [dB] IP1dB [dBm] IIP3 [dBm] Amplitude Imbalance [dB] LO to RF isolation [dB] Pdc [mW] @ 3.3 V

11.7 7.5 -8.6 -18.5 -11.2 0.33 53.5 122

For the transmitter, all the measurements were done with a 300 MHz IF frequency and a –5 dBm input LO power (Table 2). The circuit exhibits an up-conversion gain of 14.7 dB, and a 3dB cut-off frequency of 7 GHz. This is 1.75 times higher than a previously reported I/Q transceiver using GaAs MESFET technology (15). The 5.2 GHz output 1-dB compression point is –23 dBm. The amplitude imbalance is 0.5 dB at 5.2 GHz. With an amplitude imbalance of 0.5 dB we can achieve a 30dB image rejection if the phase error is less than 1.5o (16). One of the difficulties of the on-wafer measurement of the I/Q transceiver, is to provide input and output signal through cables with good control on the phase and amplitude. At 5 GHz and in free space, a one degree phase-shift difference is equivalent to only 167µm, so we need a very good match between the two connections at the output of the 90o external LO phase shifter. Also the phase shifter itself is not perfect. The specifications for the phaseshifter used, are an amplitude balance of ±0.5 dB and a phase balance of ±5o. As shown on Fig. 8, we measured a 21.3dB image rejection on the network analyzer, due to phase errors and amplitude mismatches in the cables and phase-shifters. We can have a much better control with onboard phase shifter, and we expect to reach 30dB image rejection. Table 2 – Measured Transmitter performance at 5.2 GHz, with an LO power of –5 dBm and an IF of 300 MHz.

Up-Conversion Gain [dB] OP1dB [dBm] 3 dB Bandwidth [GHz] Amplitude Imbalance [dB] Image Rejection [dB] Plo @ RF port [dBm] Pdc [mW] @ 3.3 V

14.7 -23 7 0.5 21.3 (setup limited) -40 114

The LO output power is –40 dBm at the output RF port. The power consumption is 114 mW on a 3.3 V power-supply.

Acknowledgments The authors would like to acknowledge the SiGe technology group of IBM Microelectronics in Essex Junction, VT, and East Fishkill, NY for the chip fabrication. They wish to thank K. Jenkins, S. Subbanna, D. Harame, N. Cahoon, M. Oprysko, and B. Meyerson for their support and encouragement. References (1)

(2)

Fig. 8 – Spectrum analyzer measurement showing the rejection of the image at 5.8 GHz.

The chip microphotograph is shown in Fig. 9.

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(10) Fig. 9 – Microphotograph of the I/Q SiGe 5.2 GHz transceiver. Its dimensions are 2.07 mm x 2.77 mm.

Conclusion A 5.2 GHz I/Q RF transceiver in SiGe BiCMOS was presented. A down-conversion gain of 11.7 dB, a DSB noise figure of 7.5 dB, an IP1dB of –18.5 dBm, an IIP3 of –11.2 dBm, and an amplitude imbalance of 0.33 dB were measured at 5.2 GHz for the receiver. The LO to RF isolation is 53.5 dB thanks to layout techniques using separate grounds, guard rings and deep-trench. The power dissipation is only 122 mW from a 3.3 V power supply. The I/Q transmitter exhibits a 7 GHz bandwidth. An upconversion gain of 14.7 dB, an OP1dB of –23 dBm and an amplitude imbalance of 0.5 dB were measured at 5.2 GHz. An image rejection of 21.3 dB was measured by using external phase shifters. The image rejection was limited by the accuracy of the setup. The power consumption is only 122 mW for the I/Q receiver and 114 mW for the I/Q transmitter at 3.3 V power supply.

(11) (12)

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(15) (16)

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